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| author | Stefan Roese <sr@denx.de> | 2014-03-04 15:34:35 +0100 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-03-07 10:59:06 -0500 |
| commit | 345b77bacabb84a00c7508471ab560b452910240 (patch) | |
| tree | ebfd90c103d0129cf16b07912d2a86d2b75bae5d /board/amcc/sequoia/sdram.c | |
| parent | dc116bd6c4b5cb1caf6621f282ac5156d1509bef (diff) | |
| download | u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.zip u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.tar.gz u-boot-imx-345b77bacabb84a00c7508471ab560b452910240.tar.bz2 | |
ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/amcc/sequoia/sdram.c')
| -rw-r--r-- | board/amcc/sequoia/sdram.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 2c5a218..67640d7 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -26,14 +26,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); -#if defined(CONFIG_NAND_SPL) -/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133333333 -#endif - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void); ************************************************************************/ phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ - defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_SYS_RAMBOOT) ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); @@ -81,7 +72,7 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ +#endif /* #ifndef CONFIG_SYS_RAMBOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ |