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| author | Stefan Roese <sr@denx.de> | 2005-11-01 10:08:03 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2005-11-01 10:08:03 +0100 |
| commit | 57275b69c6cdb5ed37c4cdece3cda56487ca4b0c (patch) | |
| tree | 97ab5ef11ce24368bbc4d0a38f278b5c5d6b65f0 /board/amcc/ocotea | |
| parent | d9f2f5008c32c8373d68a4c8e14f50a469965a23 (diff) | |
| download | u-boot-imx-57275b69c6cdb5ed37c4cdece3cda56487ca4b0c.zip u-boot-imx-57275b69c6cdb5ed37c4cdece3cda56487ca4b0c.tar.gz u-boot-imx-57275b69c6cdb5ed37c4cdece3cda56487ca4b0c.tar.bz2 | |
Add support for Ocotea pass 3 with 440GX Rev. F
Patch by Stefan Roese, 01 Nov 2005
Diffstat (limited to 'board/amcc/ocotea')
| -rw-r--r-- | board/amcc/ocotea/ocotea.c | 9 | ||||
| -rw-r--r-- | board/amcc/ocotea/ocotea.h | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 5b28c3b..3926109 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -506,6 +506,15 @@ void fpga_init(void) } } + /* + * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset + */ + if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { + out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); + udelay(10000); + out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); + } + /* Turn off the LED's */ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h index 41bd450..95ce1fd 100644 --- a/board/amcc/ocotea/ocotea.h +++ b/board/amcc/ocotea/ocotea.h @@ -80,6 +80,7 @@ #define FPGA_REG2_EXT_INTFACE_MASK 0x04 #define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 #define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 +#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ #define FPGA_REG2_DEFAULT_UART1_N 0x01 #define FPGA_REG3 (CFG_FPGA_BASE + 0x03) #define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ |