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| author | Andy Fleming <afleming@freescale.com> | 2007-10-19 11:24:22 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-10-19 11:24:22 -0500 |
| commit | d4d1e9bee7c45ea8c513d3af697c864107f1c4d1 (patch) | |
| tree | 3cd7eba359e6729454f4fac5b96209eb959ecf72 /board/amcc/luan/luan.c | |
| parent | 1487adbdcf9594bb2eb686325a6f9540dad1b70a (diff) | |
| parent | 27d2b1ed216b457a66c17d38ce5ffdf3c2c32d1e (diff) | |
| download | u-boot-imx-d4d1e9bee7c45ea8c513d3af697c864107f1c4d1.zip u-boot-imx-d4d1e9bee7c45ea8c513d3af697c864107f1c4d1.tar.gz u-boot-imx-d4d1e9bee7c45ea8c513d3af697c864107f1c4d1.tar.bz2 | |
Merge branch 'denx'
Diffstat (limited to 'board/amcc/luan/luan.c')
| -rw-r--r-- | board/amcc/luan/luan.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7b16f8a..0067ce0 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -66,8 +64,6 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ - return 0; } @@ -79,7 +75,18 @@ int board_early_init_f(void) int misc_init_r(void) { volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + /* set modes of operation */ + x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | + EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; + /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ + x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; + + /* put Ethernet+PHY in reset */ + x->ethuart &= ~EPLD2_RESET_ETH_N; + udelay(10000); + /* take Ethernet+PHY out of reset */ + x->ethuart |= EPLD2_RESET_ETH_N; return 0; } |