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author | Minkyu Kang <mk7.kang@samsung.com> | 2010-02-06 17:20:09 +0900 |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2010-02-06 17:20:09 +0900 |
commit | bdaef38171c9ea030bae46b798aba4f430dcac18 (patch) | |
tree | 4da072aceaa42e7ff3ec9962f5d99a9ca667ace9 /board/amcc/kilauea | |
parent | ed44387f406ca0e695609270a1282e699111a945 (diff) | |
parent | c20a3c0bac909a0a1311eaafdec156b6a8686d46 (diff) | |
download | u-boot-imx-bdaef38171c9ea030bae46b798aba4f430dcac18.zip u-boot-imx-bdaef38171c9ea030bae46b798aba4f430dcac18.tar.gz u-boot-imx-bdaef38171c9ea030bae46b798aba4f430dcac18.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
cpu/arm_cortexa8/s5pc1xx/cache.c
include/configs/spear6xx.h
lib_ppc/reloc.S
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'board/amcc/kilauea')
-rw-r--r-- | board/amcc/kilauea/kilauea.c | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 8ce2445..646f431 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static int board_cpld_version(void) +{ + u32 cpld; + + cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); + if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { + /* + * Magic not found -> "old" CPLD revision which needs + * the "old" EBC configuration + */ + mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | + EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | + EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | + EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | + EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | + EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); + + /* + * Return 0 for "old" CPLD version + */ + return 0; + } + + /* + * Magic found -> "new" CPLD revision which needs no new + * EBC configuration + */ + return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; +} + /* * Board early initialization function */ @@ -209,6 +240,13 @@ int board_early_init_f (void) mtsdr(SDR0_PFC1, val); /* + * The CPLD version detection has to be the first access to + * the CPLD, so we need to make this access this early and + * save the CPLD version for later. + */ + gd->board_type = board_cpld_version(); + + /* * Configure FPGA register with PCIe reset */ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ @@ -280,7 +318,7 @@ int checkboard (void) puts(", serial# "); puts(s); } - putc('\n'); + printf(" (CPLD rev. %ld)\n", gd->board_type); return (0); } |