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authorStefan Roese <sr@denx.de>2008-03-11 13:52:25 +0100
committerStefan Roese <sr@denx.de>2008-03-15 07:22:15 +0100
commite4170e5a50c8110f792bc37472833ae669d69951 (patch)
treea62e632dcd5fd61c5268744cc4331e7c67e203a2 /board/amcc/kilauea/init.S
parentb8aa57b5d4d69e8f0810a5e632c0ce41c0f46ee0 (diff)
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ppc4xx: Fix comment in 405EX DDR2 init code
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/kilauea/init.S')
-rw-r--r--board/amcc/kilauea/init.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
index 4338744..053fe19 100644
--- a/board/amcc/kilauea/init.S
+++ b/board/amcc/kilauea/init.S
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on code provided from UDTech and AMCC
@@ -64,7 +64,7 @@ ext_bus_cntlr_init:
/* SET SDRAM_MB3CF - Not enabled */
mtsdram_as(SDRAM_MB3CF, 0x00000000);
- /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+ /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
mtsdram_as(SDRAM_CLKTR, 0x80000000);
/* Refresh Time register (0x30) Refresh every 7.8125uS */