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authorStefan Roese <sr@denx.de>2007-10-13 16:43:23 +0200
committerStefan Roese <sr@denx.de>2007-10-31 21:20:50 +0100
commitd4cb2d17946466740afeb195a57d6cb290bf4cc0 (patch)
tree81e5eee8d2e12c4714cd7ff213696b1a3b8f74ef /board/amcc/katmai
parentfd671802b67a0ef37a06124fa2ce85f00aa22c6f (diff)
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ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/katmai')
-rw-r--r--board/amcc/katmai/katmai.c65
1 files changed, 32 insertions, 33 deletions
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index f1c352c..0627a7a 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -30,9 +30,6 @@
#include <asm/gpio.h>
#include <asm/4xx_pcie.h>
-#undef PCIE_ENDPOINT
-/* #define PCIE_ENDPOINT 1 */
-
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f (void)
@@ -392,6 +389,7 @@ void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
+ int ret = 0;
char *env;
unsigned int delay;
@@ -405,11 +403,14 @@ void pcie_setup_hoses(int busno)
if (!katmai_pcie_card_present(i))
continue;
-#ifdef PCIE_ENDPOINT
- if (ppc4xx_init_pcie_endport(i)) {
-#else
- if (ppc4xx_init_pcie_rootport(i)) {
-#endif
+ if (is_end_point(i)) {
+ printf("PCIE%d: will be configured as endpoint\n", i);
+ ret = ppc4xx_init_pcie_endport(i);
+ } else {
+ printf("PCIE%d: will be configured as root-complex\n", i);
+ ret = ppc4xx_init_pcie_rootport(i);
+ }
+ if (ret) {
printf("PCIE%d: initialization failed\n", i);
continue;
}
@@ -424,35 +425,33 @@ void pcie_setup_hoses(int busno)
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
- PCI_REGION_MEM
- );
+ PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
-#ifdef PCIE_ENDPOINT
- ppc4xx_setup_pcie_endpoint(hose, i);
- /*
- * Reson for no scanning is endpoint can not generate
- * upstream configuration accesses.
- */
-#else
- ppc4xx_setup_pcie_rootpoint(hose, i);
-
- env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul (env, NULL, 10);
- if (delay > 5)
- printf ("Warning, expect noticable delay before PCIe"
- "scan due to 'pciscandelay' value!\n");
- mdelay (delay * 1000);
+ if (is_end_point(i)) {
+ ppc4xx_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+ } else {
+ ppc4xx_setup_pcie_rootpoint(hose, i);
+ env = getenv ("pciscandelay");
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
+ if (delay > 5)
+ printf("Warning, expect noticable delay before "
+ "PCIe scan due to 'pciscandelay' value!\n");
+ mdelay(delay * 1000);
+ }
+
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
}
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
-#endif
}
}
#endif /* defined(CONFIG_PCI) */