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| author | Stefan Roese <sr@denx.de> | 2007-03-01 21:11:36 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-01 21:11:36 +0100 |
| commit | ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 (patch) | |
| tree | 1870475942be67d0516fc69095731bee3f925a99 /board/amcc/katmai/katmai.c | |
| parent | 6c7cac8c4fce0ea2bf8e15ed8658d87974155b44 (diff) | |
| download | u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.zip u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.tar.gz u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.tar.bz2 | |
[PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.
Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/katmai/katmai.c')
| -rw-r--r-- | board/amcc/katmai/katmai.c | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 8704925..fbf1a98 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -28,7 +28,6 @@ #include <i2c.h> #include <asm-ppc/io.h> -#include "katmai.h" #include "../cpu/ppc4xx/440spe_pcie.h" #undef PCIE_ENDPOINT @@ -40,7 +39,6 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port); int board_early_init_f (void) { unsigned long mfr; - unsigned long pfc; /*----------------------------------------------------------------------+ * Interrupt controller setup for the Katmai 440SPe Evaluation board. @@ -228,15 +226,11 @@ int board_early_init_f (void) mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(sdr_mfr, mfr); */ - /* - * Setup GPIO signalling per defines in katmai.h - */ - pfc = PFC0_KATMAI; - mtsdr(SDR0_PFC0, pfc); + mtsdr(SDR0_PFC0, CFG_PFC0); - out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI); - out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI); - out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI); + out32(GPIO0_OR, CFG_GPIO_OR); + out32(GPIO0_ODR, CFG_GPIO_ODR); + out32(GPIO0_TCR, CFG_GPIO_TCR); return 0; } @@ -378,6 +372,23 @@ int is_pci_host(struct pci_controller *hose) return 1; } +int katmai_pcie_card_present(int port) +{ + u32 val; + + val = in32(GPIO0_IR); + switch (port) { + case 0: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0)); + case 1: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1)); + case 2: + return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2)); + default: + return 0; + } +} + static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; void pcie_setup_hoses(void) @@ -391,6 +402,10 @@ void pcie_setup_hoses(void) */ bus = 1; for (i = 0; i <= 2; i++) { + /* Check for katmai card presence */ + if (!katmai_pcie_card_present(i)) + continue; + #ifdef PCIE_ENDPOINT if (ppc440spe_init_pcie_endport(i)) { #else |