Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

6 files changed, 222 insertions, 59 deletions

diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 1d125b6..b1f4a21 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -40,6 +40,8 @@
 static char *config_labels[] = {
 	"CPU: 600 PLB: 200 OPB: 100 EBC: 100",
 	"CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+	"CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+	"CPU:1066 PLB: 266 OPB:  88 EBC:  88",
 	NULL
 };
 
@@ -55,6 +57,16 @@ static u8 boot_configs[][17] = {
 		0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 	},
 	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08,
+		0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08,
+		0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
 		0,
 		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 	}
@@ -168,7 +180,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
 		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
-	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 
 	printf("Done\n");
 	printf("Please power-cycle the board for the changes to take effect\n");
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index e9eba49..2b74689 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -29,20 +29,61 @@
 #include <asm/4xx_pcie.h>
 #include <asm/gpio.h>
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CFG_BCSR3_PCIE		0x10
+#define CONFIG_SYS_BCSR3_PCIE		0x10
 
 #define BOARD_CANYONLANDS_PCIE	1
 #define BOARD_CANYONLANDS_SATA	2
 #define BOARD_GLACIER		3
+#define BOARD_ARCHES		4
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+	int data;
+
+	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
+
+	return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+	int data;
+
+	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
+
+	return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
+}
+#endif	/* defined(CONFIG_ARCHES) */
 
 int board_early_init_f(void)
 {
+#if !defined(CONFIG_ARCHES)
 	u32 sdr0_cust0;
 	u32 pvr = get_pvr();
+#endif
 
 	/*
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -79,6 +120,7 @@ int board_early_init_f(void)
 	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(uic3sr, 0xffffffff);	/* clear all */
 
+#if !defined(CONFIG_ARCHES)
 	/* SDR Setting - enable NDFC */
 	mfsdr(SDR0_CUST0, sdr0_cust0);
 	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
@@ -86,8 +128,9 @@ int board_early_init_f(void)
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
 		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
-		(0x80000000 >> (28 + CFG_NAND_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
 
 	/*
 	 * Configure PFC (Pin Function Control) registers
@@ -98,14 +141,15 @@ int board_early_init_f(void)
 	/* Enable PCI host functionality in SDR0_PCI0 */
 	mtsdr(SDR0_PCI0, 0xe0000000);
 
+#if !defined(CONFIG_ARCHES)
 	/* Enable ethernet and take out of reset */
-	out_8((void *)CFG_BCSR_BASE + 6, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
 
 	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-	out_8((void *)CFG_BCSR_BASE + 5, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
 
 	/* Enable USB host & USB-OTG */
-	out_8((void *)CFG_BCSR_BASE + 7, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
 
 	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
 
@@ -123,10 +167,12 @@ int board_early_init_f(void)
 		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 	}
+#endif
 
 	return 0;
 }
 
+#if !defined(CONFIG_ARCHES)
 static void canyonlands_sata_init(int board_type)
 {
 	u32 reg;
@@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type)
 		SDR_WRITE(SDR0_SRST1, 0x00000000);
 	}
 }
+#endif	/* !defined(CONFIG_ARCHES) */
+
+int get_cpu_num(void)
+{
+	int cpu = NA_OR_UNKNOWN_CPU;
+
+#if defined(CONFIG_ARCHES)
+	int cpu_num;
+
+	cpu_num = board_fpga_read(0x3);
+
+	/* sanity check; assume cpu numbering starts and increments from 0 */
+	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
+		cpu = cpu_num;
+#endif
+
+	return cpu;
+}
 
+#if !defined(CONFIG_ARCHES)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
@@ -158,7 +223,7 @@ int checkboard(void)
 		gd->board_type = BOARD_GLACIER;
 	} else {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-		if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
+		if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
 			gd->board_type = BOARD_CANYONLANDS_PCIE;
 		else
 			gd->board_type = BOARD_CANYONLANDS_SATA;
@@ -175,7 +240,7 @@ int checkboard(void)
 		break;
 	}
 
-	printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
+	printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -188,6 +253,39 @@ int checkboard(void)
 	return (0);
 }
 
+#else	/* defined(CONFIG_ARCHES) */
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
+	printf("       Revision %02x.%02x ",
+				board_fpga_read(0x0), board_fpga_read(0x1));
+
+	gd->board_type = BOARD_ARCHES;
+
+	/* Only CPU0 has access to CPLD registers */
+	if (get_cpu_num() == 0) {
+		u8 cfg_sw = board_cpld_read(0x1);
+		printf("(FPGA=%02x, CPLD=%02x)\n",
+				board_fpga_read(0x2), board_cpld_read(0x0));
+		printf("       Configuration Switch %d%d%d%d\n",
+				((cfg_sw >> 3) & 0x01),
+				((cfg_sw >> 2) & 0x01),
+				((cfg_sw >> 1) & 0x01),
+				((cfg_sw >> 0) & 0x01));
+	} else
+		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
+
+
+	if (s != NULL)
+		printf("       Serial# %s\n", s);
+
+	return 0;
+}
+#endif	/* !defined(CONFIG_ARCHES) */
+
 /*
  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  * board specific values.
@@ -208,7 +306,7 @@ u32 ddr_clktr(u32 default_val) {
  */
 phys_size_t initdram(int board_type)
 {
-	return CFG_MBYTES_SDRAM << 20;
+	return CONFIG_SYS_MBYTES_SDRAM << 20;
 }
 #endif
 
@@ -219,7 +317,7 @@ phys_size_t initdram(int board_type)
  *	inbound map (PIM). But the bootstrap config choices are limited and
  *	may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*
@@ -234,7 +332,7 @@ void pci_target_init(struct pci_controller * hose )
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 */
-	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 	out_le32((void *)PCIX0_PIM0LAH, 0);
 	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 	out_le32((void *)PCIX0_BAR0, 0);
@@ -242,12 +340,12 @@ void pci_target_init(struct pci_controller * hose )
 	/*
 	 * Program the board's subsystem id/vendor id
 	 */
-	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
 	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 #if defined(CONFIG_PCI)
 /*
@@ -314,9 +412,9 @@ void pcie_setup_hoses(int busno)
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMSIZE,
 			       PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
@@ -362,16 +460,16 @@ int board_early_init_r (void)
 
 	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+	mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 #else
-	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+	mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 #endif
 
 	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 
 	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
-	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 		    TLB_WORD2_I_ENABLE);
 
 	/*
@@ -389,6 +487,7 @@ int board_early_init_r (void)
 	return 0;
 }
 
+#if !defined(CONFIG_ARCHES)
 int misc_init_r(void)
 {
 	u32 sdr0_srst1 = 0;
@@ -427,13 +526,54 @@ int misc_init_r(void)
 	 * Disable square wave output: Batterie will be drained
 	 * quickly, when this output is not disabled
 	 */
-	val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa);
+	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 	val &= ~0x40;
-	i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val);
+	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 
 	return 0;
 }
 
+#else	/* defined(CONFIG_ARCHES) */
+
+int misc_init_r(void)
+{
+	u32 eth_cfg = 0;
+	u32 eth_pll;
+	u32 reg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+
+	/* enable SGMII mode */
+	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
+			SDR0_ETH_CFG_SGMII1_ENABLE |
+			SDR0_ETH_CFG_SGMII2_ENABLE);
+
+	/* Set EMAC for MDIO */
+	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+
+	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/* reset all SGMII interfaces */
+	mfsdr(SDR0_SRST1,   reg);
+	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
+	mtsdr(SDR0_SRST1, reg);
+	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
+	mtsdr(SDR0_SRST1,   0x00000000);
+
+	do {
+		mfsdr(SDR0_ETH_PLL, eth_pll);
+	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
+
+	return 0;
+}
+#endif	/* !defined(CONFIG_ARCHES) */
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
@@ -445,7 +585,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 	/* Fixup NOR mapping */
 	val[0] = 0;				/* chip select number */
 	val[1] = 0;				/* always 0 */
-	val[2] = CFG_FLASH_BASE_PHYS_L;		/* we fixed up this address */
+	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
 	val[3] = gd->bd->bi_flashsize;
 	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 				  val, sizeof(val), 1);
@@ -460,12 +600,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 		 * node in the device tree, so that Linux doesn't initialize
 		 * it.
 		 */
-		rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCIe node, err=%s\n",
-			       fdt_strerror(rc));
-		}
+		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+				     "disabled", sizeof("disabled"), 1);
 	}
 
 	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
@@ -474,12 +610,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 		 * node in the device tree, so that Linux doesn't initialize
 		 * it.
 		 */
-		rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCIe node, err=%s\n",
-			       fdt_strerror(rc));
-		}
+		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+				     "disabled", sizeof("disabled"), 1);
 	}
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk
index 2330cae..551a817 100644
--- a/board/amcc/canyonlands/config.mk
+++ b/board/amcc/canyonlands/config.mk
@@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 258fb5d..0b66796 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -47,10 +47,10 @@ tlbtab:
 	 * enable SA_I
 	 */
 #ifndef CONFIG_NAND_SPL
-	tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
 #else
-	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 	tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 #endif
 
@@ -60,37 +60,54 @@ tlbtab:
 	 * routine.
 	 */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
 	/* PCIe UTL register */
-	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
+#if !defined(CONFIG_ARCHES)
 	/* TLB-entry for NAND */
-	tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	/* TLB-entry for CPLD */
-	tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+#else
+	/* TLB-entry for FPGA */
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+#endif
 
 	/* TLB-entry for OCM */
-	tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 
 	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	/* AHB: Internal USB Peripherals (USB, SATA) */
-	tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+#if defined(CONFIG_RAPIDIO)
+	/* TLB-entries for RapidIO (SRIO) */
+	tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
+					0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
+					0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
+					0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K,  0x00100000,
+					0x4, AC_R|AC_W|SA_G|SA_I)
+#endif
 
 	tlbtab_end
 
@@ -99,8 +116,8 @@ tlbtab:
 	 * For NAND booting the first TLB has to be reconfigured to full size
 	 * and with caching disabled after running from RAM!
 	 */
-#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 #define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	.globl	reconfig_tlb0
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index 8a4b7f5..9f13d03 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -57,7 +57,7 @@ SECTIONS
 
     /* Align to next NAND block */
     . = ALIGN(0x20000);
-    common/environment.o  (.ppcenv)
+    common/env_embedded.o  (.ppcenv)
     /* Keep some space here for redundant env and potential bad env blocks */
     . = ALIGN(0x80000);
 
@@ -129,6 +129,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
 
   _end = . ;
diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds
index 1783bc7..f0db0b2 100644
--- a/board/amcc/canyonlands/u-boot.lds
+++ b/board/amcc/canyonlands/u-boot.lds
@@ -136,6 +136,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
+   . = ALIGN(4);
   }
 
   _end = . ;