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| author | Eugene O'Brien <eugene.obrien@advantechamt.com> | 2007-10-23 08:29:10 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-10-31 21:20:51 +0100 |
| commit | 9f798766aa85e62eb8fa8c721e148df609b78137 (patch) | |
| tree | 8c39fec8978f1f2dc98be422b3a9d0aad1211764 /board/amcc/bamboo | |
| parent | afe9fa59cb63b4f9d16bf01c93eb212f25a38c2a (diff) | |
| download | u-boot-imx-9f798766aa85e62eb8fa8c721e148df609b78137.zip u-boot-imx-9f798766aa85e62eb8fa8c721e148df609b78137.tar.gz u-boot-imx-9f798766aa85e62eb8fa8c721e148df609b78137.tar.bz2 | |
ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:
Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!
Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/bamboo')
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 00c793a..c4eace5 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0x00, /* Module data width continued: +0 */ 0x04, /* 2.5 Volt */ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + 0x00, /* SDRAM Access from clock */ #ifdef CONFIG_DDR_ECC 0x02, /* ECC ON : 02 OFF : 00 */ #else 0x00, /* ECC ON : 02 OFF : 00 */ #endif - 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ - 0, + 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ 0, 0, 0x01, /* wcsbc = 1 */ |