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authorWolfgang Denk <wd@denx.de>2009-09-30 23:26:59 +0200
committerWolfgang Denk <wd@denx.de>2009-09-30 23:26:59 +0200
commit9ae7ae6b4dd9d0c6489ac5b054846f80cfd973b8 (patch)
treed5b5c439fd49237040c81ba9fb733d1b90bf37ee /board/amcc/bamboo/bamboo.c
parent7b5ae460c34fa43261fe1ded71dc9c33d3ffd8e5 (diff)
parentb306db2f1bf561b5823a655c677fe28cfad80cfb (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'board/amcc/bamboo/bamboo.c')
-rw-r--r--board/amcc/bamboo/bamboo.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2ffd720..38186a5 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -392,21 +392,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins