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| author | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
| commit | 10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch) | |
| tree | c3ac82364df83db5d5cb963c64b863b77a20445c /board/amcc/bamboo/bamboo.c | |
| parent | 97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff) | |
| parent | 1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff) | |
| download | u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.zip u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.gz u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/amcc/bamboo/bamboo.c')
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 126 |
1 files changed, 63 insertions, 63 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index c4eace5..5077187 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -280,86 +280,86 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { #define EBC0_BNAP_SMALL_FLASH \ EBC0_BNAP_BME_DISABLED | \ EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(3) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED #define EBC0_BNCR_SMALL_FLASH_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT #define EBC0_BNCR_SMALL_FLASH_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT /* Large Flash or SRAM */ #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(8) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(1) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT /* NVRAM - FPGA */ #define EBC0_BNAP_NVRAM_FPGA \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(9) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED #define EBC0_BNCR_NVRAM_FPGA_CS5 \ - EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x80000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT /* Nand Flash */ #define EBC0_BNAP_NAND_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(3) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(0) | \ + EBC0_BNAP_WBN_ENCODE(0) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_NOT_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED @@ -367,22 +367,22 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { /* NAND0 */ #define EBC0_BNCR_NAND_FLASH_CS1 \ - EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x90000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank2 */ #define EBC0_BNCR_NAND_FLASH_CS2 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank3 */ #define EBC0_BNCR_NAND_FLASH_CS3 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT int board_early_init_f(void) |