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| author | Stefano Babic <sbabic@denx.de> | 2014-04-04 11:35:30 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-04-04 11:35:30 +0200 |
| commit | 1cad23c5f471d695bed1e3907e30caee3c2a3056 (patch) | |
| tree | 34e035df5db9b327aeae36eff9d0645a915e3177 /board/amcc/acadia | |
| parent | 5dd73bc0a40a4b318195eab871a1f535aad6b43b (diff) | |
| parent | 00b132bf34c5be86a108ac7fe8231ad9e97f6de4 (diff) | |
| download | u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.zip u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.tar.gz u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/amcc/acadia')
| -rw-r--r-- | board/amcc/acadia/memory.c | 13 | ||||
| -rw-r--r-- | board/amcc/acadia/pll.c | 42 |
2 files changed, 0 insertions, 55 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 61bfea3..9673118 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -17,7 +17,6 @@ extern void board_pll_init_f(void); -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val) return; } -#endif phys_size_t initdram(int board_type) { -#if defined(CONFIG_NAND_SPL) - u32 reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; @@ -88,7 +76,6 @@ phys_size_t initdram(int board_type) /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; -#endif return (CONFIG_SYS_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index d74b725..d868582 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -135,45 +135,3 @@ void board_pll_init_f(void) mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU_<speed>_405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ |