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| author | Stefan Roese <sr@denx.de> | 2010-09-12 06:21:37 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-09-23 09:02:05 +0200 |
| commit | afabb498b749b48ca3ee7e833fe1501e2d6993cb (patch) | |
| tree | a5e131d0d7f62e41bd9bc1c767452b43b75bf82e /board/amcc/acadia/pll.c | |
| parent | 5e7abce99163a00b8d267cc8045f06b498728288 (diff) | |
| download | u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.zip u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.tar.gz u-boot-imx-afabb498b749b48ca3ee7e833fe1501e2d6993cb.tar.bz2 | |
ppc4xx: Big header cleanup part 2, mostly PPC405 related
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/acadia/pll.c')
| -rw-r--r-- | board/amcc/acadia/pll.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index 452961d..6327d6c 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -53,9 +53,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x0000033c); mtcpr(CPR0_PLLD, 0x0c010200); - mtcpr(CPC0_PRIMAD, 0x04060c0c); - mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_CLKUP, 0x40000000); + mtcpr(CPR0_PRIMAD, 0x04060c0c); + mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_CLKUPD, 0x40000000); } #elif defined(PLLMR0_266_160_80) @@ -85,10 +85,10 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x20000238); mtcpr(CPR0_PLLD, 0x03010400); - mtcpr(CPC0_PRIMAD, 0x03050a0a); - mtcpr(CPC0_PERC0, 0x00000000); - mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0x07323200); + mtcpr(CPR0_PRIMAD, 0x03050a0a); + mtcpr(CPR0_PERC0, 0x00000000); + mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0x07323200); mtcpr(CPR0_CLKUP, 0x40000000); } @@ -119,9 +119,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x0000033C); mtcpr(CPR0_PLLD, 0x0a010000); - mtcpr(CPC0_PRIMAD, 0x02040808); - mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0xA6A60300); + mtcpr(CPR0_PRIMAD, 0x02040808); + mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0xA6A60300); mtcpr(CPR0_CLKUP, 0x40000000); } @@ -145,9 +145,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x000003BC); mtcpr(CPR0_PLLD, 0x06060600); - mtcpr(CPC0_PRIMAD, 0x02020004); - mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0xC8C81600); + mtcpr(CPR0_PRIMAD, 0x02020004); + mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0xC8C81600); mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU_<speed>_405EZ */ @@ -172,7 +172,7 @@ unsigned long get_tbclk(void) /* * Read CPR_PRIMAD register */ - mfcpr(CPC0_PRIMAD, cpr_primad); + mfcpr(CPR0_PRIMAD, cpr_primad); /* * Determine CPU clock frequency |