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authorStefan Roese <sr@denx.de>2014-03-04 15:34:35 +0100
committerTom Rini <trini@ti.com>2014-03-07 10:59:06 -0500
commit345b77bacabb84a00c7508471ab560b452910240 (patch)
treeebfd90c103d0129cf16b07912d2a86d2b75bae5d /board/amcc/acadia/memory.c
parentdc116bd6c4b5cb1caf6621f282ac5156d1509bef (diff)
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ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'board/amcc/acadia/memory.c')
-rw-r--r--board/amcc/acadia/memory.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 61bfea3..9673118 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -17,7 +17,6 @@
extern void board_pll_init_f(void);
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
@@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)
return;
}
-#endif
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_NAND_SPL)
- u32 reg;
-
- /* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR0_PINSTP, reg);
- if (reg != 0xf0000000)
- board_pll_init_f();
-#endif
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
@@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
-#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}