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authorDinh Nguyen <dinguyen@opensource.altera.com>2014-11-13 11:23:41 -0600
committerMarek Vasut <marex@denx.de>2014-12-06 13:51:54 +0100
commit74ae12e184a7cd30edc4d6853ed246abe98fffc4 (patch)
treea2f38b364546b57b5249120b5846006dbdae1067 /board/altera/socfpga
parentfa8278d702e7693b0188f77ac35d130166bcbfd4 (diff)
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arm: socfpga: set skew settings for ethernet phy
Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/altera/socfpga')
-rw-r--r--board/altera/socfpga/socfpga_cyclone5.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index ce625e5..772a58e 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,7 +12,9 @@
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
+#include <micrel.h>
#include <netdev.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,6 +46,20 @@ int board_init(void)
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+}
+
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,