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authorMarek Vasut <marex@denx.de>2014-09-15 01:29:08 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:46:50 +0200
commit40e7bcdee72830fa51d9e98428f1a61f9126527e (patch)
treeb2cd09665f2813bd3f5de81840c9979f85f77347 /board/altera/socfpga
parent9ca2116ce49449602eb9e2f8a0cafe811bcc3086 (diff)
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arm: socfpga: cache: Enable D-Cache
The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'board/altera/socfpga')
-rw-r--r--board/altera/socfpga/socfpga_cyclone5.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 4149842..6b98277 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,6 +35,7 @@ int board_early_init_f(void)
int board_init(void)
{
icache_enable();
+ dcache_enable();
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;