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authorMichal Simek <michal.simek@xilinx.com>2014-03-13 13:07:57 +0100
committerMichal Simek <michal.simek@xilinx.com>2014-05-13 09:13:59 +0200
commit14cfc4f3735d9704cb6a630ef302be596d380684 (patch)
tree23c759ab37c1368763488a5548813231cfa1d3d0 /board/alphaproject
parent2df9d5c431fca07c9868a36b48ee771bde6b19e8 (diff)
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fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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