Power: remove support for Freescale MPC8220

The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>

4 files changed, 0 insertions, 1624 deletions

diff --git a/board/alaska/Makefile b/board/alaska/Makefile
deleted file mode 100644
index a21f851..0000000
--- a/board/alaska/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/alaska/README b/board/alaska/README
deleted file mode 100644
index 3345073..0000000
--- a/board/alaska/README
+++ /dev/null
@@ -1,482 +0,0 @@
-Freescale Alaska MPC8220 board
-==============================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created 9/21/04
-===========================================
-
-
-Changed files:
-==============
-
-- Makefile		    added MPC8220 and Alaska8220_config
-- MAKEALL		    added MPC8220 and Alaska8220
-- README		    added CONFIG_MPC8220, Alaska8220_config
-
-- common/cmd_bdinfo.c	    added board information members for MPC8220
-- common/cmd_bootm.c	    added clocks for MPC8220 in do_bootm_linux()
-
-- include/common.h	    added CONFIG_MPC8220
-
-- include/asm-ppc/u-boot.h  added board information members for MPC8220
-- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
-			    vco_clk, pev_clk, flb_clk, and bExtUart
-
-- arch/powerpc/lib/board.c	    added CONFIG_MPC8220 support
-
-- net/eth.c		    added FEC support for MPC8220
-
-Added files:
-============
-- board/alaska		    directory for Alaska MPC8220
-- board/alaska/alaska.c	    Alaska dram and BATs setup
-- board/alaska/extserial.c  external serial (debug card serial) support
-- board/alaska/flash.c	    Socket (AMD) and Onboard (INTEL) flash support
-- board/alaska/serial.c	    to determine which int/ext serial to use
-- board/alaska/Makefile	    Makefile
-- board/alaska/config.mk    config make
-- board/alaska/u-boot.lds   Linker description
-
-- arch/powerpc/cpu/mpc8220/dma.h	    multi-channel dma header file
-- arch/powerpc/cpu/mpc8220/dramSetup.h   dram setup header file
-- arch/powerpc/cpu/mpc8220/fec.h	    MPC8220 FEC header file
-- arch/powerpc/cpu/mpc8220/cpu.c	    cpu specific code
-- arch/powerpc/cpu/mpc8220/cpu_init.c    Flexbus ChipSelect and Mux pins setup
-- arch/powerpc/cpu/mpc8220/dramSetup.c   MPC8220 DDR SDRAM setup
-- arch/powerpc/cpu/mpc8220/fec.c	    MPC8220 FEC driver
-- arch/powerpc/cpu/mpc8220/i2c.c	    MPC8220 I2C driver
-- arch/powerpc/cpu/mpc8220/interrupts.c  interrupt support (not enable)
-- arch/powerpc/cpu/mpc8220/loadtask.c    load dma
-- arch/powerpc/cpu/mpc8220/speed.c	    system, pci, flexbus, pev, and cpu clock
-- arch/powerpc/cpu/mpc8220/traps.c	    exception
-- arch/powerpc/cpu/mpc8220/uart.c	    MPC8220 UART driver
-- arch/powerpc/cpu/mpc8220/Makefile	    Makefile
-- arch/powerpc/cpu/mpc8220/config.mk	    config make
-- arch/powerpc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- arch/powerpc/cpu/mpc8220/io.S	    io functions
-- arch/powerpc/cpu/mpc8220/start.S	    start up
-
-- include/mpc8220.h
-
-- include/asm-ppc/immap_8220.h
-
-- include/configs/Alaska8220.h
-
-
-1. SWITCH SETTINGS
-==================
-1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL)
-    SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART
-    SW3: unsed
-    SW4: 0 - 1284 or 1 - FEC1
-    SW5: 0 - PEV or 1 - FEC2
-
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
-     linux kernel, you can customize it based on your system requirements:
-      DDR:	    0x00000000-0x1fffffff (max 512MB)
-      MBAR:	    0xf0000000-0xf0027fff (128KB)
-      CPLD:	    0xf1000000-0xf103ffff (256KB)
-      FPGA:	    0xf2000000-0xf203ffff (256KB)
-      Flash:	    0xfe000000-0xffffffff (max 32MB)
-
-3. DEFINITIONS AND COMPILATION
-==============================
-3.1 Explanation on NEW definitions in include/configs/alaska8220.h
-    CONFIG_MPC8220	    MPC8220 specific
-    CONFIG_ALASKA8220	    Alaska board specific
-    CONFIG_SYS_MPC8220_CLKIN	    Define Alaska Input Clock
-    CONFIG_PSC_CONSOLE	    Enable MPC8220 UART
-    CONFIG_EXTUART_CONSOLE  Enable External 16552 UART
-    CONFIG_SYS_AMD_BOOT	    To determine the u-boot is booted from AMD or Intel
-    CONFIG_SYS_MBAR		    MBAR base address
-    CONFIG_SYS_DEFAULT_MBAR	    Reset MBAR base address
-
-3.2 Compilation
-   export CROSS_COMPILE=cross-compile-prefix
-   cd u-boot-1-1-x
-   make distclean
-   make Alaska8220_config
-   make
-
-
-4. SCREEN DUMP
-==============
-4.1 Alaska MPC8220 board
-    Boot from AMD (NOTE: May not show exactly the same)
-
-U-Boot 1.1.1 (Sep 22 2004 - 22:14:41)
-
-CPU:   MPC8220 (JTAG ID 1640301d) at 300 MHz
-       Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz
-Board: Alaska MPC8220 Evaluation Board
-I2C:   93 kHz, ready
-DRAM:  256 MB
-Reserving 167k for U-Boot at: 0ffd6000
-FLASH: 16.5 MB
-*** Warning - bad CRC, using default environment
-
-In:    serial
-Out:   serial
-Err:   serial
-Net:   FEC ETHERNET
-=> flinfo
-
-Bank # 1: INTEL 28F128J3A
-  Size: 8 MB in 64 Sectors
-  Sector Start Addresses:
-    FE000000	  FE020000	FE040000      FE060000	    FE080000
-    FE0A0000	  FE0C0000	FE0E0000      FE100000	    FE120000
-    FE140000	  FE160000	FE180000      FE1A0000	    FE1C0000
-    FE1E0000	  FE200000	FE220000      FE240000	    FE260000
-    FE280000	  FE2A0000	FE2C0000      FE2E0000	    FE300000
-    FE320000	  FE340000	FE360000      FE380000	    FE3A0000
-    FE3C0000	  FE3E0000	FE400000      FE420000	    FE440000
-    FE460000	  FE480000	FE4A0000      FE4C0000	    FE4E0000
-    FE500000	  FE520000	FE540000      FE560000	    FE580000
-    FE5A0000	  FE5C0000	FE5E0000      FE600000	    FE620000
-    FE640000	  FE660000	FE680000      FE6A0000	    FE6C0000
-    FE6E0000	  FE700000	FE720000      FE740000	    FE760000
-    FE780000	  FE7A0000	FE7C0000      FE7E0000
-
-Bank # 2: INTEL 28F128J3A
-  Size: 8 MB in 64 Sectors
-  Sector Start Addresses:
-    FE800000	  FE820000	FE840000      FE860000	    FE880000
-    FE8A0000	  FE8C0000	FE8E0000      FE900000	    FE920000
-    FE940000	  FE960000	FE980000      FE9A0000	    FE9C0000
-    FE9E0000	  FEA00000	FEA20000      FEA40000	    FEA60000
-    FEA80000	  FEAA0000	FEAC0000      FEAE0000	    FEB00000
-    FEB20000	  FEB40000	FEB60000      FEB80000	    FEBA0000
-    FEBC0000	  FEBE0000	FEC00000      FEC20000	    FEC40000
-    FEC60000	  FEC80000	FECA0000      FECC0000	    FECE0000
-    FED00000	  FED20000	FED40000      FED60000	    FED80000
-    FEDA0000	  FEDC0000	FEDE0000      FEE00000	    FEE20000
-    FEE40000	  FEE60000	FEE80000      FEEA0000	    FEEC0000
-    FEEE0000	  FEF00000 (RO) FEF20000 (RO) FEF40000	    FEF60000
-    FEF80000	  FEFA0000	FEFC0000      FEFE0000 (RO)
-
-Bank # 3: AMD AMD29F040B
-  Size: 0 MB in 7 Sectors
-  Sector Start Addresses:
-    FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000	    FFF40000
-    FFF50000	  FFF60000
-
-Bank # 4: AMD AMD29F040B
-  Size: 0 MB in 1 Sectors
-  Sector Start Addresses:
-    FFF70000 (RO)
-=> bdinfo
-
-memstart    = 0xF0009800
-memsize	    = 0x10000000
-flashstart  = 0xFFF00000
-flashsize   = 0x01080000
-flashoffset = 0x00025000
-sramstart   = 0xF0020000
-sramsize    = 0x00008000
-bootflags   = 0x00000001
-intfreq	    =	 300 MHz
-busfreq	    =	 120 MHz
-inpfreq	    =	  30 MHz
-flbfreq	    =	  30 MHz
-pcifreq	    =	  30 MHz
-vcofreq	    =	 480 MHz
-pevfreq	    =	  81 MHz
-ethaddr	    = 00:E0:0C:BC:E0:60
-eth1addr    = 00:E0:0C:BC:E0:61
-IP addr	    = 192.162.1.2
-baudrate    = 115200 bps
-=> printenv
-bootargs=root=/dev/ram rw
-bootdelay=5
-baudrate=115200
-ethaddr=00:e0:0c:bc:e0:60
-eth1addr=00:e0:0c:bc:e0:61
-ipaddr=192.162.1.2
-serverip=192.162.1.1
-gatewayip=192.162.1.1
-netmask=255.255.255.0
-hostname=Alaska
-stdin=serial
-stdout=serial
-stderr=serial
-ethact=FEC ETHERNET
-
-Environment size: 268/65532 bytes
-=> setenv ipaddr 192.160.1.2
-=> setenv serverip 192.160.1.1
-=> setenv gatewayip 192.160.1.1
-=> saveenv
-Saving Environment to Flash...
-
-.
-Un-Protected 1 sectors
-Erasing Flash...
-Erasing sector	0 ...  done
-Erased 1 sectors
-Writing to Flash... done
-
-.
-Protected 1 sectors
-=> tftp 0x10000 linux.elf
-Using FEC ETHERNET device
-TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1
-Filename 'linux.elf'.
-Load address: 0x10000
-Loading: invalid RARP header
-#################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 #################################################################
-	 ##################################################
-done
-Bytes transferred = 2917494 (2c8476 hex)
-=> bootelf
-Loading .text @ 0x00a00000 (23820 bytes)
-Loading .data @ 0x00a06000 (2752512 bytes)
-Clearing .bss @ 0x00ca6000 (12764 bytes)
-## Starting application at 0x00a00000 ...
-
-Collect some entropy from RAM........done
-loaded at:     00A00000 00CA91DC
-zimage at:     00A06A93 00AD7756
-initrd at:     00AD8000 00CA5565
-avail ram:     00CAA000 014AA000
-
-Linux/PPC load: ip=off console=ttyS0,115200
-Uncompressing Linux...done.
-Now booting the kernel
-Total memory in system: 256 MB
-Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.21-rc1 (r61688@bluesocks.sps.mot.com) (gcc version 3.3.1) #17 Wed Sep 8 11:49:16 CDT 2004
-Motorola Alaska port (C) 2003 Motorola, Inc.
-CPLD rev 3
-CPLD switches 0x1b
-Set Pin Mux for FEC1
-Set Pin Mux for FEC2
-Alaska Pin Multiplexing:
-Port Configuration Register 0 = 0
-Port Configuration Register 1 = 0
-Port Configuration Register 2 = 0
-Port Configuration Register 3 = 50000000
-Port Configuration Register 3 - PCI = 51400180
-Setup Alaska FPGA PIC:
-Interrupt Enable Register *(u32) = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_be32 = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_le32 = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register readl = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register = 0
-Interrupt Status Register = 2f0000
-Setup Alaska PCI Controller:
-On node 0 totalpages: 65536
-zone(0): 65536 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: ip=off console=ttyS0,115200
-Using XLB clock (120.00 MHz) to set up decrementer
-Calibrating delay loop... 199.88 BogoMIPS
-Memory: 254792k available (1476k kernel code, 708k data, 228k init, 0k highmem)
-Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
-Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
-Mount cache hash table entries: 512 (order: 0, 4096 bytes)
-Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes)
-Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-PCI: (pcibios_init) Global-Hose = 0xc029d000
-Scanning bus 00
-Fixups for bus 00
-Bus scan for 00 returning with max=00
-PCI: (pcibios_init) finished pci_scan_bus(hose->first_busno = 0, hose->ops = c01a1a74, hose = c029d000)
-PCI: (pcibios_init) PCI Bus Count = 0 =?= Next Bus# = 1
-PCI: (pcibios_init@pci_fixup_irqs) finished machine dependent PCI interrupt routing!
-PCI: bridge rsrc 81000000..81ffffff (100), parent c01a7f88
-PCI: bridge rsrc 84000000..87ffffff (200), parent c01a7fa4
-PCI: (pcibios_init) finished allocating and assigning resources!
-initDma!
-Using 90 DMA buffer descriptors
-descUsed f0023600, descriptors f002360c freeSram f0024140
-unmask SDMA tasks: 0xf0008018 = 0x6f000000
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-Journalled Block Device driver loaded
-JFFS version 1.0, (C) 1999, 2000  Axis Communications AB
-JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB.
-pty: 256 Unix98 ptys configured
-tracek: Copyright (C) Motorola, 2003.
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-ttyS00 at 0xf1001008 (irq = 73) is a ST16650
-ttyS01 at 0xf1001010 (irq = 74) is a ST16650
-elp-fpanel: Copyright (C) Motorola, 2003.
-fpanel: fpanelWait timeout
-elp-engine: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-Alpine 1284 driver: Copyright (C) Motorola, 2003.
-1284 disabled due to configuration switch 5
-Alpine USB driver: Copyright (C) Motorola, 2003.
-OK
-USB: Descriptor download completed OK
-enable_irq(41) unbalanced
-enable_irq(75) unbalanced
-elp-dmaram: Copyright (C) Motorola, 2003.
-Total memory in system: 256 MB
-elp_dmaram: offset is 0x10000000, size is 0
-Xicor NVRAM driver: Copyright (C) Motorola, 2003.
-elp-video: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-elp-pfm: Copyright (C) Motorola, 2003.
-paddle: Copyright (C) Motorola, 2001, present.
-RAMDISK driver initialized: 16 RAM disks of 12288K size 1024 blocksize
-loop: loaded (max 8 devices)
-PPP generic driver version 2.4.2
-PPP Deflate Compression module registered
-Uniform Multi-Platform E-IDE driver Revision: 7.00beta-2.4
-ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
-init_alaska_mtd: chip probing count 0
-cfi_cmdset_0001: Erase suspend on write enabled
-Using buffer write method
-init_alaska_mtd: bank1, name:ALASKA0, size:16777216bytes
-ALASKA flash0: Using Static image partition definition
-Creating 3 MTD partitions on "ALASKA0":
-0x00000000-0x00280000 : "kernel"
-0x00280000-0x00fe0000 : "user"
-0x00fe0000-0x01000000 : "signature"
-mgt_fec_module_init
-mgt_fec_init()
-mgt_fec_init
-mgt_init_fec_dev(0xc05f6000,0)
-dev c05f6000 fec_priv c05f6160 fec f0009000
-mgt_init_fec_dev(0xc05f6800,1)
-dev c05f6800 fec_priv c05f6960 fec f0009800
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 2048 buckets, 16Kbytes
-TCP: Hash tables configured (established 16384 bind 32768)
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-RAMDISK: Compressed image found at block 0
-Freeing initrd memory: 1845k freed
-JFFS: Trying to mount a non-mtd device.
-VFS: Mounted root (romfs filesystem) readonly.
-Freeing unused kernel memory: 228k init
-INIT: version 2.78 booting
-INIT: Entering runlevel: 1
-"Space, a great big place of unknown stuff."  -Dexter, for our MotD.
-[01/Jan/1970:00:00:01 +0000] boa: server version Boa/0.94.8.3
-[01/Jan/1970:00:00:01 +0000] boa: server built Sep  7 2004 at 17:40:55.
-[01/Jan/1970:00:00:01 +0000] boa: starting server pid=28, port 80
-Mounting flash filesystem, will take a minute...
-/etc/rc: line 30: /dev/lp0: No such devish-2.05b#
-sh-2.05b# ifup eth0
-client (v0.9.9-pre) started
-adapter index 2
-adapter hardware address 00:e0:0c:bc:e0:60
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0
-eth0	  Link encap:Ethernet  HWaddr 00:E0:0C:BC:E0:60
-	  BROADCAST MULTICAST  MTU:1500	 Metric:1
-	 mgt_fec_open
- Rfec request irq
-X fec_open: rcv_ring_size 8, xmt_ring_size 8
-packmgt_fec_open(): call netif_start_queue()
-ets:0 errors:0 dropped:0 overruns:0 frame:0
-	  TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
-	  collisions:0 txqueuelen:100
-	  RX bytes:0 (0.0 b)  TX bytes:0 (0.0 b)
-	  Base address:0x9000
-
-/sbin/ifconfig eth0 up
-entering raw listen mode
-Opening raw socket on ifindex 2
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-Sending discover...
-Waiting on select...
-unrelated/bogus packet
-Waiting on select...
-oooooh!!! got some!
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-adding option 0x32
-adding option 0x36
-Sending select for 163.12.48.146...
-Waiting on select...
-oooooh!!! got some!
-Waiting on select...
-oooooh!!! got some!
-Lease of 163.12.48.146 obtained, lease time 345600
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0 163.12.48.146 netmask 255.255.254.0
-/sbin/ifconfig eth0 up
-deleting routers
-/sbin/route del default
-/sbin/route add default gw 163.12.49.254 dev eth0
-adding dns 163.12.252.230
-adding dns 192.55.22.4
-adding dns 192.5.249.4
-entering none listen mode
-sh-2.05b#
-
-5. REPROGRAM U-BOOT
-===================
-5.1 Reprogram u-boot (boot from AMD)
-    1. Unprotect the boot sector
-    => protect off bank 3
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfff00000 0xfff6ffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfff00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.2 Reprogram u-boot (boot from AMD program at INTEL)
-    1. Unprotect the boot sector
-    => protect off bank 2
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfef00000 0xfefdffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfef00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.3 Reprogram u-boot (boot from INTEL)
-    1. Unprotect the boot sector
-    => protect off bank 4
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfff00000 0xfffdffff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfff00000
-    5. Reset for the new u-boot to take place
-    => reset
-
-5.4 Reprogram u-boot (boot from INTEL program at AMD)
-    1. Unprotect the boot sector
-    => protect off bank 1
-    2. Download new u-boot binary file
-    => tftp 0x10000 u-boot.bin
-    3. Erase bootsector (max 7 sectors)
-    => erase 0xfe080000 0xfe0effff
-    4. Program the u-boot to flash
-    => cp.b 0x10000 0xfe080000
-    5. Reset for the new u-boot to take place
-    => reset
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
deleted file mode 100644
index 89c1abd..0000000
--- a/board/alaska/alaska.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-void setupBat (ulong size)
-{
-	ulong batu, batl;
-	int blocksize = 0;
-
-	/* Flash 0 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#else
-	batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#endif
-	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
-	write_bat (IBAT0, batu, batl);
-	write_bat (DBAT0, batu, batl);
-
-	/* Flash 1 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#else
-	batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#endif
-	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
-	write_bat (IBAT1, batu, batl);
-	write_bat (DBAT1, batu, batl);
-
-	/* CPLD */
-	batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_CPLD_BASE | 0x22;
-	write_bat (IBAT2, 0, 0);
-	write_bat (DBAT2, batu, batl);
-
-	/* FPGA */
-	batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_FPGA_BASE | 0x22;
-	write_bat (IBAT3, 0, 0);
-	write_bat (DBAT3, batu, batl);
-
-	/* MBAR - Data only */
-	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_MBAR | 0x22;
-	mtspr (IBAT4L, 0);
-	mtspr (IBAT4U, 0);
-	mtspr (DBAT4L, batl);
-	mtspr (DBAT4U, batu);
-
-	/* MBAR - SRAM */
-	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_SRAM_BASE | 0x42;
-	mtspr (IBAT5L, batl);
-	mtspr (IBAT5U, batu);
-	mtspr (DBAT5L, batl);
-	mtspr (DBAT5U, batu);
-
-	if (size <= 0x800000)	/* 8MB */
-		blocksize = BATU_BL_8M;
-	else if (size <= 0x1000000)	/* 16MB */
-		blocksize = BATU_BL_16M;
-	else if (size <= 0x2000000)	/* 32MB */
-		blocksize = BATU_BL_32M;
-	else if (size <= 0x4000000)	/* 64MB */
-		blocksize = BATU_BL_64M;
-	else if (size <= 0x8000000)	/* 128MB */
-		blocksize = BATU_BL_128M;
-	else if (size <= 0x10000000)	/* 256MB */
-		blocksize = BATU_BL_256M;
-
-	/* Memory */
-	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
-	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
-	mtspr (IBAT6L, batl);
-	mtspr (IBAT6U, batu);
-	mtspr (DBAT6L, batl);
-	mtspr (DBAT6U, batu);
-
-	/* memory size is less than 256MB */
-	if (size <= 0x10000000) {
-		/* Nothing */
-		batu = 0;
-		batl = 0;
-	} else {
-		size -= 0x10000000;
-		if (size <= 0x800000)	/* 8MB */
-			blocksize = BATU_BL_8M;
-		else if (size <= 0x1000000)	/* 16MB */
-			blocksize = BATU_BL_16M;
-		else if (size <= 0x2000000)	/* 32MB */
-			blocksize = BATU_BL_32M;
-		else if (size <= 0x4000000)	/* 64MB */
-			blocksize = BATU_BL_64M;
-		else if (size <= 0x8000000)	/* 128MB */
-			blocksize = BATU_BL_128M;
-		else if (size <= 0x10000000)	/* 256MB */
-			blocksize = BATU_BL_256M;
-
-		batu = (CONFIG_SYS_SDRAM_BASE +
-			0x10000000) | blocksize | BPP_RW | BPP_RX;
-		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
-	}
-
-	mtspr (IBAT7L, batl);
-	mtspr (IBAT7U, batu);
-	mtspr (DBAT7L, batl);
-	mtspr (DBAT7U, batu);
-}
-
-phys_size_t initdram (int board_type)
-{
-	ulong size;
-
-	size = dramSetup ();
-
-/* if iCache ad dCache is defined */
-#if defined(CONFIG_CMD_CACHE)
-/*    setupBat(size);*/
-#endif
-
-	return size;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Alaska MPC8220 Evaluation Board\n");
-
-	return 0;
-}
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
deleted file mode 100644
index 977822a..0000000
--- a/board/alaska/flash.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH8
-
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-
-#define SWAP(x)         (x)
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT    0x89
-#define INTEL_ALT       0xB0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM   0x10
-#define INTEL_ERASE     0x20
-#define INTEL_CLEAR     0x50
-#define INTEL_LOCKBIT   0x60
-#define INTEL_PROTECT   0x01
-#define INTEL_STATUS    0x70
-#define INTEL_READID    0x90
-#define INTEL_CONFIRM   0xD0
-#define INTEL_RESET     0xFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED  0x80
-#define INTEL_OK        0x80
-
-#define FPW             FLASH_PORT_WIDTH
-#define FPWV            FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1    0x0555
-#define FLASH_CYCLE2    0x02aa
-
-#define WR_BLOCK        0x20
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static int write_data_block (flash_info_t * info, ulong src, ulong dest);
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-static unsigned char same_chip_banks (int bank1, int bank2);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	ulong fsize = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		memset (&flash_info[i], 0, sizeof (flash_info_t));
-
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
-					&flash_info[i]);
-			flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
-			break;
-		case 1:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
-					&flash_info[i]);
-			fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
-			flash_get_offsets (fsize, &flash_info[i]);
-			break;
-		case 2:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
-					&flash_info[i]);
-			flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
-			break;
-		case 3:
-			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
-					&flash_info[i]);
-			fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
-			flash_get_offsets (fsize, &flash_info[i]);
-			break;
-		default:
-			panic ("configured to many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-
-		/* get the h/w and s/w protection status in sync */
-		flash_sync_real_protect(&flash_info[i]);
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-#if defined (CONFIG_SYS_AMD_BOOT)
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[2]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_INTEL_BASE,
-		       CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
-		       &flash_info[1]);
-#else
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[3]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_AMD_BASE,
-		       CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV1_ADDR,
-		       CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]);
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		printf ("28F128J3A\n");
-		break;
-
-	case FLASH_AM040:
-		printf ("AMD29F040B\n");
-		break;
-
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	FPWV value;
-	static int amd = 0;
-
-	/* Write auto select command: read Manufacturer ID */
-	/* Write auto select command sequence and test FLASH answer */
-	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
-	__asm__ ("sync");
-	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
-	__asm__ ("sync");
-	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD */
-	__asm__ ("sync");
-
-	udelay (100);
-
-	switch (addr[0] & 0xff) {
-
-	case (uchar) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		value = addr[1];
-		break;
-
-	case (uchar) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		value = addr[2];
-		break;
-
-	default:
-		printf ("unknown\n");
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);	/* no or unknown flash  */
-	}
-
-	switch (value) {
-
-	case (FPW) INTEL_ID_28F128J3A:
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 64;
-		info->size = 0x00800000;	/* => 16 MB     */
-		break;
-
-	case (FPW) AMD_ID_LV040B:
-		info->flash_id += FLASH_AM040;
-		if (amd == 0) {
-			info->sector_count = 7;
-			info->size = 0x00070000;	/* => 448 KB     */
-			amd = 1;
-		} else {
-			/* for Environment settings */
-			info->sector_count = 1;
-			info->size = PHYS_AMD_SECT_SIZE;	/* => 64 KB     */
-			amd = 0;
-		}
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	if (value == (FPW) INTEL_ID_28F128J3A)
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-	else
-		addr[0] = (FPW) 0x00F000F0;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		for (i = 0; i < info->sector_count; ++i) {
-			info->protect[i] = intel_sector_protected(info, i);
-		}
-		break;
-	case FLASH_AM040:
-	default:
-		/* no h/w protect support */
-		break;
-	}
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
-	FPWV *addr;
-	FPWV *lock_conf_addr;
-	ulong start;
-	unsigned char ret;
-
-	/*
-	 * first, wait for the WSM to be finished. The rationale for
-	 * waiting for the WSM to become idle for at most
-	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
-	 * because of: (1) erase, (2) program or (3) lock bit
-	 * configuration. So we just wait for the longest timeout of
-	 * the (1)-(3), i.e. the erase timeout.
-	 */
-
-	/* wait at least 35ns (W12) before issuing Read Status Register */
-	udelay(1);
-	addr = (FPWV *) info->start[sector];
-	*addr = (FPW) INTEL_STATUS;
-
-	start = get_timer (0);
-	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			*addr = (FPW) INTEL_RESET; /* restore read mode */
-			printf("WSM busy too long, can't get prot status\n");
-			return 1;
-		}
-	}
-
-	/* issue the Read Identifier Codes command */
-	*addr = (FPW) INTEL_READID;
-
-	/* wait at least 35ns (W12) before reading */
-	udelay(1);
-
-	/* Intel example code uses offset of 4 for 8-bit flash */
-	lock_conf_addr = (FPWV *) info->start[sector] + 4;
-	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
-	/* put flash back in read mode */
-	*addr = (FPW) INTEL_RESET;
-
-	return ret;
-}
-
-
-/*
- * Checks if "bank1" and "bank2" are on the same chip.  Returns 1 if they
- * are and 0 otherwise.
- */
-static unsigned char same_chip_banks (int bank1, int bank2)
-{
-	unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
-		{1, 1, 0, 0},
-		{1, 1, 0, 0},
-		{0, 0, 1, 1},
-		{0, 0, 1, 1}
-	};
-	return same_chip[bank1][bank2];
-}
-
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start;
-	int rcode = 0, intel = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf ("- missing\n");
-		else
-			printf ("- no sectors to erase\n");
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		type = (info->flash_id & FLASH_VENDMASK);
-		if ((type != FLASH_MAN_AMD)) {
-			printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-			return 1;
-		}
-	}
-
-	if (type == FLASH_MAN_INTEL)
-		intel = 1;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	start = get_timer (0);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer (0);
-
-			if (intel) {
-				*addr = (FPW) 0x00500050;	/* clear status register */
-				*addr = (FPW) 0x00200020;	/* erase setup */
-				*addr = (FPW) 0x00D000D0;	/* erase confirm */
-			} else {
-				FPWV *base;	/* first address in bank */
-
-				base = (FPWV *) (CONFIG_SYS_AMD_BASE);
-				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
-				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-				*addr = (FPW) 0x00300030;	/* erase sector */
-			}
-
-			while (((status =
-				 *addr) & (FPW) 0x00800080) !=
-			       (FPW) 0x00800080) {
-				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					if (intel) {
-						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
-						*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
-					} else
-						*addr = (FPW) 0x00F000F0;	/* reset to read mode */
-
-					rcode = 1;
-					break;
-				}
-			}
-
-			if (intel) {
-				*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
-				*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
-			} else
-				*addr = (FPW) 0x00F000F0;	/* reset to read mode */
-
-			printf (" done\n");
-		}
-	}
-	if (flag)
-		enable_interrupts();
-
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-	    {
-		FPW data = 0;	/* 16 or 32 bit word, matches flash bus width */
-		int bytes;	/* number of bytes to program in current word */
-		int left;	/* number of bytes left to program */
-		int i, res;
-
-		for (left = cnt, res = 0;
-		     left > 0 && res == 0;
-		     addr += sizeof (data), left -=
-		     sizeof (data) - bytes) {
-
-			bytes = addr & (sizeof (data) - 1);
-			addr &= ~(sizeof (data) - 1);
-
-			/* combine source and destination data so can program
-			 * an entire word of 16 or 32 bits
-			 */
-			for (i = 0; i < sizeof (data); i++) {
-				data <<= 8;
-				if (i < bytes || i - bytes >= left)
-					data += *((uchar *) addr + i);
-				else
-					data += *src++;
-			}
-
-			res = write_word_amd (info, (FPWV *) addr,
-					      data);
-		}
-		return res;
-	    }		/* case FLASH_MAN_AMD */
-
-	case FLASH_MAN_INTEL:
-	    {
-		ulong cp, wp;
-		FPW data;
-		int count, i, l, rc, port_width;
-
-		/* get lower word aligned address */
-		wp = addr;
-		port_width = 1;
-
-		/*
-		 * handle unaligned start bytes
-		 */
-		if ((l = addr - wp) != 0) {
-			data = 0;
-			for (i = 0, cp = wp; i < l; ++i, ++cp) {
-				data = (data << 8) | (*(uchar *) cp);
-			}
-
-			for (; i < port_width && cnt > 0; ++i) {
-				data = (data << 8) | *src++;
-				--cnt;
-				++cp;
-			}
-
-			for (; cnt == 0 && i < port_width; ++i, ++cp)
-				data = (data << 8) | (*(uchar *) cp);
-
-			if ((rc =
-			     write_data (info, wp, SWAP (data))) != 0)
-				return (rc);
-			wp += port_width;
-		}
-
-		if (cnt > WR_BLOCK) {
-			/*
-			 * handle word aligned part
-			 */
-			count = 0;
-			while (cnt >= WR_BLOCK) {
-
-				if ((rc =
-				     write_data_block (info,
-						       (ulong) src,
-						       wp)) != 0)
-					return (rc);
-
-				wp += WR_BLOCK;
-				src += WR_BLOCK;
-				cnt -= WR_BLOCK;
-
-				if (count++ > 0x800) {
-					spin_wheel ();
-					count = 0;
-				}
-			}
-		}
-
-		if (cnt < WR_BLOCK) {
-			/*
-			 * handle word aligned part
-			 */
-			count = 0;
-			while (cnt >= port_width) {
-				data = 0;
-				for (i = 0; i < port_width; ++i)
-					data = (data << 8) | *src++;
-
-				if ((rc =
-				     write_data (info, wp,
-						 SWAP (data))) != 0)
-					return (rc);
-
-				wp += port_width;
-				cnt -= port_width;
-				if (count++ > 0x800) {
-					spin_wheel ();
-					count = 0;
-				}
-			}
-		}
-
-		if (cnt == 0)
-			return (0);
-
-		/*
-		 * handle unaligned tail bytes
-		 */
-		data = 0;
-		for (i = 0, cp = wp; i < port_width && cnt > 0;
-		     ++i, ++cp) {
-			data = (data << 8) | *src++;
-			--cnt;
-		}
-
-		for (; i < port_width; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		return (write_data (info, wp, SWAP (data)));
-	    }		/* case FLASH_MAN_INTEL */
-
-	}			/* switch */
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong start;
-	int flag, rc = 0;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto OUT;
-		}
-	}
-
-OUT:
-	*addr = (FPW)0x00FF00FF;	/* restore read mode */
-
-	if (flag)
-		enable_interrupts();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data_block (flash_info_t * info, ulong src, ulong dest)
-{
-	FPWV *srcaddr = (FPWV *) src;
-	FPWV *dstaddr = (FPWV *) dest;
-	ulong start;
-	int flag, i, rc = 0;
-
-	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < WR_BLOCK; i++)
-		if ((*dstaddr++ & 0xff) != 0xff) {
-			printf ("not erased at %08lx (%lx)\n",
-				(ulong)dstaddr, (ulong)*dstaddr);
-			return (2);
-		}
-
-	dstaddr = (FPWV *) dest;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*dstaddr = (FPW) 0x00e800e8;	/* write block setup */
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto OUT;
-		}
-	}
-
-	*dstaddr = (FPW) 0x001f001f;	/* write 32 to buffer */
-	for (i = 0; i < WR_BLOCK; i++)
-		*dstaddr++ = *srcaddr++;
-
-	dstaddr -= 1;
-	*dstaddr = (FPW) 0x00d000d0;	/* write 32 to buffer */
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer (0);
-
-	/* wait while polling the status register */
-	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-
-OUT:
-	*dstaddr = (FPW)0x00FF00FF;	/* restore read mode */
-	if (flag)
-		enable_interrupts();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
-{
-	ulong start;
-	int flag;
-	int res = 0;		/* result, assume success */
-	FPWV *base;		/* first address in flash bank */
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest & data) != data) {
-		return (2);
-	}
-
-	base = (FPWV *) (CONFIG_SYS_AMD_BASE);
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
-	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
-	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
-
-	*dest = data;		/* start programming the data */
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	start = get_timer (0);
-
-	/* data polling for D7 */
-	while (res == 0
-	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*dest = (FPW) 0x00F000F0;	/* reset bank */
-			res = 1;
-		}
-	}
-
-	return (res);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
-	ulong start;
-	int i, j;
-	int curr_bank;
-	int bank;
-	int rc = 0;
-	FPWV *addr = (FPWV *) (info->start[sector]);
-	int flag = disable_interrupts ();
-
-	/*
-	 * 29F040B AMD flash does not support software protection/unprotection,
-	 * the only way to protect the AMD flash is marked it as prot bit.
-	 * This flash only support hardware protection, by supply or not supply
-	 * 12vpp to the flash
-	 */
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		info->protect[sector] = prot;
-
-		return 0;
-	}
-
-	*addr = INTEL_CLEAR;	/* Clear status register    */
-	if (prot) {		/* Set sector lock bit      */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
-		*addr = INTEL_PROTECT;	/* set                      */
-	} else {		/* Clear sector lock bit    */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
-		*addr = INTEL_CONFIRM;	/* clear                    */
-	}
-
-	start = get_timer (0);
-
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-			printf ("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
-			(uint) addr, (uint) * addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 */
-	if (!prot) {
-		/*
-		 * re-locking must be done for all banks that belong on one
-		 * FLASH chip, as all the sectors on the chip were unlocked
-		 * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
-		 * that banks never span chips, in particular chips which
-		 * support h/w protection differently).
-		 */
-
-		/* find the current bank number */
-		curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
-		for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
-			if (&flash_info[j] == info) {
-				curr_bank = j;
-			}
-		}
-		if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
-			printf("Error: can't determine bank number!\n");
-		}
-
-		for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
-			if (!same_chip_banks(curr_bank, bank)) {
-				continue;
-			}
-			info = &flash_info[bank];
-			for (i = 0; i < info->sector_count; i++) {
-				if (info->protect[i]) {
-					start = get_timer (0);
-					addr = (FPWV *) (info->start[i]);
-					*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
-					*addr = INTEL_PROTECT;	/* set              */
-					while ((*addr & INTEL_FINISHED) !=
-					       INTEL_FINISHED) {
-						if (get_timer (start) >
-						    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-							printf ("Flash lock bit operation timed out\n");
-							rc = 1;
-							break;
-						}
-					}
-				}
-			}
-		}
-
-		/*
-		 * get the s/w sector protection status in sync with the h/w,
-		 * in case something went wrong during the re-locking.
-		 */
-		flash_sync_real_protect(info); /* resets flash to read  mode */
-	}
-
-	if (flag)
-		enable_interrupts ();
-
-	*addr = INTEL_RESET;	/* Reset to read array mode */
-
-	return rc;
-}