update/fix AcTux1 board

Signed-off-by: Michael Schwingen <michael@schwingen.org>

1 files changed, 55 insertions, 50 deletions

diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
index 85e3f9e..2f631b7 100644
--- a/board/actux1/actux1.c
+++ b/board/actux1/actux1.c
@@ -37,49 +37,57 @@
 #include <asm/arch/ixp425.h>
 #include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 #include "actux1_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: HwRel */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
 
-	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
+	/* Setup GPIOs for PCI INTA */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
 
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	/* Setup GPIOs for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: HwRel */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
-
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
 
-	ACTUX1_LED1 (2);
-	ACTUX1_LED2 (2);
-	ACTUX1_LED3 (0);
-	ACTUX1_LED4 (0);
-	ACTUX1_LED5 (0);
-	ACTUX1_LED6 (0);
-	ACTUX1_LED7 (0);
+	ACTUX1_LED1(2);
+	ACTUX1_LED2(2);
+	ACTUX1_LED3(0);
+	ACTUX1_LED4(0);
+	ACTUX1_LED5(0);
+	ACTUX1_LED6(0);
+	ACTUX1_LED7(0);
 
-	ACTUX1_HS (ACTUX1_HS_DCD);
+	ACTUX1_HS(ACTUX1_HS_DCD);
 
 	return 0;
 }
@@ -87,21 +95,21 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-1 rev.");
-	putc (ACTUX1_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-1 rev.");
+	putc(ACTUX1_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts(", serial# ");
 		puts(buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
 /*************************************************************************
@@ -110,39 +118,36 @@ int checkboard (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX1_BOARDREL;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init (struct pci_controller *hose);
 
-void pci_init_board (void)
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
 {
-	extern void pci_ixp_init (struct pci_controller *hose);
-	pci_ixp_init (&hose);
+	pci_ixp_init(&hose);
 }
 #endif
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	u16 id1, id2;
 
 	/* initialize the PHY */
-	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
 
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
 
 	id2 &= 0xFFF0;		/* mask out revision bits */
 
@@ -153,9 +158,9 @@ void reset_phy (void)
 		 * LED2 (unused) = LINK,
 		 * LED3(red) = Coll
 		 */
-		miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
+		miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
 	} else if (id1 == 0x143 && id2 == 0xbc30) {
 		/* BCM5241: default values are OK */
 	} else
-		printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
+		printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
 }