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| author | York Sun <yorksun@freescale.com> | 2013-03-25 07:39:36 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:13:25 -0500 |
| commit | 431047955b7f9addeda0a7c796618c102711247b (patch) | |
| tree | e98a8d7e5bd94cc49b871efddac86215c5a577dc /board/Seagate | |
| parent | ef00227551273eb1acca299bcb9528e1a2071328 (diff) | |
| download | u-boot-imx-431047955b7f9addeda0a7c796618c102711247b.zip u-boot-imx-431047955b7f9addeda0a7c796618c102711247b.tar.gz u-boot-imx-431047955b7f9addeda0a7c796618c102711247b.tar.bz2 | |
powerpc/b4860qds: Assign DDR address in board file
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/Seagate')
0 files changed, 0 insertions, 0 deletions