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| author | Wolfgang Denk <wd@denx.de> | 2010-07-15 22:48:46 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-07-15 22:48:46 +0200 |
| commit | 93502a5e0adcfc0ce6cf8e3daa7eb9a4f4e53658 (patch) | |
| tree | 85bf8677d8e8095ef18453199a99c5e4131d217d /board/LaCie/edminiv2/edminiv2.c | |
| parent | dce6538f5d21a0def8a4df5328d536abed3e136a (diff) | |
| parent | d6f324d03d7829a1da1dee8b60f91b173a3976f0 (diff) | |
| download | u-boot-imx-93502a5e0adcfc0ce6cf8e3daa7eb9a4f4e53658.zip u-boot-imx-93502a5e0adcfc0ce6cf8e3daa7eb9a4f4e53658.tar.gz u-boot-imx-93502a5e0adcfc0ce6cf8e3daa7eb9a4f4e53658.tar.bz2 | |
Merge branch 'master' of ../master
Diffstat (limited to 'board/LaCie/edminiv2/edminiv2.c')
| -rw-r--r-- | board/LaCie/edminiv2/edminiv2.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 54c0ffe..bb388ed 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> +#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -90,3 +91,38 @@ int board_init(void) return 0; } + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ |