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authorHannes Petermaier <oe5hpm@oevsv.at>2014-10-03 07:30:15 +0200
committerTom Rini <trini@ti.com>2014-10-10 09:44:45 -0400
commit207828e215f7e8331ea3c304b922de9d155fb68e (patch)
treec871865ed1047b16f1c933c4a036dc0396430b0d /board/BuR
parent703a08f2b33b92f64277b0d06d10cc83bdc617f3 (diff)
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board/BuR: fix pinmux for MII Ethernet Interface
The lines COL (collision detect) and CRS (carrier sense) needs to be connected and muxed to the CPSW MAC for a proper function in half-duplex Mode of the interface. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/BuR')
-rw-r--r--board/BuR/kwb/mux.c2
-rw-r--r--board/BuR/tseries/mux.c3
2 files changed, 5 insertions, 0 deletions
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index 1a5ffd5..ecb2e7a 100644
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = {
};
static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 210ac71..0ba25ee 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = {
};
static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
@@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = {
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+ {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
/*
* MII2_CRS is shared with
* NAND_WAIT0