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authorDave Liu <daveliu@freescale.com>2008-11-21 16:31:22 +0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 (patch)
tree272a979e6e9ed0ae0ab583068657c33793b4355c /blackfin_config.mk
parentaca5f018a8386b85469482ed9867e3e29a2437d0 (diff)
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fsl-ddr: update the bit mask for DDR3 controller
According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
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