Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

6 files changed, 341 insertions, 5 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 0f69ef9..2fee995 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
 
 	debug("\n\n");
 
+#if defined(CONFIG_DDR_RFDC_FIXED)
+	mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+	size = 512;
+	rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
+	mfsdram(SDRAM_RDCC, rdcc);	/* record this value */
+	cal->rdcc = rdcc;
+#else /* CONFIG_DDR_RFDC_FIXED */
 	in_window = 0;
 	rdcc = 0;
 
@@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
 		rffd_average = SDRAM_RFDC_RFFD_MAX;
 
 	mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+#endif /* CONFIG_DDR_RFDC_FIXED */
 
 	rffd = rffd_average;
 	in_window = 0;
@@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void)
 		debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
 				rqdc_reg);
 
+#if defined(CONFIG_DDR_RFDC_FIXED)
+		mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
+#else /* CONFIG_DDR_RFDC_FIXED */
 		mfsdram(SDRAM_RFDC, rfdc_reg);
 		rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
 		mtsdram(SDRAM_RFDC, rfdc_reg |
 				SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
+#endif /* CONFIG_DDR_RFDC_FIXED */
 
 		mfsdram(SDRAM_RFDC, rfdc_reg);
 		debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile
index 88d53fb..c9c1a33 100644
--- a/arch/powerpc/cpu/ppc4xx/Makefile
+++ b/arch/powerpc/cpu/ppc4xx/Makefile
@@ -51,6 +51,9 @@ COBJS	+= cpu_init.o
 COBJS	+= denali_data_eye.o
 COBJS	+= denali_spd_ddr2.o
 COBJS	+= ecc.o
+ifdef CONFIG_CMD_ECCTEST
+COBJS	+= cmd_ecctest.o
+endif
 COBJS	+= fdt.o
 COBJS	+= interrupts.o
 COBJS	+= iop480_uart.o
diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
new file mode 100644
index 0000000..b4eac40
--- /dev/null
+++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
+    defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
+
+#if defined(CONFIG_405EX)
+/*
+ * Currently only 405EX uses 16bit data bus width as an alternative
+ * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
+ */
+#define SDRAM_DATA_ALT_WIDTH	2
+#else
+#define SDRAM_DATA_ALT_WIDTH	8
+#endif
+
+#if defined(CONFIG_SYS_OCM_BASE)
+#define CONFIG_FUNC_ISRAM_ADDR	CONFIG_SYS_OCM_BASE
+#endif
+
+#if defined(CONFIG_SYS_ISRAM_BASE)
+#define CONFIG_FUNC_ISRAM_ADDR	CONFIG_SYS_ISRAM_BASE
+#endif
+
+#if !defined(CONFIG_FUNC_ISRAM_ADDR)
+#error "No internal SRAM/OCM provided!"
+#endif
+
+#define force_inline inline __attribute__ ((always_inline))
+
+static inline void machine_check_disable(void)
+{
+	mtmsr(mfmsr() & ~MSR_ME);
+}
+
+static inline void machine_check_enable(void)
+{
+	mtmsr(mfmsr() | MSR_ME);
+}
+
+/*
+ * These helper functions need to be inlined, since they
+ * are called from the functions running from internal SRAM.
+ * SDRAM operation is forbidden at that time, so calling
+ * functions in SDRAM has to be avoided.
+ */
+static force_inline void wait_ddr_idle(void)
+{
+	u32 val;
+
+	do {
+		mfsdram(SDRAM_MCSTAT, val);
+	} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
+}
+
+static force_inline void recalibrate_ddr(void)
+{
+	u32 val;
+
+	/*
+	 * Rewrite RQDC & RFDC to calibrate again. If this is not
+	 * done, the SDRAM controller is working correctly after
+	 * changing the MCOPT1_MCHK bits.
+	 */
+	mfsdram(SDRAM_RQDC, val);
+	mtsdram(SDRAM_RQDC, val);
+	mfsdram(SDRAM_RFDC, val);
+	mtsdram(SDRAM_RFDC, val);
+}
+
+static force_inline void set_mcopt1_mchk(u32 bits)
+{
+	u32 val;
+
+	wait_ddr_idle();
+	mfsdram(SDRAM_MCOPT1, val);
+	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
+	recalibrate_ddr();
+}
+
+/*
+ * The next 2 functions are copied to internal SRAM/OCM and run
+ * there. No function calls allowed here. No SDRAM acitivity should
+ * be done here.
+ */
+static void inject_ecc_error(void *ptr, int par)
+{
+	u32 val;
+
+	/*
+	 * Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
+	 * 22.2.17.13 ECC Diagnostics
+	 *
+	 * Items 1 ... 5 are already done by now, running from RAM
+	 * with ECC enabled
+	 */
+
+	out_be32(ptr, 0x00000000);
+	val = in_be32(ptr);
+
+	/* 6. Set memory controller to no error checking */
+	set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
+
+	/* 7. Modify one or two bits for error simulation */
+	if (par == 1)
+		out_be32(ptr, in_be32(ptr) ^ 0x00000001);
+	else
+		out_be32(ptr, in_be32(ptr) ^ 0x00000003);
+
+	/* 8. Wait for SDRAM idle */
+	val = in_be32(ptr);
+	set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
+
+	/* Wait for SDRAM idle */
+	wait_ddr_idle();
+
+	/* Continue with 9. in calling function... */
+}
+
+static void rewrite_ecc_parity(void *ptr, int par)
+{
+	u32 current_address = (u32)ptr;
+	u32 end_address;
+	u32 address_increment;
+	u32 mcopt1;
+	u32 val;
+
+	/*
+	 * Fill ECC parity byte again. Otherwise further accesses to
+	 * the failure address will result in exceptions.
+	 */
+
+	/* Wait for SDRAM idle */
+	val = in_be32(0x00000000);
+	set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
+
+	/* ECC bit set method for non-cached memory */
+	mfsdram(SDRAM_MCOPT1, mcopt1);
+	if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
+		address_increment = 4;
+	else
+		address_increment = SDRAM_DATA_ALT_WIDTH;
+	end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
+
+	while (current_address < end_address) {
+		*((unsigned long *)current_address) = 0;
+		current_address += address_increment;
+	}
+
+	set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
+
+	/* Wait for SDRAM idle */
+	wait_ddr_idle();
+}
+
+static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 old_val;
+	u32 val;
+	u32 *ptr;
+	void (*sram_func)(u32 *, int);
+	int error;
+
+	if (argc < 3) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
+	error = simple_strtoul(argv[2], NULL, 16);
+	if ((error < 1) || (error > 2)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	printf("Using address %p for %d bit ECC error injection\n",
+	       ptr, error);
+
+	/*
+	 * Save value to restore it later on
+	 */
+	old_val = in_be32(ptr);
+
+	/*
+	 * Copy ECC injection function into internal SRAM/OCM
+	 */
+	sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
+	memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
+
+	/*
+	 * Disable interrupts and exceptions before calling this
+	 * function in internal SRAM/OCM
+	 */
+	disable_interrupts();
+	machine_check_disable();
+	eieio();
+
+	/*
+	 * Jump to ECC simulation function in internal SRAM/OCM
+	 */
+	(*sram_func)(ptr, error);
+
+	/* 10. Read the corresponding address */
+	val = in_be32(ptr);
+
+	/*
+	 * Read and print ECC status register/info:
+	 * The faulting address is only known upon uncorrectable ECC
+	 * errors.
+	 */
+	mfsdram(SDRAM_ECCES, val);
+	if (val & SDRAM_ECCES_CE)
+		printf("ECC: Correctable error\n");
+	if (val & SDRAM_ECCES_UE) {
+		printf("ECC: Uncorrectable error at 0x%02x%08x\n",
+		       mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
+	}
+
+	/*
+	 * Clear pending interrupts/exceptions
+	 */
+	mtsdram(SDRAM_ECCES, 0xffffffff);
+	mtdcr(SDRAM_ERRSTATLL, 0xff000000);
+	set_mcsr(get_mcsr());
+
+	/* Now enable interrupts and exceptions again */
+	eieio();
+	machine_check_enable();
+	enable_interrupts();
+
+	/*
+	 * The ECC parity byte need to be re-written for the
+	 * corresponding address. Otherwise future accesses to it
+	 * will result in exceptions.
+	 *
+	 * Jump to ECC parity generation function
+	 */
+	memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
+	(*sram_func)(ptr, 0);
+
+	/*
+	 * Restore value in corresponding address
+	 */
+	out_be32(ptr, old_val);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	ecctest,	3,	0,	do_ecctest,
+	"Test ECC by single and double error bit injection",
+	"address 1/2"
+);
+
+#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
+#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index f105605..49f28d9 100644
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
 
 		/* clear ECC error repoting registers */
 		mtsdram(SDRAM_ECCES, 0xffffffff);
-		mtdcr(0x4c, 0xffffffff);
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+		/*
+		 * IBM DDR(1) core (440GX):
+		 * Clear Mx bits in SDRAM0_BESR0/1
+		 */
+		mtsdram(SDRAM0_BESR0, 0xffffffff);
+		mtsdram(SDRAM0_BESR1, 0xffffffff);
+#elif defined(CONFIG_440)
+		/*
+		 * 440/460 DDR2 core:
+		 * Clear EMID (Error PLB Master ID) in MQ0_ESL
+		 */
+		mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
+#else
+		/*
+		 * 405EX(r) DDR2 core:
+		 * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
+		 */
+		mtsdram(SDRAM_BESR, 0xf0000000);
+#endif
 
 		mtsdram(SDRAM_MCOPT1,
 			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index 1616772..b5562ad 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs)
 		/* Clear MCSR */
 		mtspr(SPRN_MCSR, val);
 	}
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+	/*
+	 * Read and print ECC status register/info:
+	 * The faulting address is only known upon uncorrectable ECC
+	 * errors.
+	 */
+	mfsdram(SDRAM_ECCES, val);
+	if (val & SDRAM_ECCES_CE)
+		printf("ECC: Correctable error\n");
+	if (val & SDRAM_ECCES_UE) {
+		printf("ECC: Uncorrectable error at 0x%02x%08x\n",
+		       mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
+	}
+#endif /* CONFIG_DDR_ECC ... */
+
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	mfsdram(DDR0_00, val) ;
 	printf("DDR0: DDR0_00 %lx\n", val);
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index d9506e2..4ec1ef8 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -63,6 +63,8 @@
 #define SDRAM_CFG0	0x20	/* memory controller options 0		*/
 #define SDRAM_CFG1	0x21	/* memory controller options 1		*/
 
+#define SDRAM0_BESR0	0x0000	/* bus error status reg 0		*/
+#define SDRAM0_BESR1	0x0008	/* bus error status reg 1		*/
 #define SDRAM0_BEAR	0x0010	/* bus error address reg		*/
 #define SDRAM0_SLIO	0x0018	/* ddr sdram slave interface options	*/
 #define SDRAM0_CFG0	0x0020	/* ddr sdram options 0			*/
@@ -363,6 +365,7 @@
 /*
  * Memory controller registers
  */
+#ifdef CONFIG_405EX
 #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
 #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
@@ -371,11 +374,10 @@
 #define SDRAM_WMIRQT	0x07	/* PLB write master interrupt (test/set)     */
 #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
 #define SDRAM_PUABA	0x09	/* PLB upper address base                    */
-#ifndef CONFIG_405EX
-#define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#else
 #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#endif
+#else /* CONFIG_405EX */
+#define SDRAM_MCSTAT	0x14	/* memory controller status                  */
+#endif /* CONFIG_405EX */
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */