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| author | Wolfgang Denk <wd@denx.de> | 2011-10-29 09:37:52 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-11-03 20:39:49 +0100 |
| commit | 32bb34a76815520549dd252bb7491d4567f84e0d (patch) | |
| tree | 1da64c4e239d3f4d3c15c1f800c18a481ca55bf3 /arch | |
| parent | 3d458d2dfb06a62d40037d48a37b715c135fd3c8 (diff) | |
| download | u-boot-imx-32bb34a76815520549dd252bb7491d4567f84e0d.zip u-boot-imx-32bb34a76815520549dd252bb7491d4567f84e0d.tar.gz u-boot-imx-32bb34a76815520549dd252bb7491d4567f84e0d.tar.bz2 | |
4xx_uart.c: fix GCC 4.6 build warnings
Fix:
4xx_uart.c: In function 'get_serial_clock':
4xx_uart.c:204:6: warning: variable 'tmp' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/4xx_uart.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index 2660aa8..38ba60b 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -200,9 +200,6 @@ int get_serial_clock(void) { u32 clk; u32 udiv; -#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP) - u32 tmp; -#endif #if !defined(CONFIG_405EZ) u32 reg; #endif @@ -216,7 +213,6 @@ int get_serial_clock(void) */ #if defined(CONFIG_405CR) || defined(CONFIG_405GP) - tmp = 0; reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; @@ -227,8 +223,11 @@ int get_serial_clock(void) #ifdef CONFIG_SYS_405_UART_ERRATA_59 udiv = 31; /* Errata 59: stuck at 31 */ #else /* CONFIG_SYS_405_UART_ERRATA_59 */ - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; + { + u32 tmp = CONFIG_SYS_BASE_BAUD * 16; + + udiv = (clk + tmp / 2) / tmp; + } if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; #endif /* CONFIG_SYS_405_UART_ERRATA_59 */ @@ -243,12 +242,15 @@ int get_serial_clock(void) #endif /* CONFIG_405CR */ #if defined(CONFIG_405EP) - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; + { + u32 tmp = CONFIG_SYS_BASE_BAUD * 16; + + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + } reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */ reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */ mtdcr(CPC0_UCR, reg); |