Merge branch 'next' of ../next

36 files changed, 920 insertions, 93 deletions

diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
new file mode 100644
index 0000000..76bd06d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	= cpu.o timer.o dram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
new file mode 100644
index 0000000..62aa175
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
new file mode 100644
index 0000000..eacec23
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
new file mode 100644
index 0000000..5d911c5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
new file mode 100644
index 0000000..d5d125a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif	/* __ASSEMBLY__ */
+
+#if defined (CONFIG_ARMADA100)
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_TIMER_BASE	0xD4014000
+#define ARMD1_APBC1_BASE	0xD4015000
+#define ARMD1_APBC2_BASE	0xD4015800
+#define ARMD1_UART1_BASE	0xD4017000
+#define ARMD1_UART2_BASE	0xD4018000
+#define ARMD1_GPIO_BASE		0xD4019000
+#define ARMD1_SSP1_BASE		0xD401B000
+#define ARMD1_SSP2_BASE		0xD401C000
+#define ARMD1_MFPR_BASE		0xD401E000
+#define ARMD1_SSP3_BASE		0xD401F000
+#define ARMD1_SSP4_BASE		0xD4020000
+#define ARMD1_SSP5_BASE		0xD4021000
+#define ARMD1_UART3_BASE	0xD4026000
+#define ARMD1_MPMU_BASE		0xD4050000
+#define ARMD1_APMU_BASE		0xD4282800
+#define ARMD1_CPU_BASE		0xD4282C00
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
new file mode 100644
index 0000000..0518a6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/cpu.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
new file mode 100644
index 0000000..d21a79f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -0,0 +1,67 @@
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD	MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP107_UART1_RXD	MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP108_UART1_RXD	MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP108_UART1_TXD	MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP109_UART1_CTS	MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP109_UART1_RTS	MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_RTS	MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_CTS	MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_RI		MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_DSR	MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DTR	MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DCD	MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART2 */
+#define MFP47_UART2_RXD		MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD		MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP88_UART2_RXD		MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP89_UART2_TXD		MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART3 */
+#define MFPO8_UART3_RXD		MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFPO9_UART3_TXD		MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+
+#endif /* __ARMADA100_MFP_H */
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h
new file mode 100644
index 0000000..347aa89
--- /dev/null
+++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MISC_H
+#define __MISC_H
+
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS	8	/* Per register */
+#define PIN_MUX_FIELD_SIZE	4	/* n in bits */
+#define PIN_MUX_FIELD_MASK	((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+	dv_reg		*mux;		/* Address of mux register */
+	unsigned char	value;		/* Value to set in field */
+	unsigned char	field;		/* field number */
+};
+
+/* pin table definition */
+struct pinmux_resource {
+	const struct pinmux_config	*pins;
+	const int 			n_pins;
+};
+
+#define PINMUX_ITEM(item) { \
+				.pins = item, \
+				.n_pins = ARRAY_SIZE(item) \
+			  }
+
+#define HAWKBOARD_KICK0_UNLOCK          0x83e70b13
+#define HAWKBOARD_KICK1_UNLOCK          0x95a4f1e0
+
+struct lpsc_resource {
+	const int	lpsc_no;
+};
+
+int dvevm_read_mac_address(uint8_t *buf);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+				    int n_items);
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+void davinci_emac_mii_mode_sel(int mode_sel);
+#endif
+#if defined(CONFIG_SOC_DA8XX)
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    const int n_items);
+#endif
+
+#endif /* __MISC_H */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 3520cf8..b95fa97 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -133,7 +133,8 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_PSC1_BASE			0x01e27000
 #define DAVINCI_SPI0_BASE			0x01c41000
 #define DAVINCI_USB_OTG_BASE			0x01e00000
-#define DAVINCI_SPI1_BASE			0x01e12000
+#define DAVINCI_SPI1_BASE			(cpu_is_da830() ? \
+						0x01e12000 : 0x01f0e000)
 #define DAVINCI_GPIO_BASE			0x01e26000
 #define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
@@ -149,7 +150,12 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
 #define DAVINCI_INTC_BASE			0xfffee000
 #define DAVINCI_BOOTCFG_BASE			0x01c14000
+#define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
 
+#define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
+#define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
+#define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
+#define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
 #endif /* CONFIG_SOC_DA8XX */
 
 /* Power and Sleep Controller (PSC) Domains */
@@ -363,6 +369,9 @@ struct davinci_pllc_regs {
 #define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
+#define ASYNC3          get_async3_src()
+#define PLL1_SYSCLK2		((1 << 16) | 0x2)
+#define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
 /* Clock IDs */
 enum davinci_clk_ids {
 	DAVINCI_SPI0_CLKID = 2,
@@ -379,7 +388,10 @@ int clk_get(enum davinci_clk_ids id);
 /* Boot config */
 struct davinci_syscfg_regs {
 	dv_reg	revid;
-	dv_reg	rsvd[71];
+	dv_reg	rsvd[13];
+	dv_reg	kick0;
+	dv_reg	kick1;
+	dv_reg	rsvd1[56];
 	dv_reg	pinmux[20];
 	dv_reg	suspsrc;
 	dv_reg	chipsig;
@@ -442,6 +454,27 @@ struct davinci_uart_ctrl_regs {
 #define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
 #define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
 
+static inline int cpu_is_da830(void)
+{
+	unsigned int jtag_id	= REG(JTAG_ID_REG);
+	unsigned short part_no	= (jtag_id >> 12) & 0xffff;
+
+	return ((part_no == 0xb7df) ? 1 : 0);
+}
+static inline int cpu_is_da850(void)
+{
+	unsigned int jtag_id    = REG(JTAG_ID_REG);
+	unsigned short part_no  = (jtag_id >> 12) & 0xffff;
+
+	return ((part_no == 0xb7d1) ? 1 : 0);
+}
+
+static inline int get_async3_src(void)
+{
+	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
+			PLL1_SYSCLK2 : 2;
+}
+
 #endif /* CONFIG_SOC_DA8XX */
 
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c
index 5129a03..09ef1d2 100644
--- a/arch/m68k/cpu/mcf5227x/cpu.c
+++ b/arch/m68k/cpu/mcf5227x/cpu.c
@@ -33,7 +33,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index 582aec9..2376f97 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
 
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index fb60462..571d078 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -38,7 +38,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef	CONFIG_M5208
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
@@ -141,7 +141,7 @@ int checkcpu(void)
 	return 0;
 }
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	/* Call the board specific reset actions first. */
 	if(board_reset) {
@@ -176,7 +176,7 @@ int watchdog_init(void)
 #endif
 
 #ifdef	CONFIG_M5272
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
@@ -256,7 +256,7 @@ int watchdog_init(void)
 #endif				/* #ifdef CONFIG_M5272 */
 
 #ifdef	CONFIG_M5275
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
@@ -336,7 +336,7 @@ int checkcpu(void)
 	return 0;
 }
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 	return 0;
@@ -353,7 +353,7 @@ int checkcpu(void)
 	return 0;
 }
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	/* enable watchdog, set timeout to 0 and wait */
 	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
@@ -383,7 +383,7 @@ int checkcpu(void)
 	return 0;
 }
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	/* enable watchdog, set timeout to 0 and wait */
 	mbar_writeByte(SIM_SYPCR, 0xc0);
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 0af4969..3346784 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index 182521c..323a54e 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c
index f9a4b64..7590f2c 100644
--- a/arch/m68k/cpu/mcf547x_8x/cpu.c
+++ b/arch/m68k/cpu/mcf547x_8x/cpu.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
diff --git a/arch/nios2/cpu/config.mk b/arch/nios2/cpu/config.mk
deleted file mode 100644
index f228d72..0000000
--- a/arch/nios2/cpu/config.mk
+++ /dev/null
@@ -1,24 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS +=
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index d9c6544..ef360ee 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -40,7 +40,7 @@ int checkcpu (void)
 	return (0);
 }
 
-int do_reset(void)
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	disable_interrupts();
 	/* indirect call to go beyond 256MB limitation of toolchain */
diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c
index ab6f11d..b6a31b4 100644
--- a/arch/powerpc/cpu/74xx_7xx/cpu.c
+++ b/arch/powerpc/cpu/74xx_7xx/cpu.c
@@ -234,8 +234,7 @@ soft_restart(unsigned long addr)
     !defined(CONFIG_ELPPC)   && \
     !defined(CONFIG_PPMC7XX)
 /* no generic way to do board reset. simply call soft_reset. */
-void
-do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong addr;
 	/* flush and disable I/D cache */
@@ -263,7 +262,12 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
 #endif
 	soft_restart(addr);
-	while(1);	/* not reached */
+
+	/* not reached */
+	while(1)
+		;
+
+	return 1;
 }
 #endif
 
diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
index 771a845..8429f33 100644
--- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds
+++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
@@ -43,13 +43,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
index 361e714..ab9303f 100644
--- a/arch/powerpc/cpu/mpc512x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc512x/u-boot.lds
@@ -37,14 +37,15 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
     *(.fixup)
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds
index b7fd4bc..69bd7aa 100644
--- a/arch/powerpc/cpu/mpc5xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds
@@ -46,13 +46,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_)>>2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
index eeeff6c..7e3b70a 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
@@ -41,13 +41,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds
index 63cbbd7..72ff671 100644
--- a/arch/powerpc/cpu/mpc8220/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8220/u-boot.lds
@@ -40,13 +40,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds
index e7f2837..3b9299c 100644
--- a/arch/powerpc/cpu/mpc824x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc824x/u-boot.lds
@@ -41,13 +41,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds
index ad2ce37..c76555e 100644
--- a/arch/powerpc/cpu/mpc8260/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8260/u-boot.lds
@@ -40,13 +40,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 81a7ace..752a175 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -39,13 +39,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index fc5d951..55ee36d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -199,7 +199,7 @@ int checkcpu (void)
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 85042c5..67d7763 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -54,13 +54,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index 4e90fd2..ffcc8e6 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -123,8 +123,7 @@ checkcpu(void)
 }
 
 
-void
-do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -137,6 +136,8 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	while (1)
 		;
+
+	return 1;
 }
 
 
diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
index 49a4c78..c550ef5 100644
--- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds
@@ -45,13 +45,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 9634deb..95df1d9 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -416,7 +416,6 @@ static void	test(void);
 static void	DQS_calibration_process(void);
 #endif
 #endif
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
 static unsigned char spd_read(uchar chip, uint addr)
 {
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 0e75794..2218508 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -48,21 +48,23 @@
  *-------------------------------------------------------------------------------
  */
 
-/*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
- *
+/*
+ * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
  *
- *  The processor starts at 0xfffffffc and the code is executed
- *  from flash/rom.
- *  in memory, but as long we don't jump around before relocating.
- *  board_init lies at a quite high address and when the cpu has
- *  jumped there, everything is ok.
- *  This works because the cpu gives the FLASH (CS0) the whole
- *  address space at startup, and board_init lies as a echo of
- *  the flash somewhere up there in the memorymap.
+ * The following description only applies to the NOR flash style booting.
+ * NAND booting is different. For more details about NAND booting on 4xx
+ * take a look at doc/README.nand-boot-ppc440.
  *
- *  board_init will change CS0 to be positioned at the correct
- *  address and (s)dram will be positioned at address 0
+ * The CPU starts at address 0xfffffffc (last word in the address space).
+ * The U-Boot image therefore has to be located in the "upper" area of the
+ * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
+ * the boot chip-select (CS0) is quite big and covers this area. On the
+ * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
+ * reconfigure this CS0 (and other chip-selects as well when configured
+ * this way) in the boot process to the "correct" values matching the
+ * board layout.
  */
+
 #include <asm-offsets.h>
 #include <config.h>
 #include <asm/ppc4xx.h>
@@ -265,7 +267,7 @@
 	/* NOTREACHED - board_init_f() does not return */
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
 	/*
 	 * 4xx RAM-booting U-Boot image is started from offset 0
 	 */
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index dac0e5b..656f59a 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -23,8 +23,12 @@
 #include "config.h"	/* CONFIG_BOARDDIR */
 
 #ifndef RESET_VECTOR_ADDRESS
+#ifdef CONFIG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	CONFIG_RESET_VECTOR_ADDRESS
+#else
 #define RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
+#endif
 
 OUTPUT_ARCH(powerpc)
 
@@ -55,13 +59,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
@@ -100,7 +105,11 @@ SECTIONS
      * start.o, since the first shadow TLB only covers 4k
      * of address space.
      */
+#ifdef CONFIG_INIT_TLB
+    CONFIG_INIT_TLB (.bootpg)
+#else
     CONFIG_BOARDDIR/init.o	(.bootpg)
+#endif
   } :text = 0xffff
 #endif
 
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 4c3e2fe..116d81b 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -47,7 +47,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 extern ulong get_effective_memsize(void);
 static ulong get_sp (void);
 static void set_clocks_in_mhz (bd_t *kbd);
diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c
index 1ec6818..19a56db 100644
--- a/arch/powerpc/lib/kgdb.c
+++ b/arch/powerpc/lib/kgdb.c
@@ -12,11 +12,13 @@ void breakinst(void);
 int
 kgdb_setjmp(long *buf)
 {
-	asm ("mflr 0; stw 0,0(%0);"
-	     "stw 1,4(%0); stw 2,8(%0);"
-	     "mfcr 0; stw 0,12(%0);"
-	     "stmw 13,16(%0)"
-	     : : "r" (buf));
+	unsigned long temp;
+
+	asm volatile("mflr %0; stw %0,0(%1);"
+	     "stw %%r1,4(%1); stw %%r2,8(%1);"
+	     "mfcr %0; stw %0,12(%1);"
+	     "stmw %%r13,16(%1)"
+	     : "=&r"(temp) : "r" (buf));
 	/* XXX should save fp regs as well */
 	return 0;
 }
@@ -24,13 +26,16 @@ kgdb_setjmp(long *buf)
 void
 kgdb_longjmp(long *buf, int val)
 {
+	unsigned long temp;
+
 	if (val == 0)
 		val = 1;
-	asm ("lmw 13,16(%0);"
-	     "lwz 0,12(%0); mtcrf 0x38,0;"
-	     "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);"
-	     "mtlr 0; mr 3,%1"
-	     : : "r" (buf), "r" (val));
+
+	asm volatile("lmw %%r13,16(%1);"
+	     "lwz %0,12(%1); mtcrf 0x38,%0;"
+	     "lwz %0,0(%1); lwz %%r1,4(%1); lwz %%r2,8(%1);"
+	     "mtlr %0; mr %%r3,%2"
+	     : "=&r"(temp) : "r" (buf), "r" (val));
 }
 
 static inline unsigned long
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 2909961..34633c3 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -78,6 +78,8 @@ unsigned long ticks2usec(unsigned long ticks)
 
 int init_timebase (void)
 {
+	unsigned long temp;
+
 #if defined(CONFIG_5xx) || defined(CONFIG_8xx)
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
@@ -86,7 +88,8 @@ int init_timebase (void)
 #endif
 
 	/* reset */
-	asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
+	asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
+	     : "=&r"(temp) );
 
 #if defined(CONFIG_5xx) || defined(CONFIG_8xx)
 	/* enable */