Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx

6 files changed, 428 insertions, 89 deletions

diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index 1719c66..9cfdb0f 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -29,6 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 START	= start.o
 COBJS-y	:= cpu.o
 COBJS-y	+= traps.o
+COBJS-y += common.o
 COBJS-y += cpu_init.o
 COBJS-y += fixed_sdram.o
 COBJS-y += i2c.o
diff --git a/arch/powerpc/cpu/mpc512x/common.c b/arch/powerpc/cpu/mpc512x/common.c
new file mode 100644
index 0000000..180d323
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/common.c
@@ -0,0 +1,25 @@
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR	(CONFIG_SYS_POST_WORD_ADDR)
+#else
+#error echo "No POST word address defined"
+#endif
+
+void post_word_store(ulong a)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	out_be32(save_addr, a);
+}
+
+ulong post_word_load(void)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	return in_be32(save_addr);
+}
+#endif  /* CONFIG_POST || CONFIG_LOGBUFFER */
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index 9361161..f8d19a0 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -34,6 +34,8 @@
 #include <video_fb.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_FSL_DIU_LOGO_BMP
 extern unsigned int FSL_Logo_BMP[];
 #else
@@ -65,10 +67,11 @@ void diu_set_pixel_clock(unsigned int pixclock)
 char *valid_bmp(char *addr)
 {
 	unsigned long h_addr;
+	bd_t *bd = gd->bd;
 
 	h_addr = simple_strtoul(addr, NULL, 16);
-	if (h_addr < CONFIG_SYS_FLASH_BASE ||
-			h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+	if (h_addr < bd->bi_flashstart ||
+	    h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
 		printf("bmp addr %lx is not a valid flash address\n", h_addr);
 		return 0;
 	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
@@ -84,8 +87,13 @@ int mpc5121_diu_init(void)
 	char *bmp = NULL;
 	char *bmp_env;
 
+#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
+	xres = CONFIG_VIDEO_XRES;
+	yres = CONFIG_VIDEO_YRES;
+#else
 	xres = 1024;
 	yres = 768;
+#endif
 	pixel_format = 0x88883316;
 
 	debug("mpc5121_diu_init\n");
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
index 442b5fc..550cbd0 100644
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -78,7 +78,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 			u32 *dram_init_seq, int seq_sz)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
 	u32 msize_log2 = __ilog2(msize);
 	u32 i;
 
@@ -91,7 +91,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	}
 
 	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+	out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
 
 	/* Initialize DDR Local Window */
 	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
@@ -148,5 +148,10 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
 	out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
 
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+	/* Fix DDR Local Window for new size */
+	out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
 	return msize;
 }
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
index ec2f41b..cb5bbf0 100644
--- a/arch/powerpc/cpu/mpc512x/serial.c
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -32,14 +32,16 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_PSC_CONSOLE)
+#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
 
 static void fifo_init (volatile psc512x_t *psc)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 tfsize, rfsize;
 
 	/* reset Rx & Tx fifo slice */
 	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
@@ -49,8 +51,65 @@ static void fifo_init (volatile psc512x_t *psc)
 	out_be32(&psc->rfintmask, 0);
 	out_be32(&psc->tfintmask, 0);
 
-	out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
-	out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
+#if defined(CONFIG_SERIAL_MULTI)
+	switch (((u32)psc & 0xf00) >> 8) {
+	case 0:
+		tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
+		rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
+		break;
+	case 1:
+		tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
+		rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
+		break;
+	case 2:
+		tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
+		rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
+		break;
+	case 3:
+		tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
+		rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
+		break;
+	case 4:
+		tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
+		rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
+		break;
+	case 5:
+		tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
+		rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
+		break;
+	case 6:
+		tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
+		rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
+		break;
+	case 7:
+		tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
+		rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
+		break;
+	case 8:
+		tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
+		rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
+		break;
+	case 9:
+		tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
+		rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
+		break;
+	case 10:
+		tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
+		rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
+		break;
+	case 11:
+		tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
+		rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
+		break;
+	default:
+		return;
+	}
+#else
+	tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
+	rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+#endif
+	out_be32(&psc->tfsize, tfsize);
+	out_be32(&psc->rfsize, rfsize);
 
 	/* enable Tx & Rx FIFO slice */
 	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
@@ -60,24 +119,47 @@ static void fifo_init (volatile psc512x_t *psc)
 	__asm__ volatile ("sync");
 }
 
-void serial_setbrg(void)
+void serial_setbrg_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 	unsigned long baseclk, div;
+	unsigned long baudrate;
+	char buf[16];
+	char *br_env;
+
+	baudrate = gd->baudrate;
+	if (idx != CONFIG_PSC_CONSOLE) {
+		/* Allows setting baudrate for other serial devices
+		 * on PSCx using environment. If not specified, use
+		 * the same baudrate as for console.
+		 */
+		sprintf(buf, "psc%d_baudrate", idx);
+		br_env = getenv(buf);
+		if (br_env)
+			baudrate = simple_strtoul(br_env, NULL, 10);
+
+		debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+	}
 
-	/* calculate dividor for setting PSC CTUR and CTLR registers */
+	/* calculate divisor for setting PSC CTUR and CTLR registers */
 	baseclk = (gd->ips_clk + 8) / 16;
-	div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+	div = (baseclk + (baudrate / 2)) / baudrate;
 
 	out_8(&psc->ctur, (div >> 8) & 0xff);
 	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
 }
 
-int serial_init(void)
+int serial_init_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+#if defined(CONFIG_SERIAL_MULTI)
+	u32 reg;
+
+	reg = in_be32(&im->clk.sccr[0]);
+	out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
+#endif
 
 	fifo_init (psc);
 
@@ -100,7 +182,7 @@ int serial_init(void)
 	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
 
 	/* set baudrate */
-	serial_setbrg();
+	serial_setbrg_dev(idx);
 
 	/* disable all interrupts */
 	out_be16(&psc->psc_imr, 0);
@@ -113,13 +195,27 @@ int serial_init(void)
 	return 0;
 }
 
-void serial_putc (const char c)
+int serial_uninit_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	u32 reg;
+
+	out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
+	reg = in_be32(&im->clk.sccr[0]);
+	reg &= ~CLOCK_SCCR1_PSC_EN(idx);
+	out_be32(&im->clk.sccr[0], reg);
+
+	return 0;
+}
+
+void serial_putc_dev(unsigned int idx, const char c)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	if (c == '\n')
-		serial_putc ('\r');
+		serial_putc_dev(idx, '\r');
 
 	/* Wait for last character to go. */
 	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
@@ -128,10 +224,10 @@ void serial_putc (const char c)
 	out_8(&psc->tfdata_8, c);
 }
 
-void serial_putc_raw (const char c)
+void serial_putc_raw_dev(unsigned int idx, const char c)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	/* Wait for last character to go. */
 	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
@@ -140,18 +236,16 @@ void serial_putc_raw (const char c)
 	out_8(&psc->tfdata_8, c);
 }
 
-
-void serial_puts (const char *s)
+void serial_puts_dev(unsigned int idx, const char *s)
 {
-	while (*s) {
-		serial_putc (*s++);
-	}
+	while (*s)
+		serial_putc_dev(idx, *s++);
 }
 
-int serial_getc (void)
+int serial_getc_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	/* Wait for a character to arrive. */
 	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
@@ -160,18 +254,18 @@ int serial_getc (void)
 	return in_8(&psc->rfdata_8);
 }
 
-int serial_tstc (void)
+int serial_tstc_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
 }
 
-void serial_setrts(int s)
+void serial_setrts_dev(unsigned int idx, int s)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	if (s) {
 		/* Assert RTS (become LOW) */
@@ -183,11 +277,214 @@ void serial_setrts(int s)
 	}
 }
 
-int serial_getcts(void)
+int serial_getcts_dev(unsigned int idx)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
 
 	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
 }
+#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
+	int serial##port##_init(void) \
+	{ \
+		return serial_init_dev(port); \
+	} \
+	int serial##port##_uninit(void) \
+	{ \
+		return serial_uninit_dev(port); \
+	} \
+	void serial##port##_setbrg(void) \
+	{ \
+		serial_setbrg_dev(port); \
+	} \
+	int serial##port##_getc(void) \
+	{ \
+		return serial_getc_dev(port); \
+	} \
+	int serial##port##_tstc(void) \
+	{ \
+		return serial_tstc_dev(port); \
+	} \
+	void serial##port##_putc(const char c) \
+	{ \
+		serial_putc_dev(port, c); \
+	} \
+	void serial##port##_puts(const char *s) \
+	{ \
+		serial_puts_dev(port, s); \
+	}
+
+#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \
+	name, \
+	bus, \
+	serial##port##_init, \
+	serial##port##_uninit, \
+	serial##port##_setbrg, \
+	serial##port##_getc, \
+	serial##port##_tstc, \
+	serial##port##_putc, \
+	serial##port##_puts, \
+}
+
+#if defined(CONFIG_SYS_PSC1)
+DECLARE_PSC_SERIAL_FUNCTIONS(1);
+struct serial_device serial1_device =
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1");
+#endif
+
+#if defined(CONFIG_SYS_PSC3)
+DECLARE_PSC_SERIAL_FUNCTIONS(3);
+struct serial_device serial3_device =
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3");
+#endif
+
+#if defined(CONFIG_SYS_PSC4)
+DECLARE_PSC_SERIAL_FUNCTIONS(4);
+struct serial_device serial4_device =
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4");
+#endif
+
+#if defined(CONFIG_SYS_PSC6)
+DECLARE_PSC_SERIAL_FUNCTIONS(6);
+struct serial_device serial6_device =
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6");
+#endif
+
+#else
+
+void serial_setbrg(void)
+{
+	serial_setbrg_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_init(void)
+{
+	return serial_init_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_putc(const char c)
+{
+	serial_putc_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_putc_raw(const char c)
+{
+	serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_puts(const char *s)
+{
+	serial_puts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getc(void)
+{
+	return serial_getc_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_tstc(void)
+{
+	return serial_tstc_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_setrts(int s)
+{
+	return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getcts(void)
+{
+	return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+}
 #endif /* CONFIG_PSC_CONSOLE */
+
+#if defined(CONFIG_SERIAL_MULTI)
+#include <stdio_dev.h>
+/*
+ * Routines for communication with serial devices over PSC
+ */
+/* Bitfield for initialized PSCs */
+static unsigned int initialized;
+
+struct stdio_dev *open_port(int num, int baudrate)
+{
+	struct stdio_dev *port;
+	char env_var[16];
+	char env_val[10];
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return NULL;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return NULL;
+
+	if (!test_bit(num, &initialized)) {
+		sprintf(env_var, "psc%d_baudrate", num);
+		sprintf(env_val, "%d", baudrate);
+		setenv(env_var, env_val);
+
+		if (port->start())
+			return NULL;
+
+		set_bit(num, &initialized);
+	}
+
+	return port;
+}
+
+int close_port(int num)
+{
+	struct stdio_dev *port;
+	int ret;
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return -1;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return -1;
+
+	ret = port->stop();
+	clear_bit(num, &initialized);
+
+	return ret;
+}
+
+int write_port(struct stdio_dev *port, char *buf)
+{
+	if (!port || !buf)
+		return -1;
+
+	port->puts(buf);
+
+	return 0;
+}
+
+int read_port(struct stdio_dev *port, char *buf, int size)
+{
+	int cnt = 0;
+
+	if (!port || !buf)
+		return -1;
+
+	if (!size)
+		return 0;
+
+	while (port->tstc()) {
+		buf[cnt++] = port->getc();
+		if (cnt > size)
+			break;
+	}
+
+	return cnt;
+}
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 95350fd..7f9db8b 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -356,6 +356,11 @@ typedef struct ddr512x_config {
 	u32 ddr_time_config2;	/* Timing Configuration Register */
 } ddr512x_config_t;
 
+typedef struct sdram_conf_s {
+	unsigned long size;
+	ddr512x_config_t cfg;
+} sdram_conf_t;
+
 /*
  * DMA/Messaging Unit
  */
@@ -848,10 +853,6 @@ typedef struct ioctrl512x {
 	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
 } ioctrl512x_t;
 
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR		0x00000036
-
 /* IO pin fields */
 #define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
 #define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
@@ -1116,66 +1117,68 @@ typedef struct fifoc512x {
  *
  * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
  * tests indicate that it is 1024 words total.
+ *
+ * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
  */
-#define FIFOC_PSC0_TX_SIZE	0x0	/* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_SIZE	0x04
 #define FIFOC_PSC0_TX_ADDR	0x0
-#define FIFOC_PSC0_RX_SIZE	0x0
-#define FIFOC_PSC0_RX_ADDR	0x0
+#define FIFOC_PSC0_RX_SIZE	0x04
+#define FIFOC_PSC0_RX_ADDR	0x10
 
-#define FIFOC_PSC1_TX_SIZE	0x0
-#define FIFOC_PSC1_TX_ADDR	0x0
-#define FIFOC_PSC1_RX_SIZE	0x0
-#define FIFOC_PSC1_RX_ADDR	0x0
+#define FIFOC_PSC1_TX_SIZE	0x04
+#define FIFOC_PSC1_TX_ADDR	0x20
+#define FIFOC_PSC1_RX_SIZE	0x04
+#define FIFOC_PSC1_RX_ADDR	0x30
 
-#define FIFOC_PSC2_TX_SIZE	0x0
-#define FIFOC_PSC2_TX_ADDR	0x0
-#define FIFOC_PSC2_RX_SIZE	0x0
-#define FIFOC_PSC2_RX_ADDR	0x0
+#define FIFOC_PSC2_TX_SIZE	0x04
+#define FIFOC_PSC2_TX_ADDR	0x40
+#define FIFOC_PSC2_RX_SIZE	0x04
+#define FIFOC_PSC2_RX_ADDR	0x50
 
 #define FIFOC_PSC3_TX_SIZE	0x04
-#define FIFOC_PSC3_TX_ADDR	0x0
+#define FIFOC_PSC3_TX_ADDR	0x60
 #define FIFOC_PSC3_RX_SIZE	0x04
-#define FIFOC_PSC3_RX_ADDR	0x10
-
-#define FIFOC_PSC4_TX_SIZE	0x0
-#define FIFOC_PSC4_TX_ADDR	0x0
-#define FIFOC_PSC4_RX_SIZE	0x0
-#define FIFOC_PSC4_RX_ADDR	0x0
-
-#define FIFOC_PSC5_TX_SIZE	0x0
-#define FIFOC_PSC5_TX_ADDR	0x0
-#define FIFOC_PSC5_RX_SIZE	0x0
-#define FIFOC_PSC5_RX_ADDR	0x0
-
-#define FIFOC_PSC6_TX_SIZE	0x0
-#define FIFOC_PSC6_TX_ADDR	0x0
-#define FIFOC_PSC6_RX_SIZE	0x0
-#define FIFOC_PSC6_RX_ADDR	0x0
-
-#define FIFOC_PSC7_TX_SIZE	0x0
-#define FIFOC_PSC7_TX_ADDR	0x0
-#define FIFOC_PSC7_RX_SIZE	0x0
-#define FIFOC_PSC7_RX_ADDR	0x0
-
-#define FIFOC_PSC8_TX_SIZE	0x0
-#define FIFOC_PSC8_TX_ADDR	0x0
-#define FIFOC_PSC8_RX_SIZE	0x0
-#define FIFOC_PSC8_RX_ADDR	0x0
-
-#define FIFOC_PSC9_TX_SIZE	0x0
-#define FIFOC_PSC9_TX_ADDR	0x0
-#define FIFOC_PSC9_RX_SIZE	0x0
-#define FIFOC_PSC9_RX_ADDR	0x0
-
-#define FIFOC_PSC10_TX_SIZE	0x0
-#define FIFOC_PSC10_TX_ADDR	0x0
-#define FIFOC_PSC10_RX_SIZE	0x0
-#define FIFOC_PSC10_RX_ADDR	0x0
-
-#define FIFOC_PSC11_TX_SIZE	0x0
-#define FIFOC_PSC11_TX_ADDR	0x0
-#define FIFOC_PSC11_RX_SIZE	0x0
-#define FIFOC_PSC11_RX_ADDR	0x0
+#define FIFOC_PSC3_RX_ADDR	0x70
+
+#define FIFOC_PSC4_TX_SIZE	0x04
+#define FIFOC_PSC4_TX_ADDR	0x80
+#define FIFOC_PSC4_RX_SIZE	0x04
+#define FIFOC_PSC4_RX_ADDR	0x90
+
+#define FIFOC_PSC5_TX_SIZE	0x04
+#define FIFOC_PSC5_TX_ADDR	0xa0
+#define FIFOC_PSC5_RX_SIZE	0x04
+#define FIFOC_PSC5_RX_ADDR	0xb0
+
+#define FIFOC_PSC6_TX_SIZE	0x04
+#define FIFOC_PSC6_TX_ADDR	0xc0
+#define FIFOC_PSC6_RX_SIZE	0x04
+#define FIFOC_PSC6_RX_ADDR	0xd0
+
+#define FIFOC_PSC7_TX_SIZE	0x04
+#define FIFOC_PSC7_TX_ADDR	0xe0
+#define FIFOC_PSC7_RX_SIZE	0x04
+#define FIFOC_PSC7_RX_ADDR	0xf0
+
+#define FIFOC_PSC8_TX_SIZE	0x04
+#define FIFOC_PSC8_TX_ADDR	0x100
+#define FIFOC_PSC8_RX_SIZE	0x04
+#define FIFOC_PSC8_RX_ADDR	0x110
+
+#define FIFOC_PSC9_TX_SIZE	0x04
+#define FIFOC_PSC9_TX_ADDR	0x120
+#define FIFOC_PSC9_RX_SIZE	0x04
+#define FIFOC_PSC9_RX_ADDR	0x130
+
+#define FIFOC_PSC10_TX_SIZE	0x04
+#define FIFOC_PSC10_TX_ADDR	0x140
+#define FIFOC_PSC10_RX_SIZE	0x04
+#define FIFOC_PSC10_RX_ADDR	0x150
+
+#define FIFOC_PSC11_TX_SIZE	0x04
+#define FIFOC_PSC11_TX_ADDR	0x160
+#define FIFOC_PSC11_RX_SIZE	0x04
+#define FIFOC_PSC11_RX_ADDR	0x170
 
 /*
  * SATA