MLK-12737 mx6qp/mx6dp: Fix runtime CPU type checking issue

2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When
doing runtime cpu type checking, we can't use CPU type of i.MX6Q and
i.MX6D for them more, which is ok in 2015 u-boot.

This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to
do the checking.

Signed-off-by: Ye Li <ye.li@nxp.com>

5 files changed, 31 insertions, 8 deletions

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index e457feb..ad3fe04 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1222,7 +1222,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
+		is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
@@ -1241,7 +1242,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
+		is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) {
 		if (clock > 528)
 			clock = 528; /* 528 MHz */
 	}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 086904e..1eae50b 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -142,14 +142,16 @@ u32 get_cpu_speed_grade_hz(void)
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
+			is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 			return 1200000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_1GHZ:
 		return 996000000;
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_850MHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D) ||
+			is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 			return 852000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_800MHZ:
@@ -207,6 +209,9 @@ u32 __weak get_board_rev(void)
 	if (type == MXC_CPU_MX6D)
 		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
 
+	if (type == MXC_CPU_MX6QP || type == MXC_CPU_MX6DP)
+		cpurev = (MXC_CPU_MX6Q) << 12 | ((cpurev + 0x10) & 0xFFF);
+
 	return cpurev;
 }
 #endif
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index bec3c59..1ff4bd9 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,6 +17,9 @@
 
 #define hab_rvt_report_event_p					\
 (								\
+	(is_cpu_type(MXC_CPU_MX6QP) ||				\
+	  is_cpu_type(MXC_CPU_MX6DP)) ?				\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	((is_cpu_type(MXC_CPU_MX6Q) ||				\
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
@@ -30,6 +33,9 @@
 
 #define hab_rvt_report_status_p					\
 (								\
+	(is_cpu_type(MXC_CPU_MX6QP) ||				\
+	  is_cpu_type(MXC_CPU_MX6DP)) ?				\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	((is_cpu_type(MXC_CPU_MX6Q) ||				\
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
@@ -43,6 +49,9 @@
 
 #define hab_rvt_authenticate_image_p				\
 (								\
+	(is_cpu_type(MXC_CPU_MX6QP) ||				\
+	  is_cpu_type(MXC_CPU_MX6DP)) ?				\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	((is_cpu_type(MXC_CPU_MX6Q) ||				\
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
@@ -56,6 +65,9 @@
 
 #define hab_rvt_entry_p						\
 (								\
+	(is_cpu_type(MXC_CPU_MX6QP) ||				\
+	  is_cpu_type(MXC_CPU_MX6DP)) ?				\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	((is_cpu_type(MXC_CPU_MX6Q) ||				\
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
@@ -69,6 +81,9 @@
 
 #define hab_rvt_exit_p						\
 (								\
+	(is_cpu_type(MXC_CPU_MX6QP) ||				\
+	  is_cpu_type(MXC_CPU_MX6DP)) ?			\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	((is_cpu_type(MXC_CPU_MX6Q) ||				\
 	  is_cpu_type(MXC_CPU_MX6D)) &&				\
 	  (soc_rev() >= CHIP_REV_1_5)) ?			\
@@ -437,8 +452,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 * do cache flushes. don't think any
 					 * exist, so we ignore them.
 					 */
-					if (!is_mx6dqp())
-						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+					writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
 				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
 					   is_cpu_type(MXC_CPU_MX6SOLO)) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a46..76aad0e 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,8 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D) &&
+		!is_cpu_type(MXC_CPU_MX6QP) && !is_cpu_type(MXC_CPU_MX6DP))
 		return 1;
 
 	ret = enable_sata_clock();
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index e9fad86..f52c6b5 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,7 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
-	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
+	if (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP) ||
+	    ((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
 	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
 	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
 	     is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL))