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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-08-11 19:57:09 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-18 13:45:55 -0400 |
| commit | 327f0d23c8a3c5cdc6076cf8fb1b0deb86221260 (patch) | |
| tree | 0e35d2c00f73b19ff69c9c01afa5d34fd1fa0997 /arch | |
| parent | 980db8ca43066dc094517df01fe560ccac87ecfb (diff) | |
| download | u-boot-imx-327f0d23c8a3c5cdc6076cf8fb1b0deb86221260.zip u-boot-imx-327f0d23c8a3c5cdc6076cf8fb1b0deb86221260.tar.gz u-boot-imx-327f0d23c8a3c5cdc6076cf8fb1b0deb86221260.tar.bz2 | |
lpc32xx: move common SLC NAND defines to arch/config.h
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h
The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/config.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d57bc48..d161ad2 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -55,6 +55,35 @@ /* Ethernet */ #define LPC32XX_ETH_BASE ETHERNET_BASE +/* NAND */ +#if defined(CONFIG_NAND_LPC32XX_SLC) +#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 +#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 + +#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE +#endif + +#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 16 +#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#else +#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" +#endif + +#define CONFIG_SYS_NAND_ECCSIZE 0x100 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#endif /* CONFIG_NAND_LPC32XX_SLC */ + /* NOR Flash */ #if defined(CONFIG_SYS_FLASH_CFI) #define CONFIG_FLASH_CFI_DRIVER |