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authorSimon Glass <sjg@chromium.org>2016-01-17 16:11:51 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-01-24 12:09:41 +0800
commitfad12961b06587a6f729728b0d5b5b41f62863b3 (patch)
treecc77356b5539abb89cd7ab01ed8f164c2972488f /arch
parentc02a4242c88fa42d2a08e979551a85b45c946b8e (diff)
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x86: ivybridge: Convert report_platform to DM PCI API
Convert these functions to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/cpu/ivybridge/report_platform.c11
-rw-r--r--arch/x86/cpu/ivybridge/sdram.c2
-rw-r--r--arch/x86/include/asm/arch-ivybridge/sandybridge.h2
3 files changed, 8 insertions, 7 deletions
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
index 4493870..c78322a 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -10,6 +10,7 @@
#include <asm/cpu.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
static void report_cpu_info(void)
{
@@ -63,27 +64,27 @@ static struct {
{0x1E5F, "NM70"},
};
-static void report_pch_info(void)
+static void report_pch_info(struct udevice *dev)
{
const char *pch_type = "Unknown";
int i;
u16 dev_id;
uint8_t rev_id;
- dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
+ dm_pci_read_config16(dev, 2, &dev_id);
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
pch_type = pch_table[i].dev_name;
break;
}
}
- rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
+ dm_pci_read_config8(dev, 8, &rev_id);
debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
rev_id);
}
-void report_platform_info(void)
+void report_platform_info(struct udevice *dev)
{
report_cpu_info();
- report_pch_info();
+ report_pch_info(dev);
}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 696351b..3e5be4e 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -294,7 +294,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
uint16_t done;
int ret;
- report_platform_info();
+ report_platform_info(dev);
/* Wait for ME to be ready */
ret = intel_early_me_init(me_dev);
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index af8a9f7..ce8d030 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -110,7 +110,7 @@
int bridge_silicon_revision(void);
-void report_platform_info(void);
+void report_platform_info(struct udevice *dev);
void sandybridge_early_init(int chipset_type);