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authorTom Rini <trini@konsulko.com>2016-08-26 13:30:43 -0400
committerTom Rini <trini@konsulko.com>2016-09-06 13:41:42 -0400
commitfa2f81b06f666710c756d25297d7a9ca48c65935 (patch)
tree7d01e45e83cea5408181e9b8d868b17a7485b05b /arch
parent31c98cbb31dc8c7ccb0e9c07ff340c22f5e407ba (diff)
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TI: Rework SRAM definitions and maximums
On all TI platforms the ROM defines a "downloaded image" area at or near the start of SRAM which is followed by a reserved area. As it is at best bad form and at worst possibly harmful in corner cases to write in this reserved area, we stop doing that by adding in the define NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this. At current we define the end of scratch space at 0x228 bytes past the start of scratch space this this gives us a lot of room to grow. As these scratch uses are non-optional today, all targets are modified to respect this boundary. Tested on OMAP4 Pandaboard, OMAP3 Beagle xM Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Weber <weber@corscience.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: "B, Ravi" <ravibabu@ti.com> Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: "Kipisz, Steven" <s-kipisz2@ti.com> Cc: Daniel Allred <d-allred@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap.h13
-rw-r--r--arch/arm/include/asm/arch-omap3/omap.h5
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h5
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h6
4 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 47962da..3293caa 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -15,24 +15,23 @@
#ifndef _OMAP_H_
#define _OMAP_H_
+#include <linux/sizes.h>
+
#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
-#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800
+#define NON_SECURE_SRAM_IMG_END 0x4030B800
#elif defined(CONFIG_TI81XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
-#define SRAM_SCRATCH_SPACE_ADDR 0x4031B800
+#define NON_SECURE_SRAM_IMG_END 0x4031B800
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40340000
-#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
-#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
-#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
-#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD
-#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14
+#define NON_SECURE_SRAM_IMG_END 0x40337DE0
#define QSPI_BASE 0x47900000
#endif
+#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* Boot parameters */
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
index bc0e02a..417ff89 100644
--- a/arch/arm/include/asm/arch-omap3/omap.h
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -10,6 +10,8 @@
#ifndef _OMAP3_H_
#define _OMAP3_H_
+#include <linux/sizes.h>
+
/* Stuff on L3 Interconnect */
#define SMX_APE_BASE 0x68000000
@@ -145,7 +147,8 @@ struct gpio {
#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
#define NON_SECURE_SRAM_END 0x40210000
-#define SRAM_SCRATCH_SPACE_ADDR 0x4020E000
+#define NON_SECURE_SRAM_IMG_END 0x4020F000
+#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 5ccda6e..b86a776 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -19,6 +19,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+#include <linux/sizes.h>
+
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
@@ -109,7 +111,8 @@ struct s32ktimer {
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
-#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
+#define NON_SECURE_SRAM_IMG_END 0x4030C000
+#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 2fd5cda..ef8e975 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -16,6 +16,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+#include <linux/sizes.h>
+
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
@@ -186,11 +188,13 @@ struct s32ktimer {
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END 0x4037E000
#else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END 0x4031E000
#endif
-#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
+#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000