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author | Tom Rini <trini@konsulko.com> | 2016-06-18 23:46:21 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-06-18 23:46:21 -0400 |
commit | a10a31ec91ad2ee514a42baea9314553aa972676 (patch) | |
tree | 4fa6eff1efde896343c455854b5c78b2b91bd9e9 /arch | |
parent | 2372b0012925f9100980151f4a28347c82feaba8 (diff) | |
parent | 1e6fb0e367564d427d7c57fa7b3b972ecb7147a3 (diff) | |
download | u-boot-imx-a10a31ec91ad2ee514a42baea9314553aa972676.zip u-boot-imx-a10a31ec91ad2ee514a42baea9314553aa972676.tar.gz u-boot-imx-a10a31ec91ad2ee514a42baea9314553aa972676.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-usb
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 |
5 files changed, 15 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 297687d..8062106 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -528,6 +528,13 @@ u32 fsl_qoriq_core_to_type(unsigned int core) return -1; /* cannot identify the cluster */ } +uint get_svr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + return gur_in32(&gur->svr); +} + #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index dd633f3..d8ec426 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -124,15 +124,6 @@ void erratum_a009635(void) } #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ -static void erratum_a008751(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A008751 - u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; - - writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); -#endif -} - static void erratum_rcw_src(void) { #if defined(CONFIG_SPL) @@ -189,7 +180,6 @@ void bypass_smmu(void) } void fsl_lsch3_early_init_f(void) { - erratum_a008751(); erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index e98e055..8b8a7c1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -596,4 +596,6 @@ struct ccsr_cci400 { #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 +uint get_svr(void); + #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 8d12d6c..3ad46eb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -142,6 +142,7 @@ /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 +#define SCFG_USB3PRM1CR_INIT 0x27672b2a #define SCFG_QSPICLKCTLR 0x10 #define TP_ITYP_AV 0x00000001 /* Initiator available */ @@ -323,4 +324,7 @@ struct ccsr_reset { u32 ip_rev1; /* 0xbf8 */ u32 ip_rev2; /* 0xbfc */ }; + +uint get_svr(void); + #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 02ecc62..2cb6c54 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -53,6 +53,8 @@ struct cpu_type { #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe |