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| author | Jagan Teki <jagan@amarulasolutions.com> | 2016-12-13 17:57:01 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-12-16 18:39:05 +0100 |
| commit | 5fdea9ff00e316659db0056bf43b1faec6aa1d09 (patch) | |
| tree | ab7eb322dd082fea4b13dd190d921a8bb2cc08d8 /arch | |
| parent | 5bdf6b574a06fca4a3d7b797ee577d1d18fd3c51 (diff) | |
| download | u-boot-imx-5fdea9ff00e316659db0056bf43b1faec6aa1d09.zip u-boot-imx-5fdea9ff00e316659db0056bf43b1faec6aa1d09.tar.gz u-boot-imx-5fdea9ff00e316659db0056bf43b1faec6aa1d09.tar.bz2 | |
arm: dts: imx6qdl-icore-rqs: Add I2C node's
Add I2C nodes for Engicam i.CoreM6 RQS modules.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx6qdl-icore-rqs.dtsi | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi index 343ab35..2aaa6e4 100644 --- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -48,6 +48,26 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -63,6 +83,27 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |