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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-10-11 21:37:37 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-10-21 07:46:26 -0600 |
| commit | 2fe66dbcbc1793dc199d90c4d66acaad981f9820 (patch) | |
| tree | af1173d2071b1e13dc76f06b957a6a3529378c02 /arch | |
| parent | f6220f1a86109f88950fd42e3af54314de24365a (diff) | |
| download | u-boot-imx-2fe66dbcbc1793dc199d90c4d66acaad981f9820.zip u-boot-imx-2fe66dbcbc1793dc199d90c4d66acaad981f9820.tar.gz u-boot-imx-2fe66dbcbc1793dc199d90c4d66acaad981f9820.tar.bz2 | |
x86: Do sanity test on the cache record in mrccache_update()
For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/include/asm/mrccache.h | 2 | ||||
| -rw-r--r-- | arch/x86/lib/mrccache.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 1d50ebb..ff41b8a 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -43,7 +43,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); * @entry: Position and size of MRC cache in SPI flash * @cur: Record to write * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, other error if SPI write failed + * record, -EINVAL if the record is not valid, other error if SPI write failed */ int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index ec0d2cb..6dd3b5e 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -112,6 +112,9 @@ int mrccache_update(struct udevice *sf, struct fmap_entry *entry, ulong base_addr; int ret; + if (!is_mrc_cache(cur)) + return -EINVAL; + /* Find the last used block */ base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset; debug("Updating MRC cache data\n"); |