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| author | Chen-Yu Tsai <wens@csie.org> | 2016-06-07 10:54:28 +0800 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-06-20 22:44:00 +0200 |
| commit | 0f3b8944269034bab18760053346ae1cdcf82d51 (patch) | |
| tree | a3381ba327a0ce0382f553f8ea5658162886e6ce /arch | |
| parent | b56e06d343ba4f9af3063d023032fdc00ba17944 (diff) | |
| download | u-boot-imx-0f3b8944269034bab18760053346ae1cdcf82d51.zip u-boot-imx-0f3b8944269034bab18760053346ae1cdcf82d51.tar.gz u-boot-imx-0f3b8944269034bab18760053346ae1cdcf82d51.tar.bz2 | |
sunxi: Make CPUCFG_BASE macro names the same across families
Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 16 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 |
3 files changed, 25 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index 90b5bfd..9752550 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -73,8 +73,8 @@ psci_fiq_enter: lsr r9, r9, #10 and r9, r9, #0xf - movw r8, #(SUN6I_CPUCFG_BASE & 0xffff) - movt r8, #(SUN6I_CPUCFG_BASE >> 16) + movw r8, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r8, #(SUNXI_CPUCFG_BASE >> 16) @ Wait for the core to enter WFI lsl r11, r9, #6 @ x64 @@ -114,8 +114,8 @@ psci_fiq_enter: str r10, [r12, #0x140] #endif - movw r8, #(SUN6I_CPUCFG_BASE & 0xffff) - movt r8, #(SUN6I_CPUCFG_BASE >> 16) + movw r8, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r8, #(SUNXI_CPUCFG_BASE >> 16) @ Unlock CPU ldr r10, [r8, #0x1e4] @@ -139,8 +139,8 @@ psci_cpu_on: str r2, [r0] @ store target PC at stack top dsb - movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) - movt r0, #(SUN6I_CPUCFG_BASE >> 16) + movw r0, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r0, #(SUNXI_CPUCFG_BASE >> 16) @ CPU mask and r1, r1, #3 @ only care about first cluster @@ -189,8 +189,8 @@ psci_cpu_on: str r6, [r0, #0x100] @ re-calculate CPU control register address - movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) - movt r0, #(SUN6I_CPUCFG_BASE >> 16) + movw r0, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r0, #(SUNXI_CPUCFG_BASE >> 16) @ Deassert reset on target CPU mov r6, #3 diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index e15d587..ac8ebf8 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -73,8 +73,8 @@ psci_fiq_enter: lsr r9, r9, #10 and r9, r9, #0xf - movw r8, #(SUN7I_CPUCFG_BASE & 0xffff) - movt r8, #(SUN7I_CPUCFG_BASE >> 16) + movw r8, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r8, #(SUNXI_CPUCFG_BASE >> 16) @ Wait for the core to enter WFI lsl r11, r9, #6 @ x64 @@ -128,8 +128,8 @@ psci_cpu_on: str r2, [r0] @ store target PC at stack top dsb - movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) - movt r0, #(SUN7I_CPUCFG_BASE >> 16) + movw r0, #(SUNXI_CPUCFG_BASE & 0xffff) + movt r0, #(SUNXI_CPUCFG_BASE >> 16) @ CPU mask and r1, r1, #3 @ only care about first cluster diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 65c0441..47e327e 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,10 @@ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ +#ifdef CONFIG_MACH_SUN8I_A83T +#define SUNXI_CPUCFG_BASE 0x01700000 +#endif + #define SUNXI_SRAMC_BASE 0x01c00000 #define SUNXI_DRAMC_BASE 0x01c01000 #define SUNXI_DMA_BASE 0x01c02000 @@ -94,7 +98,10 @@ #define SUNXI_TP_BASE 0x01c25000 #define SUNXI_PMU_BASE 0x01c25400 -#define SUN7I_CPUCFG_BASE 0x01c25c00 + +#ifdef CONFIG_MACH_SUN7I +#define SUNXI_CPUCFG_BASE 0x01c25c00 +#endif #define SUNXI_UART0_BASE 0x01c28000 #define SUNXI_UART1_BASE 0x01c28400 @@ -148,7 +155,11 @@ #define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 -#define SUN6I_CPUCFG_BASE 0x01f01c00 + +#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T +#define SUNXI_CPUCFG_BASE 0x01f01c00 +#endif + #define SUNXI_R_TWI_BASE 0x01f02400 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 |