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| author | Michal Simek <michal.simek@xilinx.com> | 2013-05-08 15:37:28 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-08-12 08:59:55 +0200 |
| commit | 39523bef29f71967247ca00fe4b2c7e0831bb8a2 (patch) | |
| tree | 13eb99a9c67cb1a21cadfb5089249310be548abd /arch | |
| parent | 148ba55cc618eaca19d7c86bdc003a7a71ee3a92 (diff) | |
| download | u-boot-imx-39523bef29f71967247ca00fe4b2c7e0831bb8a2.zip u-boot-imx-39523bef29f71967247ca00fe4b2c7e0831bb8a2.tar.gz u-boot-imx-39523bef29f71967247ca00fe4b2c7e0831bb8a2.tar.bz2 | |
zynq: slcr: Wait 100ms till clk is properly setup
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index e5fe992..717ec65 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -70,7 +70,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) /* Configure GEM_RCLK_CTRL */ writel(rclk, &slcr_base->gem0_rclk_ctrl); } - + udelay(100000); out: zynq_slcr_lock(); } |