Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  drivers/rtc: add Marvell Integrated RTC
  Armada100: Add Board Support for Marvell GuruPlug-Display
  Armada100: MFP macro naming correction
  arm: auto gen asm-offsets.h for mb86r0x
  spear: fix build errors for spear3xx/spear600 platforms
  cosmetic: arm: lib/board.c: Coding Style cleanup
  ARM: versatile: fix board support
  SMDKV310: Enable device tree support
  SMDKV310: MMC_SPL: Fix building when using "make O="
  arm: a320: enable tagged list support
  arm: a320: fix multiline comment style
  ARMv7: u8500_href: Add missing header to fix compiler warning
  Removed unused define, CONFIG_ARMV7.
  avr32: add grasshopper (ICnova AP7000) board
  AT91/SPI: fix atmel_dataflash_spi.c to allow building without warnings
  MAKEALL: remove AT91 boards that are in boards.cfg
  AT91: Makes AT91SAM9263-EK build correctly against u-boot-atmel/master
  AT91: Makes AT91SAM9263 SoC build correctly against u-boot-atmel/master
  AT91: Board fix for AT91SAM9261-EK
  AT91: SoC fix at91sam9261_matrix.h
  AT91: Makes AT91SAM9RL-EK build correctly against u-boot-atmel/master
  AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
  AT91: change common at91sam9261 files to compile with new scheme
  AT91: fix mistake in at91sam9260_devices.c(spi1_hw_init)
  a/a/c/arm920t/at91/reset.c: drop obsolete CONFIG_AT91RM9200_USART
  README: fix arm920t/at91 path
  net/eth.c: drop obsolete at91rm9200 support
  README.at91-soc: remove AT91(RM9200) joining notice
  a/a/c/arm920t/cpu.c: remove CONFIG_AT91_LEGACY warning
  MAKEALL: remove obsolete at91rm9200 soc
  ARM: remove obsolete at91rm9200
  omap4: clock init support for omap4460
  omap4: support TPS programming
  omap: reuse omap3 gpio support in omap4
  omap4: sdram init changes for omap4460
  omap4: add omap4460 revision detection
  mkimage: Add OMAP boot image support
  omap: add MMC and FAT support to SPL
  omap: add basic SPL support
  armv7: start.S: fixes and enhancements for SPL
  omap4: automatic sdram detection
  omap4: calculate EMIF register values
  omap4: add sdram init support
  omap4: add clock support
  omap4: add OMAP4430 revision check
  omap4: cleanup pin mux data
  omap4: utility function to identify the context of hw init
  DA8xx: fix LPSC constants
  DA8xx: switch an enum to defines for consistency
  DA8xx: add MMC/SD controller addresses
  DaVinci EMAC: declare function for all DA8xx CPUs
  DA8xx: add generic GPIO driver
  DaVinci: rename gpio_defs.h to gpio.h
  omap3evm: eth: Include functions only when necessary
  omap3evm: Update ethernet reset sequence for Rev.G board
  omap3evm: eth: split function setup_net_chip
  omap3: Include array definition only when it is used
  omap730p2: fix build breaks
  omap2420h4: fix build breaks
  omap1610inn: fix build breaks
  omap1510inn: fix build breaks
  omap5912osk: fix build breaks
  omap1610h2: fix build breaks

67 files changed, 5894 insertions, 3647 deletions

diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c
index 4fa0f98..cd9c9f3 100644
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ b/arch/arm/cpu/arm920t/at91/reset.c
@@ -43,10 +43,6 @@ void  __attribute__((weak)) board_reset(void)
 void reset_cpu(ulong ignored)
 {
 	at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
 
 	board_reset();
 
diff --git a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
deleted file mode 100644
index 8de3cba..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Broadcom BCM5221 Ethernet PHY
- *
- * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
- * Anders Larsen <alarsen@rea.de>
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-
-#include <bcm5221.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	bcm5221_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
-		((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	bcm5221_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1, stat2;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
-		return FALSE;
-
-	if (!(stat1 & BCM5221_LINK_STATUS))	/* link status up? */
-		return FALSE;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
-		return FALSE;
-
-	if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-		/*set Emac for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-		/*set MII for 100BaseTX and Half Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return TRUE;
-	}
-
-	if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-		/*set MII for 10BaseT and Half Duplex  */
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return TRUE;
-	}
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	bcm5221_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
-{
-	unsigned char ret = TRUE;
-	unsigned short IntValue;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!bcm5221_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = bcm5221_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
-	/* clear FDX LED and INTR Enable */
-	IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
-	/* set FDX, SPD, Link, INTR masks */
-	IntValue |= (BCM5221_FDX_MASK  | BCM5221_SPD_MASK |
-		     BCM5221_LINK_MASK | BCM5221_INTR_MASK);
-	at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	bcm5221_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short PhyAnar;
-	unsigned short PhyAnalpar;
-
-	/* Set bcm5221 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-	value &= ~BCM5221_AUTONEG;	/* remove autonegotiation enable */
-	value |=  BCM5221_ISOLATE;	/* Electrically isolate PHY */
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	/* Set the Auto_negotiation Advertisement Register */
-	/* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
-	PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
-		  BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
-		return FALSE;
-
-	/* Read the Control Register     */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-	/* Restart Auto_negotiation  */
-	value |= BCM5221_RESTART_AUTONEG;
-	value &= ~BCM5221_ISOLATE;
-	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
-	if (!(value & BCM5221_AUTONEG_COMP))
-		return FALSE;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
-		return FALSE;
-
-	if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
-		/*set MII for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-	return FALSE;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
deleted file mode 100644
index 6d4384f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-#include <dm9161.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	dm9161_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
-		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	dm9161_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1, stat2;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
-		return FALSE;
-
-	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
-		return FALSE;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
-		return FALSE;
-
-	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
-		/*set Emac for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
-		/*set MII for 100BaseTX and Half Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return TRUE;
-	}
-
-	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
-		/*set MII for 10BaseT and Half Duplex  */
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return TRUE;
-	}
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	dm9161_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
-{
-	UCHAR ret = TRUE;
-	unsigned short IntValue;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!dm9161_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = dm9161_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
-	/* set FDX, SPD, Link, INTR masks */
-	IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
-			DM9161_LINK_MASK | DM9161_INTR_MASK);
-	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	dm9161_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short PhyAnar;
-	unsigned short PhyAnalpar;
-
-	/* Set dm9161 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
-	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	/* Set the Auto_negotiation Advertisement Register	*/
-	/* MII advertising for Next page, 100BaseTxFD and HD,	*/
-	/* 10BaseTFD and HD, IEEE 802.3 */
-	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
-			DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
-		return FALSE;
-
-	/* Read the Control Register     */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-	/* Restart Auto_negotiation  */
-	value |= DM9161_RESTART_AUTONEG;
-	value &= ~DM9161_ISOLATE;
-	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
-	if (!(value & DM9161_AUTONEG_COMP))
-		return FALSE;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
-		return FALSE;
-
-	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
-		/*set MII for 100BaseTX and Full Duplex  */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return TRUE;
-	}
-
-	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
-		/*set MII for 10BaseT and Full Duplex  */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return TRUE;
-	}
-	return FALSE;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c
deleted file mode 100644
index d7135c5..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ether.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-
-/* ----- Ethernet Buffer definitions ----- */
-
-typedef struct {
-	unsigned long addr, size;
-} rbf_t;
-
-#define RBF_ADDR      0xfffffffc
-#define RBF_OWNER     (1<<0)
-#define RBF_WRAP      (1<<1)
-#define RBF_BROADCAST (1<<31)
-#define RBF_MULTICAST (1<<30)
-#define RBF_UNICAST   (1<<29)
-#define RBF_EXTERNAL  (1<<28)
-#define RBF_UNKNOWN   (1<<27)
-#define RBF_SIZE      0x07ff
-#define RBF_LOCAL4    (1<<26)
-#define RBF_LOCAL3    (1<<25)
-#define RBF_LOCAL2    (1<<24)
-#define RBF_LOCAL1    (1<<23)
-
-#define RBF_FRAMEMAX 64
-#define RBF_FRAMELEN 0x600
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/* alignment as per Errata #11 (64 bytes) is insufficient! */
-rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
-rbf_t *rbfp;
-
-unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
-	__attribute__((aligned(4)));
-
-/* structure to interface the PHY */
-AT91S_PhyOps PhyOps;
-
-AT91PS_EMAC p_mac;
-
-/*********** EMAC Phy layer Management functions *************************/
-/*
- * Name:
- *	at91rm9200_EmacEnableMDIO
- * Description:
- *	Enables the MDIO bit in MAC control register
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	none
- */
-void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
-{
-	/* Mac CTRL reg set for MDIO enable */
-	p_mac->EMAC_CTL |= AT91C_EMAC_MPE;	/* Management port enable */
-}
-
-/*
- * Name:
- *	at91rm9200_EmacDisableMDIO
- * Description:
- *	Disables the MDIO bit in MAC control register
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	none
- */
-void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
-{
-	/* Mac CTRL reg set for MDIO disable */
-	p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;	/* Management port disable */
-}
-
-
-/*
- * Name:
- *	at91rm9200_EmacReadPhy
- * Description:
- *	Reads data from the PHY register
- * Arguments:
- *	dev - pointer to struct net_device
- *	RegisterAddress - unsigned char
- *	pInput - pointer to value read from register
- * Return value:
- *	TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
-				     unsigned char RegisterAddress,
-				     unsigned short *pInput)
-{
-	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-			  (AT91C_EMAC_RW_R) |
-			  (RegisterAddress << 18) |
-			  (AT91C_EMAC_CODE_802_3);
-
-	udelay (10000);
-
-	*pInput = (unsigned short) p_mac->EMAC_MAN;
-
-	return TRUE;
-}
-
-
-/*
- * Name:
- *	at91rm9200_EmacWritePhy
- * Description:
- *	Writes data to the PHY register
- * Arguments:
- *	dev - pointer to struct net_device
- *	RegisterAddress - unsigned char
- *	pOutput - pointer to value to be written in the register
- * Return value:
- *	TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
-				      unsigned char RegisterAddress,
-				      unsigned short *pOutput)
-{
-	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-			AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
-			(RegisterAddress << 18) | *pOutput;
-
-	udelay (10000);
-
-	return TRUE;
-}
-
-int eth_init (bd_t * bd)
-{
-	int ret;
-	int i;
-	uchar enetaddr[6];
-
-	p_mac = AT91C_BASE_EMAC;
-
-	/* PIO Disable Register */
-	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
-			  AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
-			  AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
-			  AT91C_PA7_ETXCK_EREFCK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
-	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
-#else
-	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
-			  AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
-			  AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-
-	/* Select B Register */
-	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
-			  AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
-			  AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-#endif
-
-	*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;	/* Peripheral Clock Enable Register */
-
-	p_mac->EMAC_CFG |= AT91C_EMAC_CSR;	/* Clear statistics */
-
-	/* Init Ethernet buffers */
-	for (i = 0; i < RBF_FRAMEMAX; i++) {
-		rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
-		rbfdt[i].size = 0;
-	}
-	rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
-	rbfp = &rbfdt[0];
-
-	eth_getenv_enetaddr("ethaddr", enetaddr);
-
-	/* The CSB337 originally used a version of the MicroMonitor bootloader
-	 * which saved Ethernet addresses in the "wrong" order.  Operating
-	 * systems (like Linux) know this, and apply a workaround.  Replicate
-	 * that MicroMonitor behavior so we avoid needing to make such OS code
-	 * care about which bootloader was used.
-	 */
-	if (machine_is_csb337()) {
-		p_mac->EMAC_SA2H = (enetaddr[0] <<  8) | (enetaddr[1]);
-		p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
-				 | (enetaddr[4] <<  8) | (enetaddr[5]);
-	} else {
-		p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
-				 | (enetaddr[1] <<  8) | (enetaddr[0]);
-		p_mac->EMAC_SA2H = (enetaddr[5] <<  8) | (enetaddr[4]);
-	}
-
-	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
-	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
-	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
-			& ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-#if (AT91C_MASTER_CLOCK > 40000000)
-	/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
-	p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
-#endif
-
-	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
-	at91rm9200_GetPhyInterface (& PhyOps);
-
-	if (!PhyOps.IsPhyConnected (p_mac))
-		printf ("PHY not connected!!\n\r");
-
-	/* MII management start from here */
-	if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
-		if (!(ret = PhyOps.Init (p_mac))) {
-			printf ("MAC: error during MII initialization\n");
-			return 0;
-		}
-	} else {
-		printf ("No link\n\r");
-		return 0;
-	}
-
-	return 0;
-}
-
-int eth_send (volatile void *packet, int length)
-{
-	while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
-	p_mac->EMAC_TAR = (long) packet;
-	p_mac->EMAC_TCR = length;
-	while (p_mac->EMAC_TCR & 0x7ff);
-	p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
-	return 0;
-}
-
-int eth_rx (void)
-{
-	int size;
-
-	if (!(rbfp->addr & RBF_OWNER))
-		return 0;
-
-	size = rbfp->size & RBF_SIZE;
-	NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
-
-	rbfp->addr &= ~RBF_OWNER;
-	if (rbfp->addr & RBF_WRAP)
-		rbfp = &rbfdt[0];
-	else
-		rbfp++;
-
-	p_mac->EMAC_RSR |= AT91C_EMAC_REC;
-
-	return size;
-}
-
-void eth_halt (void)
-{
-};
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-int  at91rm9200_miiphy_read(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short * value)
-{
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy (p_mac, reg, value);
-	at91rm9200_EmacDisableMDIO (p_mac);
-	return 0;
-}
-
-int  at91rm9200_miiphy_write(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value)
-{
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacWritePhy (p_mac, reg, &value);
-	at91rm9200_EmacDisableMDIO (p_mac);
-	return 0;
-}
-
-#endif
-
-int at91rm9200_miiphy_initialize(bd_t *bis)
-{
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
-#endif
-	return 0;
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
deleted file mode 100644
index 1711088..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/i2c.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *  i2c Support for Atmel's AT91RM9200 Two-Wire Interface
- *
- *  (c) Rick Bronson
- *
- *  Borrowed heavily from original work by:
- *  Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
- *
- *  Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
-*/
-#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#include <at91rm9200_i2c.h>
-
-/* define DEBUG */
-
-/*
- * Poll the i2c status register until the specified bit is set.
- * Returns 0 if timed out (100 msec)
- */
-static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
-	int loop_cntr = 10000;
-	do {
-		udelay(10);
-	} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
-
-	return (loop_cntr > 0);
-}
-
-/*
- * Generic i2c master transfer entrypoint
- *
- * rw == 1 means that this is a read
- */
-static int
-at91_xfer(unsigned char chip, unsigned int addr, int alen,
-						unsigned char *buffer, int len, int rw)
-{
-	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-	int length;
-	unsigned char *buf;
-	/* Set the TWI Master Mode Register */
-	twi->TWI_MMR = (chip << 16) | (alen << 8)
-		| ((rw == 1) ? AT91C_TWI_MREAD : 0);
-
-	/* Set TWI Internal Address Register with first messages data field */
-	if (alen > 0)
-		twi->TWI_IADR = addr;
-
-	length = len;
-	buf = buffer;
-	if (length && buf) {	/* sanity check */
-		if (rw) {
-			twi->TWI_CR = AT91C_TWI_START;
-			while (length--) {
-				if (!length)
-					twi->TWI_CR = AT91C_TWI_STOP;
-				/* Wait until transfer is finished */
-				if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
-					debug ("at91_i2c: timeout 1\n");
-					return 1;
-				}
-				*buf++ = twi->TWI_RHR;
-			}
-			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-				debug ("at91_i2c: timeout 2\n");
-				return 1;
-			}
-		} else {
-			twi->TWI_CR = AT91C_TWI_START;
-			while (length--) {
-				twi->TWI_THR = *buf++;
-				if (!length)
-					twi->TWI_CR = AT91C_TWI_STOP;
-				if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
-					debug ("at91_i2c: timeout 3\n");
-					return 1;
-				}
-			}
-			/* Wait until transfer is finished */
-			if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-				debug ("at91_i2c: timeout 4\n");
-				return 1;
-			}
-		}
-	}
-	return 0;
-}
-
-int
-i2c_probe(unsigned char chip)
-{
-	unsigned char buffer[1];
-
-	return at91_xfer(chip, 0, 0, buffer, 1, 1);
-}
-
-int
-i2c_read (unsigned char chip, unsigned int addr, int alen,
-	  unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-	/* we only allow one address byte */
-	if (alen > 1)
-		return 1;
-	/* XXX assume an ATMEL AT24C16 */
-	if (alen == 1) {
-#if 0 /* EEPROM code already sets this correctly */
-		chip |= (addr >> 8) & 0xff;
-#endif
-		addr = addr & 0xff;
-	}
-#endif
-	return at91_xfer(chip, addr, alen, buffer, len, 1);
-}
-
-int
-i2c_write(unsigned char chip, unsigned int addr, int alen,
-	  unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-	int i;
-	unsigned char *buf;
-
-	/* we only allow one address byte */
-	if (alen > 1)
-		return 1;
-	/* XXX assume an ATMEL AT24C16 */
-	if (alen == 1) {
-		buf = buffer;
-		/* do single byte writes */
-		for (i = 0; i < len; i++) {
-#if 0 /* EEPROM code already sets this correctly */
-			chip |= (addr >> 8) & 0xff;
-#endif
-			addr = addr & 0xff;
-			if (at91_xfer(chip, addr, alen, buf++, 1, 0))
-				return 1;
-			addr++;
-		}
-		return 0;
-	}
-#endif
-	return at91_xfer(chip, addr, alen, buffer, len, 0);
-}
-
-/*
- * Main initialization routine
- */
-void
-i2c_init(int speed, int slaveaddr)
-{
-	AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-
-	*AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-	*AT91C_PMC_PCER = 1 << AT91C_ID_TWI;		/* enable peripheral clock */
-
-	twi->TWI_IDR = 0x3ff;				/* Disable all interrupts */
-	twi->TWI_CR = AT91C_TWI_SWRST;			/* Reset peripheral */
-	twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;	/* Set Master mode */
-
-	/* Here, CKDIV = 1 and CHDIV=CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
-	twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
-
-	debug ("Found AT91 i2c\n");
-	return;
-}
-
-#endif /* CONFIG_HARD_I2C */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
deleted file mode 100644
index 9fe3793..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006
- * Author : Eric Benard (Eukrea Electromatique)
- * based on dm9161.c which is :
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <ks8721.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	ks8721_isphyconnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	1 - if id read successfully
- *	0 - if error
- */
-unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac)
-{
-	unsigned short id1, id2;
-
-	at91rm9200_EmacEnableMDIO(p_mac);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2);
-	at91rm9200_EmacDisableMDIO(p_mac);
-
-	if ((id1 == (KS8721_PHYID_OUI >> 6)) &&
-		((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) {
-		if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL)
-			printf("Micrel KS8721bL PHY detected : ");
-		else
-			printf("Unknown Micrel PHY detected : ");
-		return 1;
-	}
-	return 0;
-}
-
-/*
- * Name:
- *	ks8721_getlinkspeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	1 - if link status set succesfully
- *	0 - if link status not set
- */
-unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac)
-{
-	unsigned short stat1;
-
-	if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1))
-		return 0;
-
-	if (!(stat1 & KS8721_LINK_STATUS)) {
-		/* link status up? */
-		printf("Link Down !\n");
-		return 0;
-	}
-
-	if (stat1 & KS8721_100BASE_TX_FD) {
-		/* set Emac for 100BaseTX and Full Duplex */
-		printf("100BT FD\n");
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_10BASE_T_FD) {
-		/* set MII for 10BaseT and Full Duplex */
-		printf("10BT FD\n");
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_100BASE_T4_HD) {
-		/* set MII for 100BaseTX and Half Duplex */
-		printf("100BT HD\n");
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_SPD;
-		return 1;
-	}
-
-	if (stat1 & KS8721_10BASE_T_HD) {
-		/* set MII for 10BaseT and Half Duplex */
-		printf("10BT HD\n");
-		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		return 1;
-	}
-	return 0;
-}
-
-/*
- * Name:
- *	ks8721_initphy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	1 - if link status set succesfully
- *	0 - if link status not set
- */
-unsigned char ks8721_initphy(AT91PS_EMAC p_mac)
-{
-	unsigned char ret = 1;
-	unsigned short intvalue;
-
-	at91rm9200_EmacEnableMDIO(p_mac);
-
-	/* Try another time */
-	if (!ks8721_getlinkspeed(p_mac))
-		ret = ks8721_getlinkspeed(p_mac);
-
-	/* Disable PHY Interrupts */
-	intvalue = 0;
-	at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue);
-	at91rm9200_EmacDisableMDIO(p_mac);
-
-	return ret;
-}
-
-/*
- * Name:
- *	ks8721_autonegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	1 - if link status set successfully
- *	0 - if link status not set
- */
-unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-	unsigned short phyanar;
-	unsigned short phyanalpar;
-
-	/* Set ks8721 control register */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value))
-		return 0;
-
-	/* remove autonegotiation enable */
-	value &= ~KS8721_AUTONEG;
-	/* Electrically isolate PHY */
-	value |= KS8721_ISOLATE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/*
-	 * Set the Auto_negotiation Advertisement Register
-	 * MII advertising for Next page, 100BaseTxFD and HD,
-	 * 10BaseTFD and HD, IEEE 802.3
-	 */
-	phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX |
-		  KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) {
-		return 0;
-	}
-	/* Read the Control Register */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/* Restart Auto_negotiation */
-	value |= KS8721_RESTART_AUTONEG;
-	value &= ~KS8721_ISOLATE;
-	if (!at91rm9200_EmacWritePhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-		return 0;
-	}
-	/* Check AutoNegotiate complete */
-	udelay(10000);
-	at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_BMSR, &value);
-	if (!(value & KS8721_AUTONEG_COMP))
-		return 0;
-
-	/* Get the AutoNeg Link partner base page */
-	if (!at91rm9200_EmacReadPhy(p_mac,
-		CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) {
-		return 0;
-	}
-
-	if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) {
-		/* Set MII for 100BaseTX and Full Duplex */
-		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		return 1;
-	}
-
-	if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) {
-		/* Set MII for 10BaseT and Full Duplex */
-		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-				| AT91C_EMAC_FD;
-		return 1;
-	}
-	return 0;
-}
-
-#endif	/* CONFIG_CMD_NET */
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
deleted file mode 100644
index 2e7160f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-#include <asm/arch/AT91RM9200.h>
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Get the CKGR Base Address */
-	ldr     r1, =AT91C_BASE_CKGR
-	/* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-	ldr     r0, =0x0000FF01		/* Enable main oscillator,  OSCOUNT = 0xFF */
-#else
-	ldr     r0, =0x0000FF00		/* Disable main oscillator, OSCOUNT = 0xFF */
-#endif
-	str     r0, [r1, #AT91C_CKGR_MOR]
-	/* Add loop to compensate Main Oscillator startup time */
-	ldr     r0, =0x00000010
-LoopOsc:
-	subs    r0, r0, #1
-	bhi     LoopOsc
-
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-1:
-	subs	r0, r0, #1
-	bhi	1b
-	ldr	r0, =SMRDATA1
-	ldr	r1, _MTEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* switch from FastBus to Asynchronous clock mode */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0xC0000000	@ set bit 31 (iA) and 30 (nF)
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word AT91C_EBI_CFGR
-	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word AT91C_SMC_CSR0
-	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word AT91C_PLLAR
-	.word CONFIG_SYS_PLLAR_VAL
-	.word AT91C_PLLBR
-	.word CONFIG_SYS_PLLBR_VAL
-	.word AT91C_MCKR
-	.word CONFIG_SYS_MCKR_VAL
-	/* here there's a delay */
-SMRDATA1:
-	.word AT91C_PIOC_ASR
-	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word AT91C_PIOC_BSR
-	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word AT91C_PIOC_PDR
-	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word AT91C_EBI_CSA
-	.word CONFIG_SYS_EBI_CSA_VAL
-	.word AT91C_SDRC_CR
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word CONFIG_SYS_SDRAM1
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_TR
-	.word CONFIG_SYS_SDRC_TR_VAL
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	.word AT91C_SDRC_MR
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word CONFIG_SYS_SDRAM
-	.word CONFIG_SYS_SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
deleted file mode 100644
index f02cfdd..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Adapted for KwikByte KB920x board: 22APR2005
- */
-
-#include <common.h>
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *	lxt972_IsPhyConnected
- * Description:
- *	Reads the 2 PHY ID registers
- * Arguments:
- *	p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *	TRUE - if id read successfully
- *	FALSE- if error
- */
-unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-	unsigned short Id1, Id2;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1);
-	at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2);
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	if ((Id1 == (0x0013)) && ((Id2  & 0xFFF0) == 0x78E0))
-		return TRUE;
-
-	return FALSE;
-}
-
-/*
- * Name:
- *	lxt972_GetLinkSpeed
- * Description:
- *	Link parallel detection status of MAC is checked and set in the
- *	MAC configuration registers
- * Arguments:
- *	p_mac - pointer to MAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-	unsigned short stat1;
-
-	if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1))
-		return FALSE;
-
-	if (!(stat1 & PHY_LXT971_STAT2_LINK))	/* link status up? */
-		return FALSE;
-
-	if (stat1 & PHY_LXT971_STAT2_100BTX) {
-
-		if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-			/*set Emac for 100BaseTX and Full Duplex  */
-			p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		} else {
-
-			/*set Emac for 100BaseTX and Half Duplex  */
-			p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-					~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-					| AT91C_EMAC_SPD;
-		}
-
-		return TRUE;
-
-	} else {
-
-		if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-			/*set MII for 10BaseT and Full Duplex  */
-			p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-					~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-					| AT91C_EMAC_FD;
-		} else {
-
-			/*set MII for 10BaseT and Half Duplex  */
-			p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-		}
-
-		return TRUE;
-	}
-
-	return FALSE;
-}
-
-
-/*
- * Name:
- *	lxt972_InitPhy
- * Description:
- *	MAC starts checking its link by using parallel detection and
- *	Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *	p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *	TRUE - if link status set succesfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
-{
-	UCHAR ret = TRUE;
-
-	at91rm9200_EmacEnableMDIO (p_mac);
-
-	if (!lxt972_GetLinkSpeed (p_mac)) {
-		/* Try another time */
-		ret = lxt972_GetLinkSpeed (p_mac);
-	}
-
-	/* Disable PHY Interrupts */
-	at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
-
-	at91rm9200_EmacDisableMDIO (p_mac);
-
-	return (ret);
-}
-
-
-/*
- * Name:
- *	lxt972_AutoNegotiate
- * Description:
- *	MAC Autonegotiates with the partner status of same is set in the
- *	MAC configuration registers
- * Arguments:
- *	dev - pointer to struct net_device
- * Return value:
- *	TRUE - if link status set successfully
- *	FALSE - if link status not set
- */
-UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-	unsigned short value;
-
-	/* Set lxt972 control register */
-	if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value))
-		return FALSE;
-
-	/* Restart Auto_negotiation  */
-	value |= BMCR_ANRESTART;
-	if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value))
-		return FALSE;
-
-	/*check AutoNegotiate complete */
-	udelay (10000);
-	at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value);
-	if (!(value & BMSR_ANEGCOMPLETE))
-		return FALSE;
-
-	return (lxt972_GetLinkSpeed (p_mac));
-}
-
-#endif
-
-#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c
deleted file mode 100644
index 945ea2c..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/reset.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void board_reset(void) __attribute__((__weak__));
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * or toggle a GPIO pin on the AT91RM9200DK board
- */
-void reset_cpu (ulong ignored)
-{
-
-#if defined(CONFIG_AT91RM9200_USART)
-	/*shutdown the console to avoid strange chars during reset */
-	serial_exit();
-#endif
-
-	if (board_reset)
-		board_reset();
-
-	/* this is the way Linux does it */
-
-	/* FIXME:
-	 * These defines should be moved into
-	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
-	 * as soon as the whitespace fix gets applied.
-	 */
-	#define AT91C_ST_RSTEN (0x1 << 16)
-	#define AT91C_ST_EXTEN (0x1 << 17)
-	#define AT91C_ST_WDRST (0x1 <<  0)
-	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
-	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
-
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-
-	while (1);
-	/* Never reached */
-}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c
deleted file mode 100644
index c70efc6..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/spi.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
-					the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS	(0xC << 16)
-#define DATAFLASH_TCHS	(0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY		200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH	0xE	/* Chip Select 0: NPCS0%1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD	0x7	/* Chip Select 3: NPCS3%0111 */
-
-/*-------------------------------------------------------------------*/
-/*	SPI DataFlash Init					     */
-/*-------------------------------------------------------------------*/
-void AT91F_SpiInit(void)
-{
-	/* Configure PIOs */
-	AT91C_BASE_PIOA->PIO_ASR =
-		AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-		AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-		AT91C_PA2_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR =
-		AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-		AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-		AT91C_PA2_SPCK;
-	/* Enable CLock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-	/* Reset the SPI */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-	/* Configure SPI in Master Mode with No CS selected !!! */
-	AT91C_BASE_SPI->SPI_MR =
-		AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) =
-		AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-		(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-		((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-	*(AT91C_SPI_CSR + 3) =
-		AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-		(AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-		((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-}
-
-void AT91F_SpiEnable(int cs)
-{
-	switch(cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |=
-			((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) &
-				AT91C_SPI_PCS);
-		break;
-	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
-		/* Set up PIO SDC_TYPE to switch on DataFlash Card */
-		/* and not MMC/SDCard */
-		AT91C_BASE_PIOB->PIO_PER =
-			AT91C_PIO_PB7;	/* Set in PIO mode */
-		AT91C_BASE_PIOB->PIO_OER =
-			AT91C_PIO_PB7;	/* Configure in output */
-		/* Clear Output */
-		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-		/* Configure PCS */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |=
-			((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-		break;
-	}
-
-	/* SPI_Enable */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; }
-
-/*---------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite						     */
-/* \brief Set the PDC registers for a transfert				     */
-/*---------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
-	unsigned int timeout;
-	unsigned long start;
-
-	pDesc->state = BUSY;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-	/* Initialize the Transmit and Receive Pointer */
-	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-	/* Intialize the Transmit and Receive Counters */
-	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-	if ( pDesc->tx_data_size != 0 ) {
-		/* Initialize the Next Transmit and Next Receive Pointer */
-		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-		/* Intialize the Next Transmit and Next Receive Counters */
-		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-	}
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-	timeout = 0;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
-		((timeout = get_timer(start) ) < CONFIG_SYS_SPI_WRITE_TOUT));
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-	pDesc->state = IDLE;
-
-	if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
-		printf("Error Timeout\n\r");
-		return DATAFLASH_ERROR;
-	}
-
-	return DATAFLASH_OK;
-}
-#endif
diff --git a/arch/arm/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c
deleted file mode 100644
index fbe74b6..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/timer.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-/*#include <asm/io.h>*/
-#include <asm/arch/hardware.h>
-/*#include <asm/proc/ptrace.h>*/
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
-AT91PS_TC tmr;
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init (void)
-{
-	tmr = AT91C_BASE_TC0;
-
-	/* enables TC1.0 clock */
-	*AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
-
-	*AT91C_TCB0_BCR = 0;
-	*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
-	tmr->TC_CCR = AT91C_TC_CLKDIS;
-#define AT91C_TC_CMR_CPCTRG (1 << 14)
-	/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
-	tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
-
-	tmr->TC_IDR = ~0ul;
-	tmr->TC_RC = TIMER_LOAD_VAL;
-	lastinc = 0;
-	tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-ulong get_timer_raw (void)
-{
-	ulong now = READ_TIMER;
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw () + tmo;
-
-	do {
-		ulong now = get_timer_raw ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/usb.c b/arch/arm/cpu/arm920t/at91rm9200/usb.c
deleted file mode 100644
index 72355dc..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/usb.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# ifdef CONFIG_AT91RM9200
-
-#include <asm/arch/hardware.h>
-
-int usb_cpu_init(void)
-{
-	/* Enable USB host clock. */
-	*AT91C_PMC_SCER = AT91C_PMC_UHP;	/* 48MHz clock enabled for UHP */
-	*AT91C_PMC_PCER = 1 << AT91C_ID_UHP;	/* Peripheral Clock Enable Register */
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	/* Initialization failed */
-	*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP;	/* Peripheral Clock Disable Register */
-	*AT91C_PMC_SCDR = AT91C_PMC_UHP;	/* 48MHz clock disabled for UHP */
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	return usb_cpu_stop();
-}
-
-# endif /* CONFIG_AT91RM9200 */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c
index be82c87..34adb11 100644
--- a/arch/arm/cpu/arm920t/cpu.c
+++ b/arch/arm/cpu/arm920t/cpu.c
@@ -33,10 +33,6 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_AT91_LEGACY
-#warning Your board is using legacy AT91RM9200 SoC access. Please update!
-#endif
-
 static void cache_flush(void);
 
 int cleanup_before_linux (void)
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
index 6bdc75c..65b8d51 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -138,7 +138,7 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
 	}
 	if (cs_mask & (1 << 3)) {
-		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+		at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
 	}
 	if (cs_mask & (1 << 4)) {
 		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
index b4353ef..edc7972 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -23,77 +23,73 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
-	writel(1 << AT91SAM9261_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
-	writel(1 << AT91SAM9261_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
-	writel(1 << AT91SAM9261_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 }
 
-#ifdef CONFIG_HAS_DATAFLASH
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
@@ -123,14 +119,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 31, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* SPI1_SPCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 30, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 31, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 29, PUP);	/* SPI1_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
index 15e880a..6eb0f30 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -28,17 +28,31 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
 
 void at91_serial0_hw_init(void)
 {
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);		/* RXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);		/* RXD0 */
 	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
@@ -47,7 +61,7 @@ void at91_serial1_hw_init(void)
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);		/* RXD1 */
 	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
@@ -56,7 +70,7 @@ void at91_serial2_hw_init(void)
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);		/* RXD2 */
 	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
@@ -64,7 +78,7 @@ void at91_seriald_hw_init(void)
 {
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
 	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 }
@@ -74,9 +88,9 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 {
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
-	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
-	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
+	at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
@@ -111,9 +125,9 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 {
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_SPCK */
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..b0a1687 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,77 +23,73 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTA, 7, 0);		/* RXD0 */
-	writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);		/* RXD1 */
-	writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+	at91_set_a_periph(AT91_PIO_PORTA, 12, PUP);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);		/* RXD2 */
-	writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+	at91_set_a_periph(AT91_PIO_PORTA, 14, PUP);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
-void at91_serial3_hw_init(void)
+void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
-	at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
-	at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
-	at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3	/* DBGU */
-	at91_serial3_hw_init();
-#endif
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 }
 
-#ifdef CONFIG_HAS_DATAFLASH
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* SPI0_SPCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
index 17ff0dd..d102195 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -35,7 +35,7 @@
 #include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/at91sam9_matrix.h>
 #endif
 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
index bab048b..974d0be 100644
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
@@ -37,6 +37,8 @@ all:	$(obj).depend $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
new file mode 100644
index 0000000..6f9c722
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
@@ -0,0 +1,65 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/mb86r0x.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	/* ddr2 controller */
+	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+	/* clock reset generator */
+	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+	/* chip control module */
+	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+	/* external bus interface */
+	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 299792a..92a5a96 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	:= start.o
-COBJS	:= cpu.o cache_v7.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	+= cache_v7.o
+COBJS	+= cpu.o
+endif
+
 COBJS  += syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index def9ced..091e3e0 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -37,6 +37,13 @@
 #include <asm/cache.h>
 #include <asm/armv7.h>
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index dc01ee5..ea9f8ec 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -28,6 +28,12 @@ LIB	= $(obj)libomap-common.o
 SOBJS	:= reset.o
 
 COBJS	:= timer.o
+COBJS	+= utils.o
+COBJS	+= gpio.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	+= spl.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/omap3/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c
index aeb6066..f4c3479 100644
--- a/arch/arm/cpu/armv7/omap3/gpio.c
+++ b/arch/arm/cpu/armv7/omap-common/gpio.c
@@ -36,24 +36,13 @@
  * published by the Free Software Foundation.
  */
 #include <common.h>
-#include <asm/arch/gpio.h>
+#include <asm/omap_gpio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 
-static struct gpio_bank gpio_bank_34xx[6] = {
-	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
+static inline const struct gpio_bank *get_gpio_bank(int gpio)
 {
-	return &gpio_bank[gpio >> 5];
+	return &omap_gpio_bank[gpio >> 5];
 }
 
 static inline int get_gpio_index(int gpio)
@@ -79,14 +68,15 @@ static int check_gpio(int gpio)
 	return 0;
 }
 
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
+				int is_input)
 {
 	void *reg = bank->base;
 	u32 l;
 
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_OE;
+		reg += OMAP_GPIO_OE;
 		break;
 	default:
 		return;
@@ -101,7 +91,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 
 void omap_set_gpio_direction(int gpio, int is_input)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;
@@ -109,7 +99,8 @@ void omap_set_gpio_direction(int gpio, int is_input)
 	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
 }
 
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
+				int enable)
 {
 	void *reg = bank->base;
 	u32 l = 0;
@@ -117,9 +108,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
 		if (enable)
-			reg += OMAP24XX_GPIO_SETDATAOUT;
+			reg += OMAP_GPIO_SETDATAOUT;
 		else
-			reg += OMAP24XX_GPIO_CLEARDATAOUT;
+			reg += OMAP_GPIO_CLEARDATAOUT;
 		l = 1 << gpio;
 		break;
 	default:
@@ -132,7 +123,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 
 void omap_set_gpio_dataout(int gpio, int enable)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;
@@ -142,7 +133,7 @@ void omap_set_gpio_dataout(int gpio, int enable)
 
 int omap_get_gpio_datain(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 	void *reg;
 
 	if (check_gpio(gpio) < 0)
@@ -151,7 +142,7 @@ int omap_get_gpio_datain(int gpio)
 	reg = bank->base;
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_DATAIN;
+		reg += OMAP_GPIO_DATAIN;
 		break;
 	default:
 		return -EINVAL;
@@ -160,7 +151,7 @@ int omap_get_gpio_datain(int gpio)
 			& (1 << get_gpio_index(gpio))) != 0;
 }
 
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
+static void _reset_gpio(const struct gpio_bank *bank, int gpio)
 {
 	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
 }
@@ -175,7 +166,7 @@ int omap_request_gpio(int gpio)
 
 void omap_free_gpio(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
new file mode 100644
index 0000000..d177652
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -0,0 +1,272 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <mmc.h>
+#include <fat.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <image.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+static const char *image_name;
+static u8 image_os;
+static u32 image_load_addr;
+static u32 image_entry_point;
+static u32 image_size;
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	/*
+	 * We call relocate_code() with relocation target same as the
+	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+	 * skipped. Instead, only .bss initialization will happen. That's
+	 * all we need
+	 */
+	debug(">>board_init_f()\n");
+	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0);
+		break;
+	case BOOT_DEVICE_MMC2:
+		omap_mmc_init(1);
+		break;
+	}
+	return 0;
+}
+#endif
+
+static void parse_image_header(const struct image_header *header)
+{
+	u32 header_size = sizeof(struct image_header);
+
+	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
+		image_size = __be32_to_cpu(header->ih_size) + header_size;
+		image_entry_point = __be32_to_cpu(header->ih_load);
+		/* Load including the header */
+		image_load_addr = image_entry_point - header_size;
+		image_os = header->ih_os;
+		image_name = (const char *)&header->ih_name;
+		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
+			image_name, image_load_addr, image_size);
+	} else {
+		/* Signature not found - assume u-boot.bin */
+		printf("mkimage signature not found - ih_magic = %x\n",
+			header->ih_magic);
+		puts("Assuming u-boot.bin ..\n");
+		/* Let's assume U-Boot will not be more than 200 KB */
+		image_size = 200 * 1024;
+		image_entry_point = CONFIG_SYS_TEXT_BASE;
+		image_load_addr = CONFIG_SYS_TEXT_BASE;
+		image_os = IH_OS_U_BOOT;
+		image_name = "U-Boot";
+	}
+}
+
+static void mmc_load_image_raw(struct mmc *mmc)
+{
+	u32 image_size_sectors, err;
+	const struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	/* read image header to find the image size & load address */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)header);
+
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	/* convert size to sectors - round up */
+	image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) /
+				MMCSD_SECTOR_SIZE;
+
+	/* Read the header too to avoid extra memcpy */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+			image_size_sectors, (void *)image_load_addr);
+
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_image_fat(struct mmc *mmc)
+{
+	s32 err;
+	struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	parse_image_header(header);
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)image_load_addr, 0);
+
+end:
+	if (err <= 0) {
+		printf("spl: error reading image %s, err - %d\n",
+			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
+		hang();
+	}
+}
+
+static void mmc_load_image(void)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: err - %d\n", err);
+		hang();
+	}
+
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW) {
+		debug("boot mode - RAW\n");
+		mmc_load_image_raw(mmc);
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		debug("boot mode - FAT\n");
+		mmc_load_image_fat(mmc);
+	} else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
+
+void jump_to_image_no_args(void)
+{
+	typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) image_entry_point;
+
+	image_entry();
+}
+
+void jump_to_image_no_args(void) __attribute__ ((noreturn));
+void board_init_r(gd_t *id, ulong dummy)
+{
+	u32 boot_device;
+	debug(">>spl:board_init_r()\n");
+
+	timer_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	boot_device = omap_boot_device();
+	debug("boot device - %d\n", boot_device);
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		mmc_load_image();
+		break;
+	default:
+		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
+		hang();
+		break;
+	}
+
+	switch (image_os) {
+	case IH_OS_U_BOOT:
+		debug("Jumping to U-Boot\n");
+		jump_to_image_no_args();
+		break;
+	default:
+		puts("Unsupported OS image.. Jumping nevertheless..\n");
+		jump_to_image_no_args();
+	}
+}
+
+void preloader_console_init(void)
+{
+	const char *u_boot_rev = U_BOOT_VERSION;
+	char rev_string_buffer[50];
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	setup_clocks_for_console();
+	serial_init();		/* serial communications setup */
+
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+
+	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+		U_BOOT_TIME);
+	omap_rev_string(rev_string_buffer);
+	printf("Texas Instruments %s\n", rev_string_buffer);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
new file mode 100644
index 0000000..8867e06
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/armv7/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 0000000..ea935da
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2011 Linaro Limited
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
index 522bcd2..8e85891 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -29,7 +29,6 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
-COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
 
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 98519a9..4aaf97b 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -38,12 +38,24 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <asm/omap_gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19..8d0496c 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -33,6 +33,8 @@
 
 extern omap3_sysinfo sysinfo;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+#ifdef CONFIG_DISPLAY_CPUINFO
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
 				"2.0",
@@ -42,6 +44,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
 				"UNKNOWN",
 				"UNKNOWN",
 				"3.1.2"};
+#endif /* CONFIG_DISPLAY_CPUINFO */
 
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index 987dc9d..e7ee0b8 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,8 +28,14 @@ LIB	=  $(obj)lib$(SOC).o
 SOBJS	+= lowlevel_init.o
 
 COBJS	+= board.o
+COBJS	+= clocks.o
+COBJS	+= emif.o
+COBJS	+= sdram_elpida.o
+
+ifndef CONFIG_SPL_BUILD
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index de4cc2a..5943d61 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -28,20 +28,181 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
+#include <asm/omap_gpio.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap_revision() >= OMAP4460_ES1_0)
+		writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
+}
+
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+static void init_omap4_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int arm_rev = cortex_a9_rev();
+
+	switch (arm_rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		*omap4_revision = OMAP4430_ES1_0;
+		break;
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
+			*omap4_revision = OMAP4430_ES2_1;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
+			*omap4_revision = OMAP4430_ES2_2;
+			break;
+		default:
+			*omap4_revision = OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		*omap4_revision = OMAP4430_ES2_3;
+		break;
+	case MIDR_CORTEX_A9_R2P10:
+		*omap4_revision = OMAP4460_ES1_0;
+		break;
+	default:
+		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
+		break;
+	}
+}
+
+void omap_rev_string(char *omap4_rev_string)
+{
+	u32 omap4_rev = omap_revision();
+	u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
+	u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
+	u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
+
+	sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+		minor_rev);
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing,  andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ *	Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
+	init_omap4_revision();
 	watchdog_init();
+	set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+#endif
+	prcm_init();
+#ifdef CONFIG_SPL_BUILD
+	/* For regular u-boot sdram_init() is called from dram_init() */
+	sdram_init();
+#endif
 }
 
 /*
@@ -76,17 +237,17 @@ void watchdog_init(void)
  * This is needed because the size of memory installed may be
  * different on different versions of the board
  */
-u32 sdram_size(void)
+u32 omap4_sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;
@@ -102,8 +263,8 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
-	gd->ram_size = sdram_size();
+	sdram_init();
+	gd->ram_size = omap4_sdram_size();
 
 	return 0;
 }
@@ -124,7 +285,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
new file mode 100644
index 0000000..eda960c
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -0,0 +1,940 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
+
+struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
+
+static const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	13000000,	       /* 13 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
+	{230, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{920, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{219, 3, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{575, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{460, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{920, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{575, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
+static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
+	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{330, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{165, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{396, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{88, 2, 1, -1, -1, -1, -1, -1},		/* 27 MHz   */
+	{165, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
+	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1
+};
+
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	u32 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl(&prcm->cm_sys_clksel) &
+			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+static inline void do_bypass_dpll(u32 *const base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_FAST_RELOCK_BYPASS <<
+			CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+				LDELAY)) {
+		printf("Bypassing DPLL failed %p\n", base);
+	}
+}
+
+static inline void do_lock_dpll(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
+		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 *const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+		&dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for %p\n", base);
+		hang();
+	}
+}
+
+static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+				u8 lock)
+{
+	u32 temp;
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, &dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, &dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, &dpll_regs->cm_div_m6_dpll);
+	if (params->m7 >= 0)
+		writel(params->m7, &dpll_regs->cm_div_m7_dpll);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+const struct dpll_params *get_core_dpll_params(void)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	switch (omap_revision()) {
+	case OMAP4430_ES1_0:
+		return &core_dpll_params_es1_1524mhz[sysclk_ind];
+	case OMAP4430_ES2_0:
+	case OMAP4430_SILICON_ID_INVALID:
+		 /* safest */
+		return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
+	default:
+		return &core_dpll_params_1600mhz[sysclk_ind];
+	}
+}
+
+u32 omap4_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz;
+	const struct dpll_params *core_dpll_params;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params();
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+	/*
+	 * DDR frequency is PHY_ROOT_CLK/2
+	 * PHY_ROOT_CLK = Fdpll/2/M2
+	 */
+	ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
+
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0	: 600 MHz
+ * 4430 ES2.x	: 792 MHz (OPP Turbo)
+ * 4460		: 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+	const struct dpll_params *params;
+	struct dpll_regs *mpu_dpll_regs;
+	u32 omap4_rev, sysclk_ind;
+
+	omap4_rev = omap_revision();
+	sysclk_ind = get_sys_clk_index();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else if (omap4_rev < OMAP4460_ES1_0)
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1840mhz[sysclk_ind];
+
+	/* DCC and clock divider settings for 4460 */
+	if (omap4_rev >= OMAP4460_ES1_0) {
+		mpu_dpll_regs =
+			(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
+		bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
+		clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+		setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+			CM_CLKSEL_DCC_EN_MASK);
+	}
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
+static void setup_dplls(void)
+{
+	u32 sysclk_ind, temp;
+	const struct dpll_params *params;
+	debug("setup_dplls\n");
+
+	sysclk_ind = get_sys_clk_index();
+
+	/* CORE dpll */
+	params = get_core_dpll_params();	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, &prcm->cm_clksel_core);
+	debug("Core DPLL configured\n");
+
+	/* lock PER dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+			&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
+	debug("PER DPLL locked\n");
+
+	/* MPU dpll */
+	configure_mpu_dpll();
+}
+
+static void setup_non_essential_dplls(void)
+{
+	u32 sys_clk_khz, abe_ref_clk;
+	u32 sysclk_ind, sd_div, num, den;
+	const struct dpll_params *params;
+
+	sysclk_ind = get_sys_clk_index();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/* IVA */
+	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
+			&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
+
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = &usb_dpll_params_1920mhz[sysclk_ind];
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
+
+#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
+	params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+#else
+	params = &abe_dpll_params_32k_196608khz;
+	abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
+	/*
+	 * We need to enable some additional options to achieve
+	 * 196.608MHz from 32768 Hz
+	 */
+	setbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
+			CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
+			CM_CLKMODE_DPLL_LPMODE_EN_MASK|
+			CM_CLKMODE_DPLL_REGM4XEN_MASK);
+	/* Spend 4 REFCLK cycles at each stage */
+	clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+			CM_CLKMODE_DPLL_RAMP_RATE_MASK,
+			1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
+#endif
+
+	/* Select the right reference clk */
+	clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+			CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
+			abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
+	/* Lock the dpll */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
+}
+
+static void do_scale_tps62361(u32 reg, u32 volt_mv)
+{
+	u32 temp, step;
+
+	step = volt_mv - TPS62361_BASE_VOLT_MV;
+	step /= 10;
+
+	/*
+	 * Select SET1 in TPS62361:
+	 * VSEL1 is grounded on board. So the following selects
+	 * VSEL1 = 0 and VSEL0 = 1
+	 */
+	omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);
+	omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);
+
+	temp = TPS62361_I2C_SLAVE_ADDR |
+	    (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
+
+	writel(temp, &prcm->prm_vc_val_bypass);
+	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				&prcm->prm_vc_val_bypass, LDELAY)) {
+		puts("Scaling voltage failed for vdd_mpu from TPS\n");
+	}
+}
+
+static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+{
+	u32 temp, offset_code;
+	u32 step = 12660; /* 12.66 mV represented in uV */
+	u32 offset = volt_mv;
+
+	/* convert to uV for better accuracy in the calculations */
+	offset *= 1000;
+
+	if (omap_revision() == OMAP4430_ES1_0)
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+	else
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+	offset_code = (offset + step - 1) / step;
+	/* The code starts at 1 not 0 */
+	offset_code++;
+
+	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+		offset_code);
+
+	temp = SMPS_I2C_SLAVE_ADDR |
+	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
+	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
+	    PRM_VC_VAL_BYPASS_VALID_BIT;
+	writel(temp, &prcm->prm_vc_val_bypass);
+	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
+				&prcm->prm_vc_val_bypass, LDELAY)) {
+		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+	}
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+static void scale_vcores(void)
+{
+	u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
+
+	/* Disable high speed mode and all advanced features */
+	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
+
+	omap4_rev = omap_revision();
+	/* TPS - supplies vdd_mpu on 4460 */
+	if (omap4_rev >= OMAP4460_ES1_0) {
+		volt = 1430;
+		do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+	}
+
+	/*
+	 * VCORE 1
+	 *
+	 * 4430 : supplies vdd_mpu
+	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
+	 * We use the maximum possible value in the AVS range because the next
+	 * higher voltage in the discrete range (code >= 0b111010) is way too
+	 * high
+	 *
+	 * 4460 : supplies vdd_core
+	 */
+	if (omap4_rev < OMAP4460_ES1_0) {
+		volt = 1417;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+	} else {
+		volt = 1200;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+	}
+
+	/* VCORE 2 - supplies vdd_iva */
+	volt = 1200;
+	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
+	/*
+	 * VCORE 3
+	 * 4430 : supplies vdd_core
+	 * 4460 : not connected
+	 */
+	if (omap4_rev < OMAP4460_ES1_0) {
+		volt = 1200;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+	}
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+				clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_basic_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 1;
+	u32 *const clk_domains_essential[] = {
+		&prcm->cm_l4per_clkstctrl,
+		&prcm->cm_l3init_clkstctrl,
+		&prcm->cm_memif_clkstctrl,
+		&prcm->cm_l4cfg_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_essential[] = {
+		&prcm->cm_wkup_gpio1_clkctrl,
+		&prcm->cm_l4per_gpio2_clkctrl,
+		&prcm->cm_l4per_gpio3_clkctrl,
+		&prcm->cm_l4per_gpio4_clkctrl,
+		&prcm->cm_l4per_gpio5_clkctrl,
+		&prcm->cm_l4per_gpio6_clkctrl,
+		&prcm->cm_memif_emif_1_clkctrl,
+		&prcm->cm_memif_emif_2_clkctrl,
+		&prcm->cm_l3init_hsusbotg_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_l4cfg_l4_cfg_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_essential[] = {
+		&prcm->cm_l4per_gptimer2_clkctrl,
+		&prcm->cm_l3init_hsmmc1_clkctrl,
+		&prcm->cm_l3init_hsmmc2_clkctrl,
+		&prcm->cm_l4per_mcspi1_clkctrl,
+		&prcm->cm_wkup_gptimer1_clkctrl,
+		&prcm->cm_l4per_i2c1_clkctrl,
+		&prcm->cm_l4per_i2c2_clkctrl,
+		&prcm->cm_l4per_i2c3_clkctrl,
+		&prcm->cm_l4per_i2c4_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_l4per_uart3_clkctrl,
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
+			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
+		enable_clock_domain(clk_domains_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+static void enable_non_essential_clocks(void)
+{
+	u32 i, max = 100, wait_for_enable = 0;
+	u32 *const clk_domains_non_essential[] = {
+		&prcm->cm_mpu_m3_clkstctrl,
+		&prcm->cm_ivahd_clkstctrl,
+		&prcm->cm_dsp_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sgx_clkstctrl,
+		&prcm->cm1_abe_clkstctrl,
+		&prcm->cm_c2c_clkstctrl,
+		&prcm->cm_cam_clkstctrl,
+		&prcm->cm_dss_clkstctrl,
+		&prcm->cm_sdma_clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_hw_auto_non_essential[] = {
+		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
+		&prcm->cm_ivahd_ivahd_clkctrl,
+		&prcm->cm_ivahd_sl2_clkctrl,
+		&prcm->cm_dsp_dsp_clkctrl,
+		&prcm->cm_l3_2_gpmc_clkctrl,
+		&prcm->cm_l3instr_l3_3_clkctrl,
+		&prcm->cm_l3instr_l3_instr_clkctrl,
+		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
+		&prcm->cm_l3init_hsi_clkctrl,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_non_essential[] = {
+		&prcm->cm1_abe_aess_clkctrl,
+		&prcm->cm1_abe_pdm_clkctrl,
+		&prcm->cm1_abe_dmic_clkctrl,
+		&prcm->cm1_abe_mcasp_clkctrl,
+		&prcm->cm1_abe_mcbsp1_clkctrl,
+		&prcm->cm1_abe_mcbsp2_clkctrl,
+		&prcm->cm1_abe_mcbsp3_clkctrl,
+		&prcm->cm1_abe_slimbus_clkctrl,
+		&prcm->cm1_abe_timer5_clkctrl,
+		&prcm->cm1_abe_timer6_clkctrl,
+		&prcm->cm1_abe_timer7_clkctrl,
+		&prcm->cm1_abe_timer8_clkctrl,
+		&prcm->cm1_abe_wdt3_clkctrl,
+		&prcm->cm_l4per_gptimer9_clkctrl,
+		&prcm->cm_l4per_gptimer10_clkctrl,
+		&prcm->cm_l4per_gptimer11_clkctrl,
+		&prcm->cm_l4per_gptimer3_clkctrl,
+		&prcm->cm_l4per_gptimer4_clkctrl,
+		&prcm->cm_l4per_hdq1w_clkctrl,
+		&prcm->cm_l4per_mcbsp4_clkctrl,
+		&prcm->cm_l4per_mcspi2_clkctrl,
+		&prcm->cm_l4per_mcspi3_clkctrl,
+		&prcm->cm_l4per_mcspi4_clkctrl,
+		&prcm->cm_l4per_mmcsd3_clkctrl,
+		&prcm->cm_l4per_mmcsd4_clkctrl,
+		&prcm->cm_l4per_mmcsd5_clkctrl,
+		&prcm->cm_l4per_uart1_clkctrl,
+		&prcm->cm_l4per_uart2_clkctrl,
+		&prcm->cm_l4per_uart4_clkctrl,
+		&prcm->cm_wkup_keyboard_clkctrl,
+		&prcm->cm_wkup_wdtimer2_clkctrl,
+		&prcm->cm_cam_iss_clkctrl,
+		&prcm->cm_cam_fdif_clkctrl,
+		&prcm->cm_dss_dss_clkctrl,
+		&prcm->cm_sgx_sgx_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
+		0
+	};
+
+	/* Enable optional functional clock for ISS */
+	setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable all optional functional clocks of DSS */
+	setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
+	     i++) {
+		enable_clock_module(clk_modules_explicit_en_non_essential[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
+		enable_clock_domain(clk_domains_non_essential[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+
+	/* Put camera module in no sleep mode */
+	clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
+			CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+
+	core_dpll_params = get_core_dpll_params();
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+	freq_config1 |= (core_dpll_params->m2 <<
+			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+	writel(freq_config1, &prcm->cm_shadow_freq_config1);
+	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+				&prcm->cm_shadow_freq_config1, LDELAY)) {
+		puts("FREQ UPDATE procedure failed!!");
+		hang();
+	}
+
+	/* Put EMIF clock domain back in hw auto mode */
+	enable_clock_domain(&prcm->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+}
+
+void bypass_dpll(u32 *const base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 *const base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable all UARTs - console will be on one of them */
+	clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
+void prcm_init(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
+		scale_vcores();
+		setup_dplls();
+		setup_non_essential_dplls();
+		enable_non_essential_clocks();
+		break;
+	default:
+		break;
+	}
+}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/Makefile b/arch/arm/cpu/armv7/omap4/config.mk
index 7530e6a..b34fa64 100644
--- a/arch/arm/cpu/arm920t/at91rm9200/Makefile
+++ b/arch/arm/cpu/armv7/omap4/config.mk
@@ -1,10 +1,13 @@
 #
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
+# Copyright 2011 Linaro Limited
 # See file CREDITS for list of people who contributed to this
 # project.
 #
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
@@ -20,37 +23,8 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-SOBJS	+= lowlevel_init.o
-
-COBJS	+= bcm5221.o
-COBJS	+= dm9161.o
-COBJS	+= ether.o
-COBJS	+= i2c.o
-COBJS-$(CONFIG_KS8721_PHY)	+= ks8721.o
-COBJS	+= lxt972.o
-COBJS	+= reset.o
-COBJS	+= spi.o
-COBJS	+= timer.o
-COBJS	+= usb.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 0000000..487ec42
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,1310 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+
+static inline u32 emif_num(u32 base)
+{
+	if (base == OMAP44XX_EMIF1)
+		return 1;
+	else if (base == OMAP44XX_EMIF2)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << OMAP44XX_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= OMAP44XX_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+	sdelay(2000);
+	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK);
+
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK);
+
+}
+
+static void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+			&emif->emif_l3_config);
+	} else {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+			&emif->emif_l3_config);
+	}
+}
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+static u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	config_reg |=  (cs0_device->type + 4) << OMAP44XX_REG_SDRAM_TYPE_SHIFT;
+	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+			OMAP44XX_REG_IBANK_POS_SHIFT;
+
+	config_reg |= cs0_device->io_width << OMAP44XX_REG_NARROW_MODE_SHIFT;
+
+	config_reg |= RL << OMAP44XX_REG_CL_SHIFT;
+
+	config_reg |= addressing->row_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_ROWSIZE_SHIFT;
+
+	config_reg |= addressing->num_banks << OMAP44XX_REG_IBANK_SHIFT;
+
+	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+			OMAP44XX_REG_EBANK_SHIFT;
+
+	config_reg |= addressing->col_sz[cs0_device->io_width] <<
+			OMAP44XX_REG_PAGESIZE_SHIFT;
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	ref_ctrl |= val << OMAP44XX_REG_REFRESH_RATE_SHIFT;
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WTR_SHIFT;
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	tim1 |= val << OMAP44XX_REG_T_RRD_SHIFT;
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RC_SHIFT;
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RCD_SHIFT;
+
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	tim1 |= val << OMAP44XX_REG_T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	tim2 |= val << OMAP44XX_REG_T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_RTP_SHIFT;
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XSRD_SHIFT;
+	tim2 |= val << OMAP44XX_REG_T_XSNR_SHIFT;
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	tim2 |= val << OMAP44XX_REG_T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	tim3 |= val << OMAP44XX_REG_T_RAS_MAX_SHIFT;
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	tim3 |= val << OMAP44XX_REG_T_RFC_SHIFT;
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	tim3 |= val << OMAP44XX_REG_T_TDQSCKMAX_SHIFT;
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	tim3 |= val << OMAP44XX_REG_ZQ_ZQCS_SHIFT;
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	tim3 |= val << OMAP44XX_REG_T_CKESR_SHIFT;
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	zq |= val << OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT;
+
+	zq |= (REG_ZQ_ZQCL_MULT - 1) << OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT;
+
+	zq |= (REG_ZQ_ZQINIT_MULT - 1) << OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= REG_ZQ_SFEXITEN_ENABLE << OMAP44XX_REG_ZQ_SFEXITEN_SHIFT;
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	zq |= REG_ZQ_DUALCALEN_DISABLE << OMAP44XX_REG_ZQ_DUALCALEN_SHIFT;
+
+	zq |= REG_ZQ_CS0EN_ENABLE << OMAP44XX_REG_ZQ_CS0EN_SHIFT;
+
+	zq |= (cs1_device ? 1 : 0) << OMAP44XX_REG_ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	alert |= interval << OMAP44XX_REG_TA_REFINTERVAL_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << OMAP44XX_REG_TA_DEVCNT_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << OMAP44XX_REG_TA_DEVWDT_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_SFEXITEN_SHIFT;
+
+	alert |= 1 << OMAP44XX_REG_TA_CS0EN_SHIFT;
+
+	alert |= (cs1_device ? 1 : 0) << OMAP44XX_REG_TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	idle |= val << OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT;
+
+	idle |= EMIF_REG_READ_IDLE_LEN_VAL << OMAP44XX_REG_READ_IDLE_LEN_SHIFT;
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	phy |= (RL + 2) << OMAP44XX_REG_READ_LATENCY_SHIFT;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	phy |= val << OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+	/* Other fields are constant magic values. Hardcode them together */
+	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+		OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+	return phy;
+}
+
+static u32 get_emif_mem_size(struct emif_device_details *devices)
+{
+	u32 size_mbytes = 0, temp;
+
+	if (!devices)
+		return 0;
+
+	if (devices->cs0_device_details) {
+		temp = devices->cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (devices->cs1_device_details) {
+		temp = devices->cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 333 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_333_mhz = {
+	.max_freq = 333000000,
+	.RL = 5,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_333_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = &jedec_default_timings;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 base = (emif_nr == 1) ? OMAP44XX_EMIF1 : OMAP44XX_EMIF2;
+
+	if (running_from_sdram()) {
+		/*
+		 * We can not do automatic discovery running from SDRAM
+		 * Most likely we came here by mistake. Indicate error
+		 * by returning NULL
+		 */
+		cs0_device_details = NULL;
+		cs1_device_details = NULL;
+	} else {
+		/*
+		 * Automatically find the device details:
+		 *
+		 * Reset the PHY after each call to get_lpddr2_details().
+		 * If there is nothing connected to a given chip select
+		 * (typically CS1) mode register reads will mess up with
+		 * the PHY state and subsequent initialization won't work.
+		 * PHY reset brings back PHY to a good state.
+		 */
+		cs0_device_details =
+		    get_lpddr2_details(base, CS0, cs0_device_details);
+		emif_reset_phy(base);
+
+		cs1_device_details =
+		    get_lpddr2_details(base, CS1, cs1_device_details);
+		emif_reset_phy(base);
+	}
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs;
+	u32 in_sdram, emif_nr;
+
+	debug(">>do_sdram_init() %x\n", base);
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	emif_get_reg_dump(emif_nr, &regs);
+	if (!regs) {
+		debug("EMIF: reg dump not provided\n");
+		return;
+	}
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+	struct emif_device_details dev_details;
+	struct emif_regs calculated_regs;
+
+	/*
+	 * Get device details:
+	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+	 * - Obtained from user otherwise
+	 */
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	emif_get_device_details(emif_nr, &cs0_dev_details,
+				&cs1_dev_details);
+	dev_details.cs0_device_details = &cs0_dev_details;
+	dev_details.cs1_device_details = &cs1_dev_details;
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		emif_sizes[emif_nr - 1] = 0;
+		return;
+	}
+
+	if (!in_sdram)
+		emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
+
+	/*
+	 * Get device timings:
+	 * - Default timings specified by JESD209-2 if
+	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+	 * - Obtained from user otherwise
+	 */
+	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+				&dev_details.cs1_device_timings);
+
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap4_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!in_sdram)
+		lpddr2_init(base, regs);
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+
+	debug("<<do_sdram_init() %x\n", base);
+}
+
+void sdram_init_pads(void)
+{
+	u32 lpddr2io;
+	struct control_lpddr2io_regs *lpddr2io_regs =
+		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		return;		/* Post ES2.1 reset values will work */
+
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+	writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);
+
+	writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);
+}
+
+static void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap4_rev = omap_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap4_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap4_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+static void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = emif_sizes[0];
+	emif2_size = emif_sizes[1];
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		section_map |= 0 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) <<
+				OMAP44XX_SYS_ADDR_SHIFT;
+		section_map |= get_dmm_section_size_map(mapped_size * 2)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif1_size)
+				<< OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= (mapped_size >> 24) <<
+				OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif2_size) <<
+				OMAP44XX_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= mapped_size >> 24 << OMAP44XX_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= sys_addr >> 24 << OMAP44XX_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		hw_lisa_map_regs =
+		    (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
+
+		writel(lisa_map_regs->dmm_lisa_map_3,
+			&hw_lisa_map_regs->dmm_lisa_map_3);
+		writel(lisa_map_regs->dmm_lisa_map_2,
+			&hw_lisa_map_regs->dmm_lisa_map_2);
+		writel(lisa_map_regs->dmm_lisa_map_1,
+			&hw_lisa_map_regs->dmm_lisa_map_1);
+		writel(lisa_map_regs->dmm_lisa_map_0,
+			&hw_lisa_map_regs->dmm_lisa_map_0);
+	}
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram, size_prog, size_detect;
+
+	debug(">>sdram_init()\n");
+
+	if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	in_sdram = running_from_sdram();
+	debug("in_sdram = %d\n", in_sdram);
+
+	if (!in_sdram) {
+		sdram_init_pads();
+		bypass_dpll(&prcm->cm_clkmode_dpll_core);
+	}
+
+	do_sdram_init(OMAP44XX_EMIF1);
+	do_sdram_init(OMAP44XX_EMIF2);
+
+	if (!in_sdram) {
+		dmm_init(OMAP44XX_DMM_LISA_MAP_BASE);
+		emif_post_init_config(OMAP44XX_EMIF1);
+		emif_post_init_config(OMAP44XX_EMIF2);
+
+	}
+
+	/* for the shadow registers to take effect */
+	freq_update_core();
+
+	/* Do some testing after the init */
+	if (!in_sdram) {
+		size_prog = omap4_sdram_size();
+		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+						size_prog);
+		/* Compare with the size programmed */
+		if (size_detect != size_prog) {
+			printf("SDRAM: identified size not same as expected"
+				" size identified: %x expected: %x\n",
+				size_detect,
+				size_prog);
+		} else
+			debug("get_ram_size() successful");
+	}
+
+	debug("<<sdram_init()\n");
+}
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
index 6abfbba..91525ec 100644
--- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -27,6 +27,37 @@
  */
 
 #include <asm/arch/omap4.h>
+#ifdef CONFIG_SPL_BUILD
+.global save_boot_params
+save_boot_params:
+	/*
+	 * See if the rom code passed pointer is valid:
+	 * It is not valid if it is not in non-secure SRAM
+	 * This may happen if you are booting with the help of
+	 * debugger
+	 */
+	ldr     r2, =NON_SECURE_SRAM_START
+	cmp	r2, r0
+	bgt	1f
+	ldr	r2, =NON_SECURE_SRAM_END
+	cmp	r2, r0
+	blt	1f
+
+	/* Store the boot device in omap4_boot_device */
+	ldr     r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
+	and	r2, #BOOT_DEVICE_MASK
+	ldr	r3, =omap4_boot_device
+	str     r2, [r3]			@ omap4_boot_device <- r1
+
+	/* Store the boot mode (raw/FAT) in omap4_boot_mode */
+	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
+	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
+	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode
+	ldr	r3, =omap4_boot_mode
+	str	r2, [r3]
+1:
+	bx	lr
+#endif
 
 .globl lowlevel_init
 lowlevel_init:
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
new file mode 100644
index 0000000..00c52f8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
@@ -0,0 +1,76 @@
+ /*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_MUX_DATA_H_
+#define _OMAP4_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 0000000..7757aad
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,282 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
+ * SDP and Panda. Since the parts used and geometry are identical for
+ * SDP and Panda for a given OMAP4 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP4 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_2cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	u32 omap_rev = omap_revision();
+
+	/* EMIF1 & EMIF2 have identical configuration */
+	*cs0_device_details = elpida_2G_S4_details;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		cs1_device_details = NULL;
+	else
+		*cs1_device_details = elpida_2G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	u32 omap_rev = omap_revision();
+
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*cs1_device_timings = NULL;
+	else
+		*cs1_device_timings = &elpida_2G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5c87e9c..db8e9d2 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -42,7 +42,16 @@ _start: b	reset
 	ldr	pc, _not_used
 	ldr	pc, _irq
 	ldr	pc, _fiq
-
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -51,6 +60,8 @@ _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
 _pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
 .global _end_vect
 _end_vect:
 
@@ -89,6 +100,10 @@ _armboot_start:
 _bss_start_ofs:
 	.word __bss_start - _start
 
+.global	_image_copy_end_ofs
+_image_copy_end_ofs:
+	.word 	__image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
 	.word __bss_end__ - _start
@@ -119,6 +134,7 @@ IRQ_STACK_START_IN:
  */
 
 reset:
+	bl	save_boot_params
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -182,12 +198,11 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
-#ifndef CONFIG_SPL_BUILD
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
-#endif
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
+	ldr	r3, _image_copy_end_ofs
 	add	r2, r0, r3		/* r2 <- source end address	    */
 
 copy_loop:
@@ -235,20 +250,34 @@ fixnext:
 	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
 	cmp	r2, r3
 	blo	fixloop
+	b	clear_bss
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 clear_bss:
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
-#endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -276,12 +305,6 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
@@ -329,6 +352,8 @@ cpu_init_crit:
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
 #endif
+
+#ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
@@ -516,4 +541,5 @@ fiq:
 	bad_save_user_regs
 	bl	do_fiq
 
-#endif
+#endif /* CONFIG_USE_IRQ */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index dbae54d..40ecf78 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -55,6 +55,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index 73783a7..d6e0494 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -57,8 +57,8 @@
 #define MFP89_UART2_TXD		(MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* UART3 */
-#define MFPO8_UART3_RXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFPO9_UART3_TXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO8_UART3_TXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_RXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* I2c */
 #define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
index c520e89..afe724d 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -33,7 +33,7 @@ typedef struct at91_spi {
 	at91_pdc_t	pdc;
 } at91_spi_t;
 
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 
 #define AT91_SPI_CR			0x00		/* Control Register */
 #define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h
index c85fd29..59b1864 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9261.h
@@ -104,7 +104,7 @@
 #define ATMEL_SIZE_SRAM		0x00028000	/* Internal SRAM size (160Kb) */
 
 #define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
-#define ATMEL_SIZE_ROM		SZ_32K		/* Internal ROM size (32Kb) */
+#define ATMEL_SIZE_ROM		0x00008000	/* Internal ROM size (32Kb) */
 
 #define ATMEL_BASE_UHP		0x00500000	/* USB Host controller */
 #define ATMEL_BASE_LCDC		0x00600000	/* LDC controller */
@@ -125,6 +125,7 @@
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS		3		/* theese SoCs have 3 PIO */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 #define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
 
 /*
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
index e2bfc4b..913b4d7 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
@@ -15,50 +15,45 @@
 #ifndef AT91SAM9261_MATRIX_H
 #define AT91SAM9261_MATRIX_H
 
-#define AT91_MATRIX_MCFG	(AT91_MATRIX + 0x00)	/* Master Configuration Register */
-#define		AT91_MATRIX_RCB0	(1 << 0)		/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1	(1 << 1)		/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#ifndef __ASSEMBLY__
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x04)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x08)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x0C)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x10)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x14)	/* Slave Configuration Register 4 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
+struct at91_matrix {
+	u32	mcfg;	/* Master Configuration Registers */
+	u32	scfg[5];	/* Slave Configuration Registers */
+	u32	filler[6];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+#endif /* __ASSEMBLY__ */
 
-#define AT91_MATRIX_TCR		(AT91_MATRIX + 0x24)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define			AT91_MATRIX_ITCM_64		(7 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-#define			AT91_MATRIX_DTCM_64		(7 << 4)
+#define AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x30)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_USBPUCR	(AT91_MATRIX + 0x34)	/* USB Pad Pull-Up Control Register */
-#define		AT91_MATRIX_USBPUCR_PUON	(1 << 30)	/* USB Device PAD Pull-up Enable */
+#define AT91_MATRIX_M0PR_SHIFT          0
+#define AT91_MATRIX_M1PR_SHIFT          4
+#define AT91_MATRIX_M2PR_SHIFT          8
+#define AT91_MATRIX_M3PR_SHIFT          12
+#define AT91_MATRIX_M4PR_SHIFT          16
+#define AT91_MATRIX_M5PR_SHIFT          20
+
+#define AT91_MATRIX_RCB0                (1 << 0)
+#define AT91_MATRIX_RCB1                (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define AT91_MATRIX_DBPUC               (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h
index 2a1d6ee..bf9ff76 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -125,10 +125,23 @@
 #define ATMEL_BASE_UHP		0x00a00000	/* USB Host controller */
 
 /*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+#define ATMEL_BASE_CS6		0x70000000
+#define ATMEL_BASE_CS7		0x80000000
+
+/*
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
 #define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 
 /*
  * Cpu Name
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
index 83aaaab..3f67093 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
@@ -15,115 +15,53 @@
 #ifndef AT91SAM9263_MATRIX_H
 #define AT91SAM9263_MATRIX_H
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#ifndef __ASSEMBLY__
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * Note: not all masters/slaves are available
+ */
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[0x06];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
 
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
-#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
-#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
 
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-#define		AT91_MATRIX_RCB6		(1 << 6)
-#define		AT91_MATRIX_RCB7		(1 << 7)
-#define		AT91_MATRIX_RCB8		(1 << 8)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
 
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x114)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20
 
-#define AT91_MATRIX_EBI0CSA	(AT91_MATRIX + 0x120)	/* EBI0 Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI0_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI0_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI0_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI0_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI0_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI0_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_EBI0_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_EBI0_CS4A_SMC_CF1		(1 << 4)
-#define		AT91_MATRIX_EBI0_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_EBI0_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_EBI0_CS5A_SMC_CF2		(1 << 5)
-#define		AT91_MATRIX_EBI0_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_EBI0_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		(1 << 16)
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)
 
-#define AT91_MATRIX_EBI1CSA	(AT91_MATRIX + 0x124)	/* EBI1 Chip Select Assignment Register */
-#define		AT91_MATRIX_EBI1_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_EBI1_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_EBI1_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_EBI1_CS2A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_EBI1_CS2A_SMC		(0 << 3)
-#define			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_EBI1_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_EBI1_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		(0 << 16)
-#define			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		(1 << 16)
+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..00b6aa4 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -15,116 +15,117 @@
 #define AT91SAM9RL_H
 
 /*
- * Peripheral identifiers/interrupts.
+ * defines to be used in other places
  */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Controller */
-#define AT91SAM9RL_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD	5	/* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0	6	/* USART 0 */
-#define AT91SAM9RL_ID_US1	7	/* USART 1 */
-#define AT91SAM9RL_ID_US2	8	/* USART 2 */
-#define AT91SAM9RL_ID_US3	9	/* USART 3 */
-#define AT91SAM9RL_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0	11	/* TWI 0 */
-#define AT91SAM9RL_ID_TWI1	12	/* TWI 1 */
-#define AT91SAM9RL_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0	16	/* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1	17	/* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2	18	/* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC	20	/* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA	21	/* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS	22	/* USB Device HS */
-#define AT91SAM9RL_ID_LCDC	23	/* LCD Controller */
-#define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
-
-#define AT91_SDRAMC_BASE	0xffffea00
-#define AT91_SMC_BASE		0xffffec00
-#define AT91_MATRIX_BASE	0xffffee00
-#define AT91_PIO_BASE		0xfffff400
-#define AT91_PMC_BASE		0xfffffc00
-#define AT91_RSTC_BASE		0xfffffd00
-#define AT91_PIT_BASE		0xfffffd30
-#define AT91_WDT_BASE		0xfffffd40
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
 
-#ifdef CONFIG_AT91_LEGACY
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Peripherals */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
+#define ATMEL_ID_PIOD	5	/* Parallel IO Controller D */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_USART3	9	/* USART 3 */
+#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
+#define ATMEL_ID_TWI0	11	/* TWI 0 */
+#define ATMEL_ID_TWI1	12	/* TWI 1 */
+#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
+#define ATMEL_ID_TC0	16	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	17	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	18	/* Timer Counter 2 */
+#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	20	/* Touch Screen Controller */
+#define ATMEL_ID_DMA	21	/* DMA Controller */
+#define ATMEL_ID_UDPHS	22	/* USB Device HS */
+#define ATMEL_ID_LCDC	23	/* LCD Controller */
+#define ATMEL_ID_AC97C	24	/* AC97 Controller */
+#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
 
 /*
  * User Peripheral physical base addresses.
  */
-#define AT91SAM9RL_BASE_TCB0	0xfffa0000
-#define AT91SAM9RL_BASE_TC0	0xfffa0000
-#define AT91SAM9RL_BASE_TC1	0xfffa0040
-#define AT91SAM9RL_BASE_TC2	0xfffa0080
-#define AT91SAM9RL_BASE_MCI	0xfffa4000
-#define AT91SAM9RL_BASE_TWI0	0xfffa8000
-#define AT91SAM9RL_BASE_TWI1	0xfffac000
-#define AT91SAM9RL_BASE_US0	0xfffb0000
-#define AT91SAM9RL_BASE_US1	0xfffb4000
-#define AT91SAM9RL_BASE_US2	0xfffb8000
-#define AT91SAM9RL_BASE_US3	0xfffbc000
-#define AT91SAM9RL_BASE_SSC0	0xfffc0000
-#define AT91SAM9RL_BASE_SSC1	0xfffc4000
-#define AT91SAM9RL_BASE_PWMC	0xfffc8000
-#define AT91SAM9RL_BASE_SPI	0xfffcc000
-#define AT91SAM9RL_BASE_TSC	0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS	0xfffd4000
-#define AT91SAM9RL_BASE_AC97C	0xfffd8000
-#define AT91_BASE_SYS		0xffffc000
+#define ATMEL_BASE_TCB0		0xfffa0000
+#define ATMEL_BASE_TC0		0xfffa0000
+#define ATMEL_BASE_TC1		0xfffa0040
+#define ATMEL_BASE_TC2		0xfffa0080
+#define ATMEL_BASE_MCI		0xfffa4000
+#define ATMEL_BASE_TWI0		0xfffa8000
+#define ATMEL_BASE_TWI1		0xfffac000
+#define ATMEL_BASE_USART0	0xfffb0000
+#define ATMEL_BASE_USART1	0xfffb4000
+#define ATMEL_BASE_USART2	0xfffb8000
+#define ATMEL_BASE_USART3	0xfffbc000
+#define ATMEL_BASE_SSC0		0xfffc0000
+#define ATMEL_BASE_SSC1		0xfffc4000
+#define ATMEL_BASE_PWMC		0xfffc8000
+#define ATMEL_BASE_SPI0		0xfffcc000
+#define ATMEL_BASE_TSC		0xfffd0000
+#define ATMEL_BASE_UDPHS	0xfffd4000
+#define ATMEL_BASE_AC97C	0xfffd8000
+#define ATMEL_BASE_SYS		0xffffc000
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_DMA	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC	(0xfffffe00 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91SAM9RL_BASE_US0
-#define AT91_USART1	AT91SAM9RL_BASE_US1
-#define AT91_USART2	AT91SAM9RL_BASE_US2
-#define AT91_USART3	AT91SAM9RL_BASE_US3
-
-#endif /* CONFIG_AT91_LEGACY */
+#define ATMEL_BASE_DMA		0xffffe600
+#define ATMEL_BASE_ECC		0xffffe800
+#define ATMEL_BASE_SDRAMC	0xffffea00
+#define ATMEL_BASE_SMC		0xffffec00
+#define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_CCFG		0xffffef10
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+#define ATMEL_BASE_PIOD		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWC	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_SCKCR	0xfffffd50
+#define ATMEL_BASE_GPBR		0xfffffd60
+#define ATMEL_BASE_RTC		0xfffffe00
 
 /*
  * Internal Memory.
  */
-#define AT91SAM9RL_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */
+#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
+
+#define ATMEL_BASE_LCDC		0x00500000	/* LCD Controller */
+#define ATMEL_UHP_BASE		0x00600000	/* USB Device HS controller */
 
-#define AT91SAM9RL_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE	(2 * SZ_16K)	/* Internal ROM size (32Kb) */
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* NAND */
+#define ATMEL_BASE_CS4		0x50000000	/* Compact Flash Slot 0 */
+#define ATMEL_BASE_CS5		0x60000000	/* Compact Flash Slot 1 */
 
-#define AT91SAM9RL_LCDC_BASE	0x00500000	/* LCD Controller */
-#define AT91SAM9RL_UDPHS_BASE	0x00600000	/* USB Device HS controller */
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		4		/* this SoC has 4 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
 
 /*
  * Cpu Name
  */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9RL"
+#define ATMEL_CPU_NAME		"AT91SAM9RL"
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
index af8d914..295f768 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
@@ -14,83 +14,48 @@
 #ifndef AT91SAM9RL_MATRIX_H
 #define AT91SAM9RL_MATRIX_H
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
-
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
-
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x114)	/* TCM Configuration Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
-
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI0 Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[7];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20
+
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h b/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
deleted file mode 100644
index 00bae1c..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
+++ /dev/null
@@ -1,812 +0,0 @@
-/*
- * (C) Copyright 2003
- * AT91RM9200 definitions
- * Author : ATMEL AT91 application group
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface       */
-/*****************************************************************************/
-typedef struct _AT91S_TC
-{
-	AT91_REG	 TC_CCR;	/* Channel Control Register */
-	AT91_REG	 TC_CMR;	/* Channel Mode Register */
-	AT91_REG	 Reserved0[2];	/*  */
-	AT91_REG	 TC_CV;		/* Counter Value */
-	AT91_REG	 TC_RA;		/* Register A */
-	AT91_REG	 TC_RB;		/* Register B */
-	AT91_REG	 TC_RC;		/* Register C */
-	AT91_REG	 TC_SR;		/* Status Register */
-	AT91_REG	 TC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 TC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 TC_IMR;	/* Interrupt Mask Register */
-} AT91S_TC, *AT91PS_TC;
-
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK	  ((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK*/
-#define AT91C_TC_XC0_CLOCK	  ((unsigned int) 0x5 <<  0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK	  ((unsigned int) 0x6 <<  0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK	  ((unsigned int) 0x7 <<  0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE	  ((unsigned int) 0x1)       /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE	  ((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE	  ((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS		  ((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG		  ((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN		  ((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command */
-
-/*****************************************************************************/
-/*                  SOFTWARE API DEFINITION  FOR Usart                       */
-/*****************************************************************************/
-typedef struct _AT91S_USART
-{
-	AT91_REG	 US_CR;		/* Control Register */
-	AT91_REG	 US_MR;		/* Mode Register */
-	AT91_REG	 US_IER;	/* Interrupt Enable Register */
-	AT91_REG	 US_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 US_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 US_CSR;	/* Channel Status Register */
-	AT91_REG	 US_RHR;	/* Receiver Holding Register */
-	AT91_REG	 US_THR;	/* Transmitter Holding Register */
-	AT91_REG	 US_BRGR;	/* Baud Rate Generator Register */
-	AT91_REG	 US_RTOR;	/* Receiver Time-out Register */
-	AT91_REG	 US_TTGR;	/* Transmitter Time-guard Register */
-	AT91_REG	 Reserved0[5];	/*  */
-	AT91_REG	 US_FIDI;	/* FI_DI_Ratio Register */
-	AT91_REG	 US_NER;	/* Nb Errors Register */
-	AT91_REG	 US_XXR;	/* XON_XOFF Register */
-	AT91_REG	 US_IF;		/* IRDA_FILTER Register */
-	AT91_REG	 Reserved1[44];	/*  */
-	AT91_REG	 US_RPR;	/* Receive Pointer Register */
-	AT91_REG	 US_RCR;	/* Receive Counter Register */
-	AT91_REG	 US_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 US_TCR;	/* Transmit Counter Register */
-	AT91_REG	 US_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 US_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 US_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 US_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 US_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 US_PTSR;	/* PDC Transfer Status Register */
-} AT91S_USART, *AT91PS_USART;
-
-/*****************************************************************************/
-/*          SOFTWARE API DEFINITION  FOR Clock Generator Controler           */
-/*****************************************************************************/
-typedef struct _AT91S_CKGR
-{
-	AT91_REG	 CKGR_MOR;	/* Main Oscillator Register */
-	AT91_REG	 CKGR_MCFR;	/* Main Clock  Frequency Register */
-	AT91_REG	 CKGR_PLLAR;	/* PLL A Register */
-	AT91_REG	 CKGR_PLLBR;	/* PLL B Register */
-} AT91S_CKGR, *AT91PS_CKGR;
-
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN	((unsigned int) 0x1  <<  0)	/* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCTEST	((unsigned int) 0x1  <<  1)	/* (CKGR) Oscillator Test */
-#define AT91C_CKGR_OSCOUNT	((unsigned int) 0xFF <<  8)	/* (CKGR) Main Oscillator Start-up Time */
-
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF	((unsigned int) 0xFFFF <<  0)	/* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY	((unsigned int) 0x1 << 16)	/* (CKGR) Main Clock Ready */
-
-/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
-#define AT91C_CKGR_DIVA		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVA_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVA_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLACOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL A Counter */
-#define AT91C_CKGR_OUTA		((unsigned int) 0x3   << 14)	/* (CKGR) PLL A Output Frequency Range */
-#define AT91C_CKGR_OUTA_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_MULA		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL A Multiplier */
-#define AT91C_CKGR_SRCA		((unsigned int) 0x1   << 29)	/* (CKGR) PLL A Source */
-
-/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIVB		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVB_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVB_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLBCOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL B Counter */
-#define AT91C_CKGR_OUTB		((unsigned int) 0x3   << 14)	/* (CKGR) PLL B Output Frequency Range */
-#define AT91C_CKGR_OUTB_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_MULB		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL B Multiplier */
-#define AT91C_CKGR_USB_96M	((unsigned int) 0x1   << 28)	/* (CKGR) Divider for USB Ports */
-#define AT91C_CKGR_USB_PLL	((unsigned int) 0x1   << 29)	/* (CKGR) PLL Use */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Parallel Input Output Controler       */
-/*****************************************************************************/
-typedef struct _AT91S_PIO
-{
-	AT91_REG	 PIO_PER;	/* PIO Enable Register */
-	AT91_REG	 PIO_PDR;	/* PIO Disable Register */
-	AT91_REG	 PIO_PSR;	/* PIO Status Register */
-	AT91_REG	 Reserved0[1];	/*  */
-	AT91_REG	 PIO_OER;	/* Output Enable Register */
-	AT91_REG	 PIO_ODR;	/* Output Disable Registerr */
-	AT91_REG	 PIO_OSR;	/* Output Status Register */
-	AT91_REG	 Reserved1[1];	/*  */
-	AT91_REG	 PIO_IFER;	/* Input Filter Enable Register */
-	AT91_REG	 PIO_IFDR;	/* Input Filter Disable Register */
-	AT91_REG	 PIO_IFSR;	/* Input Filter Status Register */
-	AT91_REG	 Reserved2[1];	/*  */
-	AT91_REG	 PIO_SODR;	/* Set Output Data Register */
-	AT91_REG	 PIO_CODR;	/* Clear Output Data Register */
-	AT91_REG	 PIO_ODSR;	/* Output Data Status Register */
-	AT91_REG	 PIO_PDSR;	/* Pin Data Status Register */
-	AT91_REG	 PIO_IER;	/* Interrupt Enable Register */
-	AT91_REG	 PIO_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 PIO_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 PIO_ISR;	/* Interrupt Status Register */
-	AT91_REG	 PIO_MDER;	/* Multi-driver Enable Register */
-	AT91_REG	 PIO_MDDR;	/* Multi-driver Disable Register */
-	AT91_REG	 PIO_MDSR;	/* Multi-driver Status Register */
-	AT91_REG	 Reserved3[1];	/*  */
-	AT91_REG	 PIO_PPUDR;	/* Pull-up Disable Register */
-	AT91_REG	 PIO_PPUER;	/* Pull-up Enable Register */
-	AT91_REG	 PIO_PPUSR;	/* Pad Pull-up Status Register */
-	AT91_REG	 Reserved4[1];	/*  */
-	AT91_REG	 PIO_ASR;	/* Select A Register */
-	AT91_REG	 PIO_BSR;	/* Select B Register */
-	AT91_REG	 PIO_ABSR;	/* AB Select Status Register */
-	AT91_REG	 Reserved5[9];	/*  */
-	AT91_REG	 PIO_OWER;	/* Output Write Enable Register */
-	AT91_REG	 PIO_OWDR;	/* Output Write Disable Register */
-	AT91_REG	 PIO_OWSR;	/* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Debug Unit                      */
-/*****************************************************************************/
-typedef struct _AT91S_DBGU
-{
-	AT91_REG	 DBGU_CR;	/* Control Register */
-	AT91_REG	 DBGU_MR;	/* Mode Register */
-	AT91_REG	 DBGU_IER;	/* Interrupt Enable Register */
-	AT91_REG	 DBGU_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 DBGU_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 DBGU_CSR;	/* Channel Status Register */
-	AT91_REG	 DBGU_RHR;	/* Receiver Holding Register */
-	AT91_REG	 DBGU_THR;	/* Transmitter Holding Register */
-	AT91_REG	 DBGU_BRGR;	/* Baud Rate Generator Register */
-	AT91_REG	 Reserved0[7];	/*  */
-	AT91_REG	 DBGU_C1R;	/* Chip ID1 Register */
-	AT91_REG	 DBGU_C2R;	/* Chip ID2 Register */
-	AT91_REG	 DBGU_FNTR;	/* Force NTRST Register */
-	AT91_REG	 Reserved1[45];	/*  */
-	AT91_REG	 DBGU_RPR;	/* Receive Pointer Register */
-	AT91_REG	 DBGU_RCR;	/* Receive Counter Register */
-	AT91_REG	 DBGU_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 DBGU_TCR;	/* Transmit Counter Register */
-	AT91_REG	 DBGU_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 DBGU_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 DBGU_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 DBGU_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 DBGU_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 DBGU_PTSR;	/* PDC Transfer Status Register */
-} AT91S_DBGU, *AT91PS_DBGU;
-
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
-#define AT91C_US_RXRDY		((unsigned int) 0x1 <<  0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY		((unsigned int) 0x1 <<  1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX		((unsigned int) 0x1 <<  3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX		((unsigned int) 0x1 <<  4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE		((unsigned int) 0x1 <<  5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME		((unsigned int) 0x1 <<  6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE		((unsigned int) 0x1 <<  7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY	((unsigned int) 0x1 <<  9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE		((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF		((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX	((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX	((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
-
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
-#define AT91C_US_RSTRX		((unsigned int) 0x1 <<  2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX		((unsigned int) 0x1 <<  3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN		((unsigned int) 0x1 <<  4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS		((unsigned int) 0x1 <<  5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN		((unsigned int) 0x1 <<  6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS		((unsigned int) 0x1 <<  7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK	((unsigned int) 0x0 <<  4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE	((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-/*****************************************************************************/
-/*      SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface    */
-/*****************************************************************************/
-typedef struct _AT91S_SMC2
-{
-	AT91_REG	 SMC2_CSR[8];	/* SMC2 Chip Select Register */
-} AT91S_SMC2, *AT91PS_SMC2;
-
-/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------  */
-#define AT91C_SMC2_NWS			((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
-#define AT91C_SMC2_WSEN			((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_SMC2_TDF			((unsigned int) 0xF <<  8) /* (SMC2) Data Float Time */
-#define AT91C_SMC2_BAT			((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW			((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
-#define AT91C_SMC2_DBW_16		((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
-#define AT91C_SMC2_DBW_8		((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_DRP			((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
-#define AT91C_SMC2_ACSS			((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
-#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_ACSS_1_CYCLE		((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_2_CYCLES	((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_3_CYCLES	((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_RWSETUP		((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD		((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Power Management Controler         */
-/*****************************************************************************/
-typedef struct _AT91S_PMC
-{
-	AT91_REG	 PMC_SCER;	/* System Clock Enable Register */
-	AT91_REG	 PMC_SCDR;	/* System Clock Disable Register */
-	AT91_REG	 PMC_SCSR;	/* System Clock Status Register */
-	AT91_REG	 Reserved0[1];	/* */
-	AT91_REG	 PMC_PCER;	/* Peripheral Clock Enable Register */
-	AT91_REG	 PMC_PCDR;	/* Peripheral Clock Disable Register */
-	AT91_REG	 PMC_PCSR;	/* Peripheral Clock Status Register */
-	AT91_REG	 Reserved1[5];	/* */
-	AT91_REG	 PMC_MCKR;	/* Master Clock Register */
-	AT91_REG	 Reserved2[3];	/* */
-	AT91_REG	 PMC_PCKR[8];	/* Programmable Clock Register */
-	AT91_REG	 PMC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 PMC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 PMC_SR;	/* Status Register */
-	AT91_REG	 PMC_IMR;	/* Interrupt Mask Register */
-} AT91S_PMC, *AT91PS_PMC;
-
-/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
-#define AT91C_PMC_PCK		((unsigned int) 0x1 <<  0) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP		((unsigned int) 0x1 <<  1) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_MCKUDP	((unsigned int) 0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
-#define AT91C_PMC_UHP		((unsigned int) 0x1 <<  4) /* (PMC) USB Host Port Clock */
-#define AT91C_PMC_PCK0		((unsigned int) 0x1 <<  8) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1		((unsigned int) 0x1 <<  9) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2		((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3		((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK4		((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK5		((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK6		((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK7		((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
-/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
-/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
-/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
-#define AT91C_PMC_CSS		((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK	((unsigned int) 0x0)       /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK	((unsigned int) 0x1)       /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLLA_CLK	((unsigned int) 0x2)       /* (PMC) Clock from PLL A is selected */
-#define AT91C_PMC_CSS_PLLB_CLK	((unsigned int) 0x3)       /* (PMC) Clock from PLL B is selected */
-#define AT91C_PMC_PRES		((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK	((unsigned int) 0x0 <<  2) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2	((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4	((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8	((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16	((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32	((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64	((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64 */
-#define AT91C_PMC_MDIV		((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division */
-#define AT91C_PMC_MDIV_1	((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same */
-#define AT91C_PMC_MDIV_2	((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock */
-#define AT91C_PMC_MDIV_3	((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock */
-#define AT91C_PMC_MDIV_4	((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock */
-/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
-/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
-#define AT91C_PMC_MOSCS		((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKA		((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKB		((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY	((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY	((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY	((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY	((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY	((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK4RDY	((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK5RDY	((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK6RDY	((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK7RDY	((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
-/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
-/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
-/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Ethernet MAC                    */
-/*****************************************************************************/
-typedef struct _AT91S_EMAC
-{
-	AT91_REG	 EMAC_CTL;	/* Network Control Register */
-	AT91_REG	 EMAC_CFG;	/* Network Configuration Register */
-	AT91_REG	 EMAC_SR;	/* Network Status Register */
-	AT91_REG	 EMAC_TAR;	/* Transmit Address Register */
-	AT91_REG	 EMAC_TCR;	/* Transmit Control Register */
-	AT91_REG	 EMAC_TSR;	/* Transmit Status Register */
-	AT91_REG	 EMAC_RBQP;	/* Receive Buffer Queue Pointer */
-	AT91_REG	 Reserved0[1];	/*  */
-	AT91_REG	 EMAC_RSR;	/* Receive Status Register */
-	AT91_REG	 EMAC_ISR;	/* Interrupt Status Register */
-	AT91_REG	 EMAC_IER;	/* Interrupt Enable Register */
-	AT91_REG	 EMAC_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 EMAC_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 EMAC_MAN;	/* PHY Maintenance Register */
-	AT91_REG	 Reserved1[2];	/*  */
-	AT91_REG	 EMAC_FRA;	/* Frames Transmitted OK Register */
-	AT91_REG	 EMAC_SCOL;	/* Single Collision Frame Register */
-	AT91_REG	 EMAC_MCOL;	/* Multiple Collision Frame Register */
-	AT91_REG	 EMAC_OK;	/* Frames Received OK Register */
-	AT91_REG	 EMAC_SEQE;	/* Frame Check Sequence Error Register */
-	AT91_REG	 EMAC_ALE;	/* Alignment Error Register */
-	AT91_REG	 EMAC_DTE;	/* Deferred Transmission Frame Register */
-	AT91_REG	 EMAC_LCOL;	/* Late Collision Register */
-	AT91_REG	 EMAC_ECOL;	/* Excessive Collision Register */
-	AT91_REG	 EMAC_CSE;	/* Carrier Sense Error Register */
-	AT91_REG	 EMAC_TUE;	/* Transmit Underrun Error Register */
-	AT91_REG	 EMAC_CDE;	/* Code Error Register */
-	AT91_REG	 EMAC_ELR;	/* Excessive Length Error Register */
-	AT91_REG	 EMAC_RJB;	/* Receive Jabber Register */
-	AT91_REG	 EMAC_USF;	/* Undersize Frame Register */
-	AT91_REG	 EMAC_SQEE;	/* SQE Test Error Register */
-	AT91_REG	 EMAC_DRFC;	/* Discarded RX Frame Register */
-	AT91_REG	 Reserved2[3];	/*  */
-	AT91_REG	 EMAC_HSH;	/* Hash Address High[63:32] */
-	AT91_REG	 EMAC_HSL;	/* Hash Address Low[31:0] */
-	AT91_REG	 EMAC_SA1L;	/* Specific Address 1 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA1H;	/* Specific Address 1 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA2L;	/* Specific Address 2 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA2H;	/* Specific Address 2 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA3L;	/* Specific Address 3 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA3H;	/* Specific Address 3 High, Last 2 bytes */
-	AT91_REG	 EMAC_SA4L;	/* Specific Address 4 Low, First 4 bytes */
-	AT91_REG	 EMAC_SA4H;	/* Specific Address 4 High, Last 2 bytesr */
-} AT91S_EMAC, *AT91PS_EMAC;
-
-/* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
-#define AT91C_EMAC_LB		((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LBL		((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE		((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE		((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE		((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CSR		((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_ISR		((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WES		((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP		((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
-
-/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
-#define AT91C_EMAC_SPD		((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD		((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_BR		((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
-#define AT91C_EMAC_CAF		((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC		((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI		((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */
-#define AT91C_EMAC_UNI		((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG		((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE		((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK		((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8	((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16	((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32	((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64	((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY		((unsigned int) 0x1 << 12) /* (EMAC) */
-#define AT91C_EMAC_RMII		((unsigned int) 0x1 << 13) /* (EMAC) */
-
-/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
-#define AT91C_EMAC_MDIO		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_IDLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
-#define AT91C_EMAC_LEN		((unsigned int) 0x7FF <<  0) /* (EMAC) */
-#define AT91C_EMAC_NCRC		((unsigned int) 0x1 << 15) /* (EMAC) */
-
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
-#define AT91C_EMAC_OVR		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_COL		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TXIDLE	((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_BNQ		((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_COMP		((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_UND		((unsigned int) 0x1 <<  6) /* (EMAC) */
-
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_REC		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR	((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
-#define AT91C_EMAC_DONE		((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_RCOM		((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RBNA		((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TOVR		((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_TUND		((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_RTRY		((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_TBRE		((unsigned int) 0x1 <<  6) /* (EMAC) */
-#define AT91C_EMAC_TCOM		((unsigned int) 0x1 <<  7) /* (EMAC) */
-#define AT91C_EMAC_TIDLE	((unsigned int) 0x1 <<  8) /* (EMAC) */
-#define AT91C_EMAC_LINK		((unsigned int) 0x1 <<  9) /* (EMAC) */
-#define AT91C_EMAC_ROVR		((unsigned int) 0x1 << 10) /* (EMAC) */
-#define AT91C_EMAC_HRESP	((unsigned int) 0x1 << 11) /* (EMAC) */
-
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA		((unsigned int) 0xFFFF <<  0) /* (EMAC) */
-#define AT91C_EMAC_CODE		((unsigned int) 0x3  << 16) /* (EMAC) */
-#define AT91C_EMAC_CODE_802_3	((unsigned int) 0x2  << 16) /* (EMAC) Write Operation */
-#define AT91C_EMAC_REGA		((unsigned int) 0x1F << 18) /* (EMAC) */
-#define AT91C_EMAC_PHYA		((unsigned int) 0x1F << 23) /* (EMAC) */
-#define AT91C_EMAC_RW		((unsigned int) 0x3  << 28) /* (EMAC) */
-#define AT91C_EMAC_RW_R		((unsigned int) 0x2  << 28) /* (EMAC) Read Operation */
-#define AT91C_EMAC_RW_W		((unsigned int) 0x1  << 28) /* (EMAC) Write Operation */
-#define AT91C_EMAC_HIGH		((unsigned int) 0x1  << 30) /* (EMAC) */
-#define AT91C_EMAC_LOW		((unsigned int) 0x1  << 31) /* (EMAC) */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Serial Parallel Interface          */
-/*****************************************************************************/
-typedef struct _AT91S_SPI
-{
-	AT91_REG	 SPI_CR;	/* Control Register */
-	AT91_REG	 SPI_MR;	/* Mode Register */
-	AT91_REG	 SPI_RDR;	/* Receive Data Register */
-	AT91_REG	 SPI_TDR;	/* Transmit Data Register */
-	AT91_REG	 SPI_SR;	/* Status Register */
-	AT91_REG	 SPI_IER;	/* Interrupt Enable Register */
-	AT91_REG	 SPI_IDR;	/* Interrupt Disable Register */
-	AT91_REG	 SPI_IMR;	/* Interrupt Mask Register */
-	AT91_REG	 Reserved0[4];	/* */
-	AT91_REG	 SPI_CSR[4];	/* Chip Select Register */
-	AT91_REG	 Reserved1[48]; /* */
-	AT91_REG	 SPI_RPR;	/* Receive Pointer Register */
-	AT91_REG	 SPI_RCR;	/* Receive Counter Register */
-	AT91_REG	 SPI_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 SPI_TCR;	/* Transmit Counter Register */
-	AT91_REG	 SPI_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 SPI_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 SPI_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 SPI_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 SPI_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 SPI_PTSR;	/* PDC Transfer Status Register */
-} AT91S_SPI, *AT91PS_SPI;
-
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN		((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS	((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST		((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset */
-
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR		((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS		((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED	((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE	((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC	((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_DIV32		((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS	((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB		((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
-
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD		((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD		((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF		((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE		((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF		((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES		((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_SPENDRX	((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_SPENDTX	((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF	((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE	((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_SPIENS	((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
-
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL		((unsigned int) 0x1  <<  0) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA		((unsigned int) 0x1  <<  1) /* (SPI) Clock Phase */
-#define AT91C_SPI_BITS		((unsigned int) 0xF  <<  4) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8	((unsigned int) 0x0  <<  4) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9	((unsigned int) 0x1  <<  4) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10	((unsigned int) 0x2  <<  4) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11	((unsigned int) 0x3  <<  4) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12	((unsigned int) 0x4  <<  4) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13	((unsigned int) 0x5  <<  4) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14	((unsigned int) 0x6  <<  4) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15	((unsigned int) 0x7  <<  4) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16	((unsigned int) 0x8  <<  4) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR		((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS		((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Peripheral Data Controller         */
-/*****************************************************************************/
-typedef struct _AT91S_PDC
-{
-	AT91_REG	 PDC_RPR;	/* Receive Pointer Register */
-	AT91_REG	 PDC_RCR;	/* Receive Counter Register */
-	AT91_REG	 PDC_TPR;	/* Transmit Pointer Register */
-	AT91_REG	 PDC_TCR;	/* Transmit Counter Register */
-	AT91_REG	 PDC_RNPR;	/* Receive Next Pointer Register */
-	AT91_REG	 PDC_RNCR;	/* Receive Next Counter Register */
-	AT91_REG	 PDC_TNPR;	/* Transmit Next Pointer Register */
-	AT91_REG	 PDC_TNCR;	/* Transmit Next Counter Register */
-	AT91_REG	 PDC_PTCR;	/* PDC Transfer Control Register */
-	AT91_REG	 PDC_PTSR;	/* PDC Transfer Status Register */
-} AT91S_PDC, *AT91PS_PDC;
-
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN		((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS	((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN		((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS	((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  */
-
-/* ========== Register definition ==================================== */
-#define AT91C_SPI_CSR		((AT91_REG *)	0xFFFE0030) /* (SPI) Chip Select Register */
-#define AT91C_PMC_PCER		((AT91_REG *)	0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR		((AT91_REG *)	0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCER		((AT91_REG *)	0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCDR		((AT91_REG *)	0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PER		((AT91_REG *)	0xFFFFF400) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PDR		((AT91_REG *)	0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_PSR		((AT91_REG *)	0xFFFFF408) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER		((AT91_REG *)	0xFFFFF410) /* (PIOA) PIO Output Enable Register */
-#define AT91C_PIOA_ODR		((AT91_REG *)	0xFFFFF414) /* (PIOA) PIO Output Disable Register */
-#define AT91C_PIOA_OSR		((AT91_REG *)	0xFFFFF418) /* (PIOA) PIO Output Status Register */
-#define AT91C_PIOA_IFER		((AT91_REG *)	0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
-#define AT91C_PIOA_IFDR		((AT91_REG *)	0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
-#define AT91C_PIOA_IFSR		((AT91_REG *)	0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
-#define AT91C_PIOA_SODR		((AT91_REG *)	0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
-#define AT91C_PIOA_CODR		((AT91_REG *)	0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
-#define AT91C_PIOA_ODSR		((AT91_REG *)	0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
-#define AT91C_PIOA_PDSR		((AT91_REG *)	0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
-#define AT91C_PIOA_IER		((AT91_REG *)	0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
-#define AT91C_PIOA_IDR		((AT91_REG *)	0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
-#define AT91C_PIOA_IMR		((AT91_REG *)	0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
-#define AT91C_PIOA_ISR		((AT91_REG *)	0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
-#define AT91C_PIOA_MDER		((AT91_REG *)	0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
-#define AT91C_PIOA_MDDR		((AT91_REG *)	0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
-#define AT91C_PIOA_MDSR		((AT91_REG *)	0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
-#define AT91C_PIOA_PUDR		((AT91_REG *)	0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
-#define AT91C_PIOA_PUER		((AT91_REG *)	0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
-#define AT91C_PIOA_PUSR		((AT91_REG *)	0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
-#define AT91C_PIOA_ASR		((AT91_REG *)	0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
-#define AT91C_PIOA_BSR		((AT91_REG *)	0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
-#define AT91C_PIOA_ABSR		((AT91_REG *)	0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
-#define AT91C_PIOA_OWER		((AT91_REG *)	0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
-#define AT91C_PIOA_OWDR		((AT91_REG *)	0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
-#define AT91C_PIOA_OWSR		((AT91_REG *)	0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
-#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_PIO_PA30		((unsigned int) 1 << 30)	/* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0		((unsigned int) 1 <<  0)	/* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK		((unsigned int) AT91C_PIO_PC0)	/* Burst Flash Clock */
-#define AT91C_PA30_DRXD		((unsigned int) AT91C_PIO_PA30)	/* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31		((unsigned int) 1 << 31)	/* Pin Controlled by PA31 */
-#define AT91C_PA25_TWD		((unsigned int) 1 << 25)
-#define AT91C_PA26_TWCK		((unsigned int) 1 << 26)
-#define AT91C_PA31_DTXD		((unsigned int) AT91C_PIO_PA31)	/* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA17		((unsigned int) 1 << 17)	/* Pin Controlled by PA17 */
-#define AT91C_PA17_TXD0		AT91C_PIO_PA17			/* USART0 Transmit Data */
-#define AT91C_PIO_PA18		((unsigned int) 1 << 18)	/* Pin Controlled by PA18 */
-#define AT91C_PA18_RXD0		AT91C_PIO_PA18			/* USART0 Receive Data */
-#define AT91C_PIO_PB20		((unsigned int) 1 << 20)	/* Pin Controlled by PB20 */
-#define AT91C_PB20_RXD1		AT91C_PIO_PB20			/* USART1 Receive Data */
-#define AT91C_PIO_PB21		((unsigned int) 1 << 21)	/* Pin Controlled by PB21 */
-#define AT91C_PB21_TXD1		AT91C_PIO_PB21			/* USART1 Transmit Data */
-
-#define AT91C_ID_SYS		((unsigned int)  1) /* System Peripheral */
-#define AT91C_ID_PIOA		((unsigned int)  2) /* PIO port A */
-#define AT91C_ID_PIOB		((unsigned int)  3) /* PIO port B */
-#define AT91C_ID_PIOC		((unsigned int)  4) /* PIO port C */
-#define AT91C_ID_USART0		((unsigned int)  6) /* USART 0 */
-#define AT91C_ID_USART1		((unsigned int)  7) /* USART 1 */
-#define AT91C_ID_TWI		((unsigned int) 12) /* Two Wire Interface */
-#define AT91C_ID_SPI		((unsigned int) 13) /* Serial Peripheral Interface */
-#define AT91C_ID_TC0		((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_UHP		((unsigned int) 23) /* OHCI USB Host Port */
-#define AT91C_ID_EMAC		((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1		((unsigned int) 1 <<  1)	/* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE	((unsigned int) AT91C_PIO_PC1)	/*  Burst Flash Ready */
-#define AT91C_PIO_PC3		((unsigned int) 1 <<  3)	/* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE	((unsigned int) AT91C_PIO_PC3)	/*  Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2		((unsigned int) 1 <<  2)	/* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD		((unsigned int) AT91C_PIO_PC2)	/*  Burst Flash Address Valid */
-#define AT91C_PIO_PB1		((unsigned int) 1 <<  1)	/* Pin Controlled by PB1 */
-
-#define AT91C_PIO_PA23		((unsigned int) 1 << 23)	/* Pin Controlled by PA23 */
-#define AT91C_PA23_TXD2		((unsigned int) AT91C_PIO_PA23)	/* USART 2 Transmit Data */
-
-#define AT91C_PIO_PA0		((unsigned int) 1 <<  0)	/* Pin Controlled by PA0 */
-#define AT91C_PA0_MISO		((unsigned int) AT91C_PIO_PA0)	/* SPI Master In Slave */
-#define AT91C_PIO_PA1		((unsigned int) 1 <<  1)	/* Pin Controlled by PA1 */
-#define AT91C_PA1_MOSI		((unsigned int) AT91C_PIO_PA1)	/* SPI Master Out Slave */
-#define AT91C_PIO_PA2		((unsigned int) 1 <<  2)	/* Pin Controlled by PA2 */
-#define AT91C_PA2_SPCK		((unsigned int) AT91C_PIO_PA2)	/* SPI Serial Clock */
-#define AT91C_PIO_PA3		((unsigned int) 1 <<  3)	/* Pin Controlled by PA3 */
-#define AT91C_PA3_NPCS0		((unsigned int) AT91C_PIO_PA3)	/* SPI Peripheral Chip Select 0 */
-#define AT91C_PIO_PA4		((unsigned int) 1 <<  4)	/* Pin Controlled by PA4 */
-#define AT91C_PA4_NPCS1		((unsigned int) AT91C_PIO_PA4)	/* SPI Peripheral Chip Select 1 */
-#define AT91C_PIO_PA5		((unsigned int) 1 <<  5)	/* Pin Controlled by PA5 */
-#define AT91C_PA5_NPCS2		((unsigned int) AT91C_PIO_PA5)	/* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA6		((unsigned int) 1 <<  6)	/* Pin Controlled by PA6 */
-#define AT91C_PA6_NPCS3		((unsigned int) AT91C_PIO_PA6)	/* SPI Peripheral Chip Select 3 */
-
-#define AT91C_PIO_PA16		((unsigned int) 1 << 16)	/* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO	((unsigned int) AT91C_PIO_PA16)	/* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15		((unsigned int) 1 << 15)	/* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC		((unsigned int) AT91C_PIO_PA15)	/* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14		((unsigned int) 1 << 14)	/* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER	((unsigned int) AT91C_PIO_PA14)	/* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13		((unsigned int) 1 << 13)	/* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1		((unsigned int) AT91C_PIO_PA13)	/* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12		((unsigned int) 1 << 12)	/* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0		((unsigned int) AT91C_PIO_PA12)	/* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11		((unsigned int) 1 << 11)	/* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV	((unsigned int) AT91C_PIO_PA11)	/* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10		((unsigned int) 1 << 10)	/* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1		((unsigned int) AT91C_PIO_PA10)	/* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9		((unsigned int) 1 <<  9)	/* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0		((unsigned int) AT91C_PIO_PA9)	/* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8		((unsigned int) 1 <<  8)	/* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN		((unsigned int) AT91C_PIO_PA8)	/* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7		((unsigned int) 1 <<  7)	/* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK	((unsigned int) AT91C_PIO_PA7)	/* Ethernet MAC Transmit Clock/Reference Clock */
-
-#define AT91C_PIO_PB0		((unsigned int) 1 <<  0)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB1		((unsigned int) 1 <<  1)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB2		((unsigned int) 1 <<  2)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB3		((unsigned int) 1 <<  3)	/* Pin Controlled by PB3 */
-#define AT91C_PIO_PB4		((unsigned int) 1 <<  4)	/* Pin Controlled by PB4 */
-#define AT91C_PIO_PB5		((unsigned int) 1 <<  5)	/* Pin Controlled by PB5 */
-#define AT91C_PIO_PB6		((unsigned int) 1 <<  6)	/* Pin Controlled by PB6 */
-#define AT91C_PIO_PB7		((unsigned int) 1 <<  7)	/* Pin Controlled by PB7 */
-#define AT91C_PIO_PB22		((unsigned int) 1 << 22)	/* Pin Controlled by PB22 */
-#define AT91C_PIO_PB25		((unsigned int) 1 << 25)	/* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1		((unsigned int) AT91C_PIO_PB25)	/* USART 1 Data Set ready */
-#define AT91C_PB25_EF100	((unsigned int) AT91C_PIO_PB25)	/* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19		((unsigned int) 1 << 19)	/* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1		((unsigned int) AT91C_PIO_PB19)	/* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK	((unsigned int) AT91C_PIO_PB19)	/* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18		((unsigned int) 1 << 18)	/* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1		((unsigned int) AT91C_PIO_PB18)	/* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL		((unsigned int) AT91C_PIO_PB18)	/* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17		((unsigned int) 1 << 17)	/* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2		((unsigned int) AT91C_PIO_PB17)	/* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV	((unsigned int) AT91C_PIO_PB17)	/* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16		((unsigned int) 1 << 16)	/* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2		((unsigned int) AT91C_PIO_PB16)	/* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3		((unsigned int) AT91C_PIO_PB16)	/* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15		((unsigned int) 1 << 15)	/* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2		((unsigned int) AT91C_PIO_PB15)	/* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2		((unsigned int) AT91C_PIO_PB15)	/* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14		((unsigned int) 1 << 14)	/* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2		((unsigned int) AT91C_PIO_PB14)	/* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER	((unsigned int) AT91C_PIO_PB14)	/* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13		((unsigned int) 1 << 13)	/* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2		((unsigned int) AT91C_PIO_PB13)	/* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3		((unsigned int) AT91C_PIO_PB13)	/* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12		((unsigned int) 1 << 12)	/* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2		((unsigned int) AT91C_PIO_PB12)	/* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2		((unsigned int) AT91C_PIO_PB12)	/* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR		((AT91_REG *)	0xFFFFF674)	/* (PIOB) Select B Register */
-#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604)	/* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia	((unsigned int) 0x1 <<  3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8	((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN		((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR		((AT91_REG *)	0xFFFFF870) /* (PIOC) Select A Register */
-#define AT91C_PIOC_SODR		((AT91_REG *)	0xFFFFF830) /* (PIOC) Set Output Data Register */
-#define AT91C_PIOC_CODR		((AT91_REG *)	0xFFFFF834) /* (PIOC) Clear Output Data Register */
-#define AT91C_PIOC_PDSR		((AT91_REG *)	0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-
-#define AT91C_BASE_AIC		((AT91PS_AIC)	0xFFFFF000) /* (AIC) Base Address */
-#define AT91C_BASE_DBGU		((AT91PS_DBGU)	0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA		((AT91PS_PIO)	0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB		((AT91PS_PIO)	0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOC		((AT91PS_PIO)	0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOD		((AT91PS_PIO)	0xFFFFFA00) /* (PIOC) Base Address */
-#define AT91C_BASE_PMC		((AT91PS_PMC)	0xFFFFFC00) /* (PMC) Base Address */
-#if	0
-#define AT91C_BASE_ST		((AT91PS_ST)	0xFFFFFD00) /* (PMC) Base Address */
-#define AT91C_BASE_RTC		((AT91PS_RTC)	0xFFFFFE00) /* (PMC) Base Address */
-#define AT91C_BASE_MC		((AT91PS_MC)	0xFFFFFF00) /* (PMC) Base Address */
-#endif
-
-#define AT91C_BASE_TC0		((AT91PS_TC)	0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_TC1		((AT91PS_TC)	0xFFFA4000) /* (TC0) Base Address */
-#if	0
-#define AT91C_BASE_UDP		((AT91PS_UDP)	0xFFFB0000) /* (TC0) Base Address */
-#define AT91C_BASE_MCI		((AT91PS_MCI)	0xFFFB4000) /* (TC0) Base Address */
-#define AT91C_BASE_TWI		((AT91PS_TWI)	0xFFFB8000) /* (TC0) Base Address */
-#endif
-#define AT91C_BASE_EMAC		((AT91PS_EMAC)	0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_BASE_US0		((AT91PS_USART)	0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1		((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_BASE_US2		((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
-#define AT91C_BASE_US3		((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
-#define AT91C_BASE_SPI		((AT91PS_SPI)	0xFFFE0000) /* (SPI) Base Address */
-
-#define AT91C_BASE_CKGR		((AT91PS_CKGR)	0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_EBI_CSA		((AT91_REG *)	0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2		((AT91PS_SMC2)	0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_TCB0_BMR		((AT91_REG *)	0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR		((AT91_REG *)	0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR		((AT91_REG *)	0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER		((AT91_REG *)	0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR		((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
-
-#else
-/* flash */
-#define AT91C_MC_PUIA		0xFFFFFF10
-#define AT91C_MC_PUP		0xFFFFFF50
-#define AT91C_MC_PUER		0xFFFFFF54
-#define AT91C_MC_ASR		0xFFFFFF04
-#define AT91C_MC_AASR		0xFFFFFF08
-#define AT91C_EBI_CFGR		0xFFFFFF64
-#define AT91C_SMC_CSR0		0xFFFFFF70
-
-/* clocks */
-#define AT91C_PLLAR		0xFFFFFC28
-#define AT91C_PLLBR		0xFFFFFC2C
-#define AT91C_MCKR		0xFFFFFC30
-
-#define AT91C_BASE_CKGR		0xFFFFFC20
-#define AT91C_CKGR_MOR		0
-
-/* sdram */
-#define AT91C_PIOC_ASR		0xFFFFF870
-#define AT91C_PIOC_BSR		0xFFFFF874
-#define AT91C_PIOC_PDR		0xFFFFF804
-#define AT91C_EBI_CSA		0xFFFFFF60
-#define AT91C_SDRC_CR		0xFFFFFF98
-#define AT91C_SDRC_MR		0xFFFFFF90
-#define AT91C_SDRC_TR		0xFFFFFF94
-
-#endif /* __ASSEMBLY__ */
-#endif /* AT91RM9200_H */
diff --git a/arch/arm/include/asm/arch-at91rm9200/hardware.h b/arch/arm/include/asm/arch-at91rm9200/hardware.h
deleted file mode 100644
index b868e38..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/hardware.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-at91/hardware.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#include "AT91RM9200.h"
-#endif
-
-/* Virtual and Physical base address for system peripherals */
-#define AT91_SYS_BASE		0xFFFFF000 /*4K */
-
-/* Virtual and Physical base addresses of user peripherals */
-#define AT91_SPI_BASE		0xFFFE0000 /*16K */
-#define AT91_SSC2_BASE		0xFFFD8000 /*16K */
-#define AT91_SSC1_BASE		0xFFFD4000 /*16K */
-#define AT91_SSC0_BASE		0xFFFD0000 /*16K */
-#define AT91_USART3_BASE	0xFFFCC000 /*16K */
-#define AT91_USART2_BASE	0xFFFC8000 /*16K */
-#define AT91_USART1_BASE	0xFFFC4000 /*16K */
-#define AT91_USART0_BASE	0xFFFC0000 /*16K */
-#define AT91_EMAC_BASE		0xFFFBC000 /*16K */
-#define AT91_TWI_BASE		0xFFFB8000 /*16K */
-#define AT91_MCI_BASE		0xFFFB4000 /*16K */
-#define AT91_UDP_BASE		0xFFFB0000 /*16K */
-#define AT91_TCB1_BASE		0xFFFA4000 /*16K */
-#define AT91_TCB0_BASE		0xFFFA0000 /*16K */
-
-#define AT91_USB_HOST_BASE	0x00300000
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define AT91_IO_BASE		0xF0000000	/* Virt/Phys Address of IO */
-
-/* FLASH */
-#define AT91_FLASH_BASE		0x10000000	/* NCS0 */
-
-/* SDRAM */
-#define AT91_SDRAM_BASE		0x20000000	/* NCS1 */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE	0x40000000	/* NCS3 */
-
-/* Definition of interrupt priority levels */
-#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
-#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
-#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
-#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
-#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
-#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
-#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
-#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h
index 347aa89..211b769 100644
--- a/arch/arm/include/asm/arch-davinci/davinci_misc.h
+++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h
@@ -57,7 +57,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
 int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
 int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
 				    int n_items);
-#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
 void davinci_emac_mii_mode_sel(int mode_sel);
 #endif
 #if defined(CONFIG_SOC_DA8XX)
diff --git a/arch/arm/include/asm/arch-davinci/gpio_defs.h b/arch/arm/include/asm/arch-davinci/gpio.h
index 1be2ac2..29dcccf 100644
--- a/arch/arm/include/asm/arch-davinci/gpio_defs.h
+++ b/arch/arm/include/asm/arch-davinci/gpio.h
@@ -63,4 +63,12 @@ struct davinci_gpio_bank {
 #define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
 #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
 
+#define gpio_status()		gpio_info()
+#define GPIO_NAME_SIZE		20
+#define MAX_NUM_GPIOS		144
+#define GPIO_BANK(gp)		(davinci_gpio_bank01 + ((gp) >> 5))
+#define GPIO_BIT(gp)		((gp) & 0x1F)
+
+void gpio_info(void);
+
 #endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index df3f549..f537c4b 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -140,6 +140,8 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
 #define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
 #define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
+#define DAVINCI_MMC_SD0_BASE			0x01c40000
+#define DAVINCI_MMC_SD1_BASE			0x01e1b000
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
@@ -213,47 +215,65 @@ typedef volatile unsigned int *	dv_reg_p;
 
 #else /* CONFIG_SOC_DA8XX */
 
-enum davinci_lpsc_ids {
-	DAVINCI_LPSC_TPCC = 0,
-	DAVINCI_LPSC_TPTC0,
-	DAVINCI_LPSC_TPTC1,
-	DAVINCI_LPSC_AEMIF,
-	DAVINCI_LPSC_SPI0,
-	DAVINCI_LPSC_MMC_SD,
-	DAVINCI_LPSC_AINTC,
-	DAVINCI_LPSC_ARM_RAM_ROM,
-	DAVINCI_LPSC_SECCTL_KEYMGR,
-	DAVINCI_LPSC_UART0,
-	DAVINCI_LPSC_SCR0,
-	DAVINCI_LPSC_SCR1,
-	DAVINCI_LPSC_SCR2,
-	DAVINCI_LPSC_DMAX,
-	DAVINCI_LPSC_ARM,
-	DAVINCI_LPSC_GEM,
-	/* for LPSCs in PSC1, offset from 32 for differentiation */
-	DAVINCI_LPSC_PSC1_BASE = 32,
-	DAVINCI_LPSC_USB11,
-	DAVINCI_LPSC_USB20,
-	DAVINCI_LPSC_GPIO,
-	DAVINCI_LPSC_UHPI,
-	DAVINCI_LPSC_EMAC,
-	DAVINCI_LPSC_DDR_EMIF,
-	DAVINCI_LPSC_McASP0,
-	DAVINCI_LPSC_McASP1,
-	DAVINCI_LPSC_McASP2,
-	DAVINCI_LPSC_SPI1,
-	DAVINCI_LPSC_I2C1,
-	DAVINCI_LPSC_UART1,
-	DAVINCI_LPSC_UART2,
-	DAVINCI_LPSC_LCDC,
-	DAVINCI_LPSC_ePWM,
-	DAVINCI_LPSC_eCAP,
-	DAVINCI_LPSC_eQEP,
-	DAVINCI_LPSC_SCR_P0,
-	DAVINCI_LPSC_SCR_P1,
-	DAVINCI_LPSC_CR_P3,
-	DAVINCI_LPSC_L3_CBA_RAM
-};
+#define DAVINCI_LPSC_TPCC		0
+#define DAVINCI_LPSC_TPTC0		1
+#define DAVINCI_LPSC_TPTC1		2
+#define DAVINCI_LPSC_AEMIF		3
+#define DAVINCI_LPSC_SPI0		4
+#define DAVINCI_LPSC_MMC_SD		5
+#define DAVINCI_LPSC_AINTC		6
+#define DAVINCI_LPSC_ARM_RAM_ROM	7
+#define DAVINCI_LPSC_SECCTL_KEYMGR	8
+#define DAVINCI_LPSC_UART0		9
+#define DAVINCI_LPSC_SCR0		10
+#define DAVINCI_LPSC_SCR1		11
+#define DAVINCI_LPSC_SCR2		12
+#define DAVINCI_LPSC_DMAX		13
+#define DAVINCI_LPSC_ARM		14
+#define DAVINCI_LPSC_GEM		15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE		32
+#define DAVINCI_LPSC_USB20		(DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB11		(DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO		(DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI		(DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC		(DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF		(DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0		(DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_SPI1		(DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1		(DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1		(DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2		(DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC		(DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_ePWM		(DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_eCAP		(DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM		(DAVINCI_LPSC_PSC1_BASE + 31)
+
+/* DA830-specific peripherals */
+#define DAVINCI_LPSC_McASP1		(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2		(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_eQEP		(DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR8		(DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR7		(DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR12		(DAVINCI_LPSC_PSC1_BASE + 26)
+
+/* DA850-specific peripherals */
+#define DAVINCI_LPSC_TPCC1		(DAVINCI_LPSC_PSC1_BASE + 0)
+#define DAVINCI_LPSC_SATA		(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_VPIF		(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_McBSP0		(DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_McBSP1		(DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_MMC_SD1		(DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_uPP		(DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_TPTC2		(DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR_F0		(DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR_F1		(DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR_F2		(DAVINCI_LPSC_PSC1_BASE + 26)
+#define DAVINCI_LPSC_SCR_F6		(DAVINCI_LPSC_PSC1_BASE + 27)
+#define DAVINCI_LPSC_SCR_F7		(DAVINCI_LPSC_PSC1_BASE + 28)
+#define DAVINCI_LPSC_SCR_F8		(DAVINCI_LPSC_PSC1_BASE + 29)
+#define DAVINCI_LPSC_BR_F7		(DAVINCI_LPSC_PSC1_BASE + 30)
 
 #endif /* CONFIG_SOC_DA8XX */
 
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 0104418..3c843a0 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -50,6 +50,7 @@
 #define KW_MPP_BASE			(KW_REGISTER(0x10000))
 #define KW_GPIO0_BASE			(KW_REGISTER(0x10100))
 #define KW_GPIO1_BASE			(KW_REGISTER(0x10140))
+#define KW_RTC_BASE			(KW_REGISTER(0x10300))
 #define KW_NANDF_BASE			(KW_REGISTER(0x10418))
 #define KW_SPI_BASE			(KW_REGISTER(0x10600))
 #define KW_CPU_WIN_BASE			(KW_REGISTER(0x20000))
diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
deleted file mode 100644
index 0bc5279..0000000
--- a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef ASM_OFFSETS_H
-#define ASM_OFFSETS_H
-
-/*
- * Offset definitions for DDR controller
- */
-#define DDR2_DRIC		0x00
-#define DDR2_DRIC1		0x02
-#define DDR2_DRIC2		0x04
-#define DDR2_DRCA		0x06
-#define DDR2_DRCM		0x08
-#define DDR2_DRCST1		0x0a
-#define DDR2_DRCST2		0x0c
-#define DDR2_DRCR		0x0e
-#define DDR2_DRCF		0x20
-#define DDR2_DRASR		0x30
-#define DDR2_DRIMS		0x50
-#define DDR2_DROS		0x60
-#define DDR2_DRIBSODT1		0x64
-#define DDR2_DROABA		0x70
-#define DDR2_DROBS		0x84
-
-/*
- * Offset definitions Chip Control Module
- */
-#define CCNT_CDCRC		0xec
-
-/*
- * Offset definitions clock reset generator
- */
-#define CRG_CRPR		0x00
-#define CRG_CRHA		0x18
-#define CRG_CRPA		0x1c
-#define CRG_CRPB		0x20
-#define CRG_CRHB		0x24
-#define CRG_CRAM		0x28
-
-/*
- * Offset definitions External bus interface
- */
-#define MEMC_MCFMODE0		0x00
-#define MEMC_MCFMODE2		0x08
-#define MEMC_MCFMODE4		0x10
-#define MEMC_MCFTIM0		0x20
-#define MEMC_MCFTIM2		0x28
-#define MEMC_MCFTIM4		0x30
-#define MEMC_MCFAREA0		0x40
-#define MEMC_MCFAREA2		0x48
-#define MEMC_MCFAREA4		0x50
-
-#endif /* ASM_OFFSETS_H */
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
index 36a28b7..cb9eee5 100644
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
@@ -498,6 +498,48 @@ struct mb86r0x_gdc {
 	uint32_t pad08[7*1024];
 };
 
+/* mb86r0x ddr2c */
+struct mb86r0x_ddr2c {
+	uint16_t dric;
+	uint16_t dric1;
+	uint16_t dric2;
+	uint16_t drca;
+	uint16_t drcm;
+	uint16_t drcst1;
+	uint16_t drcst2;
+	uint16_t drcr;
+	uint16_t pad00[8];
+	uint16_t drcf;
+	uint16_t pad01[7];
+	uint16_t drasr;
+	uint16_t pad02[15];
+	uint16_t drims;
+	uint16_t pad03[7];
+	uint16_t dros;
+	uint16_t pad04;
+	uint16_t dribsodt1;
+	uint16_t dribsocd;
+	uint16_t dribsocd2;
+	uint16_t pad05[3];
+	uint16_t droaba;
+	uint16_t pad06[9];
+	uint16_t drobs;
+	uint16_t pad07[5];
+	uint16_t drimr1;
+	uint16_t drimr2;
+	uint16_t drimr3;
+	uint16_t drimr4;
+	uint16_t droisr1;
+	uint16_t droisr2;
+};
+
+/* mb86r0x memc */
+struct mb86r0x_memc {
+	uint32_t mcfmode[8];
+	uint32_t mcftim[8];
+	uint32_t mcfarea[8];
+};
+
 #endif /* __ASSEMBLY__ */
 
 /*
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index e944de7..08a725d 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -498,4 +498,30 @@ struct pm {
 /* MUSB base */
 #define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
new file mode 100644
index 0000000..374e064
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -0,0 +1,690 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+#define CM_CLKMODE_DPLL_CORE		0x4A004120
+#define CM_CLKMODE_DPLL_PER		0x4A008140
+#define CM_CLKMODE_DPLL_MPU		0x4A004160
+#define CM_CLKSEL_CORE			0x4A004100
+
+struct omap4_prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 pad001[1];
+	u32 cm_clksel_abe;
+	u32 pad002[1];
+	u32 cm_dll_ctrl;
+	u32 pad003[3];
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 pad004[3];
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 pad005[5];
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 pad006[3];
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 pad007[2];
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 pad008[2];
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 pad009[3];
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 pad010[4];
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 pad011[4];
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 pad012[1];
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 pad013[1];
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 pad014[5];
+	u32 cm_shadow_freq_config1;
+	u32 pad0141[47];
+	u32 cm_mpu_mpu_clkctrl;
+
+	/* cm1.dsp */
+	u32 pad015[55];
+	u32 cm_dsp_clkstctrl;
+	u32 pad016[7];
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 pad017[55];
+	u32 cm1_abe_clkstctrl;
+	u32 pad018[7];
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 pad019[1];
+	u32 cm1_abe_aess_clkctrl;
+	u32 pad020[1];
+	u32 cm1_abe_pdm_clkctrl;
+	u32 pad021[1];
+	u32 cm1_abe_dmic_clkctrl;
+	u32 pad022[1];
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 pad023[1];
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 pad024[1];
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 pad025[1];
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 pad026[1];
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 pad027[1];
+	u32 cm1_abe_timer5_clkctrl;
+	u32 pad028[1];
+	u32 cm1_abe_timer6_clkctrl;
+	u32 pad029[1];
+	u32 cm1_abe_timer7_clkctrl;
+	u32 pad030[1];
+	u32 cm1_abe_timer8_clkctrl;
+	u32 pad031[1];
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 pad032[3805];
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 pad033[1];
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 pad034[1];
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 pad035[1];
+	u32 cm_iva_dvfs_current;
+	u32 pad036[1];
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 pad037[3];
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 pad038[5];
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 pad039[1];
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 pad040[2];
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 pad041[5];
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+	/* cm2.core */
+	u32 pad0411[324];
+	u32 cm_l3_1_clkstctrl;
+	u32 pad042[1];
+	u32 cm_l3_1_dynamicdep;
+	u32 pad043[5];
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 pad044[55];
+	u32 cm_l3_2_clkstctrl;
+	u32 pad045[1];
+	u32 cm_l3_2_dynamicdep;
+	u32 pad046[5];
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 pad047[1];
+	u32 cm_l3_2_gpmc_clkctrl;
+	u32 pad048[1];
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 pad049[51];
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 pad050[5];
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 pad051[55];
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 pad052[5];
+	u32 cm_sdma_sdma_clkctrl;
+	u32 pad053[55];
+	u32 cm_memif_clkstctrl;
+	u32 pad054[7];
+	u32 cm_memif_dmm_clkctrl;
+	u32 pad055[1];
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 pad056[1];
+	u32 cm_memif_emif_1_clkctrl;
+	u32 pad057[1];
+	u32 cm_memif_emif_2_clkctrl;
+	u32 pad058[1];
+	u32 cm_memif_dll_clkctrl;
+	u32 pad059[3];
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 pad060[1];
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 pad061[1];
+	u32 cm_memif_dll_h_clkctrl;
+	u32 pad062[39];
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 pad063[5];
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 pad064[1];
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 pad065[1];
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 pad066[51];
+	u32 cm_l4cfg_clkstctrl;
+	u32 pad067[1];
+	u32 cm_l4cfg_dynamicdep;
+	u32 pad068[5];
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 pad069[1];
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 pad070[1];
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 pad071[1];
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 pad072[49];
+	u32 cm_l3instr_clkstctrl;
+	u32 pad073[7];
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 pad074[1];
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 pad075[5];
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+
+	/* cm2.ivahd */
+	u32 pad076[47];
+	u32 cm_ivahd_clkstctrl;
+	u32 pad077[7];
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 pad078[1];
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 pad079[53];
+	u32 cm_cam_clkstctrl;
+	u32 pad080[7];
+	u32 cm_cam_iss_clkctrl;
+	u32 pad081[1];
+	u32 cm_cam_fdif_clkctrl;
+
+	/* cm2.dss */
+	u32 pad082[53];
+	u32 cm_dss_clkstctrl;
+	u32 pad083[7];
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 pad084[55];
+	u32 cm_sgx_clkstctrl;
+	u32 pad085[7];
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 pad086[55];
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 pad087[9];
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 pad088[1];
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 pad089[1];
+	u32 cm_l3init_hsi_clkctrl;
+	u32 pad090[7];
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 pad091[1];
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 pad092[1];
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 pad093[3];
+	u32 cm_l3init_p1500_clkctrl;
+	u32 pad094[21];
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 pad095[3];
+	u32 cm_l3init_usbphy_clkctrl;
+
+	/* cm2.l4per */
+	u32 pad096[7];
+	u32 cm_l4per_clkstctrl;
+	u32 pad097[1];
+	u32 cm_l4per_dynamicdep;
+	u32 pad098[5];
+	u32 cm_l4per_adc_clkctrl;
+	u32 pad100[1];
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 pad101[1];
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 pad102[1];
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 pad103[1];
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 pad104[1];
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 pad105[1];
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 pad106[1];
+	u32 cm_l4per_elm_clkctrl;
+	u32 pad107[1];
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 pad108[1];
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 pad109[1];
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 pad110[1];
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 pad111[1];
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 pad112[1];
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 pad113[1];
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 pad114[1];
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 pad115[1];
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 pad116[1];
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 pad117[1];
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 pad118[1];
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 pad119[1];
+	u32 cm_l4per_l4per_clkctrl;
+	u32 pad1191[3];
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 pad120[1];
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 pad121[1];
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 pad122[1];
+	u32 cm_l4per_mgate_clkctrl;
+	u32 pad123[1];
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 pad124[1];
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 pad125[1];
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 pad126[1];
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 pad127[5];
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 pad128[1];
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 pad129[1];
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 pad130[1];
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 pad131[1];
+	u32 cm_l4per_uart1_clkctrl;
+	u32 pad132[1];
+	u32 cm_l4per_uart2_clkctrl;
+	u32 pad133[1];
+	u32 cm_l4per_uart3_clkctrl;
+	u32 pad134[1];
+	u32 cm_l4per_uart4_clkctrl;
+	u32 pad135[1];
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 pad136[1];
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 pad137[5];
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 pad138[5];
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 pad139[1];
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 pad140[1];
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 pad141[1];
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 pad142[1];
+	u32 cm_l4sec_rng_clkctrl;
+	u32 pad143[1];
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 pad144[3];
+	u32 cm_l4sec_cryptodma_clkctrl;
+	u32 pad145[776841];
+
+	/* l4 wkup regs */
+	u32 pad201[6211];
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 pad202[1467];
+	u32 cm_wkup_clkstctrl;
+	u32 pad203[7];
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 pad204;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 pad205;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 pad206;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 pad207;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 pad208;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 pad209;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 pad210;
+	u32 cm_wkup_usim_clkctrl;
+	u32 pad211;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 pad212[5];
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 pad213;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 pad214;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 pad215[197];
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_channel;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL		0
+#define CM_IDLEST_DPLL		0x4
+#define CM_AUTOIDLE_DPLL	0x8
+#define CM_CLKSEL_DPLL		0xC
+#define CM_DIV_M2_DPLL		0x10
+#define CM_DIV_M3_DPLL		0x14
+#define CM_DIV_M4_DPLL		0x18
+#define CM_DIV_M5_DPLL		0x1C
+#define CM_DIV_M6_DPLL		0x20
+#define CM_DIV_M7_DPLL		0x24
+
+#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
+
+#define OMAP4_DPLL_MAX_N	127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+#define OMAP_32K_CLK_FREQ		32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#define NUM_SYS_CLKS	7
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+	u32 cm_div_m7_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+	u32 m;
+	u32 n;
+	u8 m2;
+	u8 m3;
+	u8 m4;
+	u8 m5;
+	u8 m6;
+	u8 m7;
+};
+
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 7d5748a..08b9c99 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -142,4 +142,30 @@ struct watchdog {
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
new file mode 100644
index 0000000..37ad1fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -0,0 +1,1040 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+
+/* Base address */
+#define OMAP44XX_EMIF1				0x4c000000
+#define OMAP44XX_EMIF2				0x4d000000
+
+/* Registers shifts and masks */
+
+/* EMIF_MOD_ID_REV */
+#define OMAP44XX_REG_SCHEME_SHIFT			30
+#define OMAP44XX_REG_SCHEME_MASK			(0x3 << 30)
+#define OMAP44XX_REG_MODULE_ID_SHIFT			16
+#define OMAP44XX_REG_MODULE_ID_MASK			(0xfff << 16)
+#define OMAP44XX_REG_RTL_VERSION_SHIFT			11
+#define OMAP44XX_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define OMAP44XX_REG_MAJOR_REVISION_SHIFT		8
+#define OMAP44XX_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define OMAP44XX_REG_MINOR_REVISION_SHIFT		0
+#define OMAP44XX_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define OMAP44XX_REG_BE_SHIFT				31
+#define OMAP44XX_REG_BE_MASK				(1 << 31)
+#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT		30
+#define OMAP44XX_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define OMAP44XX_REG_FAST_INIT_SHIFT			29
+#define OMAP44XX_REG_FAST_INIT_MASK			(1 << 29)
+#define OMAP44XX_REG_PHY_DLL_READY_SHIFT		2
+#define OMAP44XX_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define OMAP44XX_REG_SDRAM_TYPE_SHIFT			29
+#define OMAP44XX_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define OMAP44XX_REG_IBANK_POS_SHIFT			27
+#define OMAP44XX_REG_IBANK_POS_MASK			(0x3 << 27)
+#define OMAP44XX_REG_DDR_TERM_SHIFT			24
+#define OMAP44XX_REG_DDR_TERM_MASK			(0x7 << 24)
+#define OMAP44XX_REG_DDR2_DDQS_SHIFT			23
+#define OMAP44XX_REG_DDR2_DDQS_MASK			(1 << 23)
+#define OMAP44XX_REG_DYN_ODT_SHIFT			21
+#define OMAP44XX_REG_DYN_ODT_MASK			(0x3 << 21)
+#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT		20
+#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT			18
+#define OMAP44XX_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define OMAP44XX_REG_CWL_SHIFT				16
+#define OMAP44XX_REG_CWL_MASK				(0x3 << 16)
+#define OMAP44XX_REG_NARROW_MODE_SHIFT			14
+#define OMAP44XX_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_CL_SHIFT				10
+#define OMAP44XX_REG_CL_MASK				(0xf << 10)
+#define OMAP44XX_REG_ROWSIZE_SHIFT			7
+#define OMAP44XX_REG_ROWSIZE_MASK			(0x7 << 7)
+#define OMAP44XX_REG_IBANK_SHIFT			4
+#define OMAP44XX_REG_IBANK_MASK				(0x7 << 4)
+#define OMAP44XX_REG_EBANK_SHIFT			3
+#define OMAP44XX_REG_EBANK_MASK				(1 << 3)
+#define OMAP44XX_REG_PAGESIZE_SHIFT			0
+#define OMAP44XX_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define OMAP44XX_REG_CS1NVMEN_SHIFT			30
+#define OMAP44XX_REG_CS1NVMEN_MASK			(1 << 30)
+#define OMAP44XX_REG_EBANK_POS_SHIFT			27
+#define OMAP44XX_REG_EBANK_POS_MASK			(1 << 27)
+#define OMAP44XX_REG_RDBNUM_SHIFT			4
+#define OMAP44XX_REG_RDBNUM_MASK			(0x3 << 4)
+#define OMAP44XX_REG_RDBSIZE_SHIFT			0
+#define OMAP44XX_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define OMAP44XX_REG_INITREF_DIS_SHIFT			31
+#define OMAP44XX_REG_INITREF_DIS_MASK			(1 << 31)
+#define OMAP44XX_REG_SRT_SHIFT				29
+#define OMAP44XX_REG_SRT_MASK				(1 << 29)
+#define OMAP44XX_REG_ASR_SHIFT				28
+#define OMAP44XX_REG_ASR_MASK				(1 << 28)
+#define OMAP44XX_REG_PASR_SHIFT				24
+#define OMAP44XX_REG_PASR_MASK				(0x7 << 24)
+#define OMAP44XX_REG_REFRESH_RATE_SHIFT			0
+#define OMAP44XX_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define OMAP44XX_REG_T_RP_SHIFT				25
+#define OMAP44XX_REG_T_RP_MASK				(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHIFT			21
+#define OMAP44XX_REG_T_RCD_MASK				(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHIFT				17
+#define OMAP44XX_REG_T_WR_MASK				(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHIFT			12
+#define OMAP44XX_REG_T_RAS_MASK				(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHIFT				6
+#define OMAP44XX_REG_T_RC_MASK				(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHIFT			3
+#define OMAP44XX_REG_T_RRD_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHIFT			0
+#define OMAP44XX_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define OMAP44XX_REG_T_RP_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define OMAP44XX_REG_T_RCD_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define OMAP44XX_REG_T_WR_SHDW_SHIFT			17
+#define OMAP44XX_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define OMAP44XX_REG_T_RAS_SHDW_SHIFT			12
+#define OMAP44XX_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define OMAP44XX_REG_T_RC_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define OMAP44XX_REG_T_RRD_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_WTR_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define OMAP44XX_REG_T_XP_SHIFT				28
+#define OMAP44XX_REG_T_XP_MASK				(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHIFT			25
+#define OMAP44XX_REG_T_ODT_MASK				(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHIFT			3
+#define OMAP44XX_REG_T_RTP_MASK				(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHIFT			0
+#define OMAP44XX_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define OMAP44XX_REG_T_XP_SHDW_SHIFT			28
+#define OMAP44XX_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_T_ODT_SHDW_SHIFT			25
+#define OMAP44XX_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT			16
+#define OMAP44XX_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT			6
+#define OMAP44XX_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define OMAP44XX_REG_T_RTP_SHDW_SHIFT			3
+#define OMAP44XX_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define OMAP44XX_REG_T_CKE_SHDW_SHIFT			0
+#define OMAP44XX_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define OMAP44XX_REG_T_CKESR_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT			13
+#define OMAP44XX_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHIFT			4
+#define OMAP44XX_REG_T_RFC_MASK				(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHIFT			0
+#define OMAP44XX_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT			21
+#define OMAP44XX_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define OMAP44XX_REG_T_RFC_SHDW_SHIFT			4
+#define OMAP44XX_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define OMAP44XX_REG_NVM_T_XP_SHIFT			28
+#define OMAP44XX_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHIFT			24
+#define OMAP44XX_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHIFT			20
+#define OMAP44XX_REG_NVM_T_RP_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHIFT			16
+#define OMAP44XX_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHIFT			8
+#define OMAP44XX_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT			0
+#define OMAP44XX_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT		28
+#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT		20
+#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define OMAP44XX_REG_IDLEMODE_SHIFT			30
+#define OMAP44XX_REG_IDLEMODE_MASK			(0x3 << 30)
+#define OMAP44XX_REG_PD_TIM_SHIFT			12
+#define OMAP44XX_REG_PD_TIM_MASK			(0xf << 12)
+#define OMAP44XX_REG_DPD_EN_SHIFT			11
+#define OMAP44XX_REG_DPD_EN_MASK			(1 << 11)
+#define OMAP44XX_REG_LP_MODE_SHIFT			8
+#define OMAP44XX_REG_LP_MODE_MASK			(0x7 << 8)
+#define OMAP44XX_REG_SR_TIM_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT			8
+#define OMAP44XX_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT			4
+#define OMAP44XX_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT			0
+#define OMAP44XX_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define OMAP44XX_REG_VALUE_0_SHIFT			0
+#define OMAP44XX_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define OMAP44XX_REG_CS_SHIFT				31
+#define OMAP44XX_REG_CS_MASK				(1 << 31)
+#define OMAP44XX_REG_REFRESH_EN_SHIFT			30
+#define OMAP44XX_REG_REFRESH_EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ADDRESS_SHIFT			0
+#define OMAP44XX_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
+#define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT		20
+#define OMAP44XX_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
+#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
+#define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0
+#define OMAP44XX_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT		30
+#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT			28
+#define OMAP44XX_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define OMAP44XX_REG_TLEC_SHIFT				16
+#define OMAP44XX_REG_TLEC_MASK				(0xffff << 16)
+#define OMAP44XX_REG_MT_SHIFT				14
+#define OMAP44XX_REG_MT_MASK				(1 << 14)
+#define OMAP44XX_REG_ACT_CAP_EN_SHIFT			13
+#define OMAP44XX_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define OMAP44XX_REG_OPG_LD_SHIFT			12
+#define OMAP44XX_REG_OPG_LD_MASK			(1 << 12)
+#define OMAP44XX_REG_RESET_PHY_SHIFT			10
+#define OMAP44XX_REG_RESET_PHY_MASK			(1 << 10)
+#define OMAP44XX_REG_MMS_SHIFT				8
+#define OMAP44XX_REG_MMS_MASK				(1 << 8)
+#define OMAP44XX_REG_MC_SHIFT				4
+#define OMAP44XX_REG_MC_MASK				(0x3 << 4)
+#define OMAP44XX_REG_PC_SHIFT				1
+#define OMAP44XX_REG_PC_MASK				(0x7 << 1)
+#define OMAP44XX_REG_TM_SHIFT				0
+#define OMAP44XX_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define OMAP44XX_REG_DQM_TLMR_SHIFT			16
+#define OMAP44XX_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define OMAP44XX_REG_CTL_TLMR_SHIFT			0
+#define OMAP44XX_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define OMAP44XX_REG_ADDR_TLMR_SHIFT			0
+#define OMAP44XX_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT		0
+#define OMAP44XX_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define OMAP44XX_REG_COUNTER1_SHIFT			0
+#define OMAP44XX_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define OMAP44XX_REG_COUNTER2_SHIFT			0
+#define OMAP44XX_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT		30
+#define OMAP44XX_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define OMAP44XX_REG_CNTR2_CFG_SHIFT			16
+#define OMAP44XX_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT		14
+#define OMAP44XX_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define OMAP44XX_REG_CNTR1_CFG_SHIFT			0
+#define OMAP44XX_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define OMAP44XX_REG_MCONNID2_SHIFT			24
+#define OMAP44XX_REG_MCONNID2_MASK			(0xff << 24)
+#define OMAP44XX_REG_REGION_SEL2_SHIFT			16
+#define OMAP44XX_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define OMAP44XX_REG_MCONNID1_SHIFT			8
+#define OMAP44XX_REG_MCONNID1_MASK			(0xff << 8)
+#define OMAP44XX_REG_REGION_SEL1_SHIFT			0
+#define OMAP44XX_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define OMAP44XX_REG_TOTAL_TIME_SHIFT			0
+#define OMAP44XX_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define OMAP44XX_REG_EOI_SHIFT				0
+#define OMAP44XX_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define OMAP44XX_REG_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define OMAP44XX_REG_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_TA_LL_SHIFT			1
+#define OMAP44XX_REG_TA_LL_MASK				(1 << 1)
+#define OMAP44XX_REG_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define OMAP44XX_REG_EN_DNV_SYS_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_SYS_SHIFT			1
+#define OMAP44XX_REG_EN_TA_SYS_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_SYS_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define OMAP44XX_REG_EN_DNV_LL_SHIFT			2
+#define OMAP44XX_REG_EN_DNV_LL_MASK			(1 << 2)
+#define OMAP44XX_REG_EN_TA_LL_SHIFT			1
+#define OMAP44XX_REG_EN_TA_LL_MASK			(1 << 1)
+#define OMAP44XX_REG_EN_ERR_LL_SHIFT			0
+#define OMAP44XX_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define OMAP44XX_REG_ZQ_CS1EN_SHIFT			31
+#define OMAP44XX_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_ZQ_CS0EN_SHIFT			30
+#define OMAP44XX_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT			29
+#define OMAP44XX_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define OMAP44XX_REG_TA_CS1EN_SHIFT			31
+#define OMAP44XX_REG_TA_CS1EN_MASK			(1 << 31)
+#define OMAP44XX_REG_TA_CS0EN_SHIFT			30
+#define OMAP44XX_REG_TA_CS0EN_MASK			(1 << 30)
+#define OMAP44XX_REG_TA_SFEXITEN_SHIFT			28
+#define OMAP44XX_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define OMAP44XX_REG_TA_DEVWDT_SHIFT			26
+#define OMAP44XX_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define OMAP44XX_REG_TA_DEVCNT_SHIFT			24
+#define OMAP44XX_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT		0
+#define OMAP44XX_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define OMAP44XX_REG_MADDRSPACE_SHIFT			14
+#define OMAP44XX_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define OMAP44XX_REG_MBURSTSEQ_SHIFT			11
+#define OMAP44XX_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define OMAP44XX_REG_MCMD_SHIFT				8
+#define OMAP44XX_REG_MCMD_MASK				(0x7 << 8)
+#define OMAP44XX_REG_MCONNID_SHIFT			0
+#define OMAP44XX_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHIFT			0
+#define OMAP44XX_REG_READ_LATENCY_MASK			(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT		0
+#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/* DMM */
+#define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
+
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_LISA_MAP_BASE		0x482AF040
+
+/* DMM_LISA_MAP */
+#define OMAP44XX_SYS_ADDR_SHIFT		24
+#define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)
+#define OMAP44XX_SYS_SIZE_SHIFT		20
+#define OMAP44XX_SYS_SIZE_MASK		(0x7 << 20)
+#define OMAP44XX_SDRC_INTL_SHIFT	18
+#define OMAP44XX_SDRC_INTL_MASK		(0x3 << 18)
+#define OMAP44XX_SDRC_ADDRSPC_SHIFT	16
+#define OMAP44XX_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define OMAP44XX_SDRC_MAP_SHIFT		8
+#define OMAP44XX_SDRC_MAP_MASK		(0x3 << 8)
+#define OMAP44XX_SDRC_ADDR_SHIFT	0
+#define OMAP44XX_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 padding6[4];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+};
+
+struct control_lpddr2io_regs {
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#define RL_FINAL	6
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0xF
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\
+			& OMAP44XX_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\
+			& OMAP44XX_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
+			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen at lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+};
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h
index 019574b..30bfad7 100644
--- a/arch/arm/include/asm/arch-omap4/mux_omap4.h
+++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h
@@ -341,4 +341,5 @@ struct pad_conf_entry {
 #define CONTROL_SPARE_R		0x0618
 #define CONTROL_SPARE_R_C0		0x061C
 
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
 #endif /* _MUX_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb33..9aad0e6 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,20 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define LPDDR2_IO_REGS_BASE	0x4A100638
+
+#define CONTROL_EFUSE_2		0x4A100704
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -70,12 +84,6 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
 /*
  * Hardware Register Details
  */
@@ -119,13 +127,38 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+#define LOW_LEVEL_SRAM_STACK		NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
+#define OMAP4460_ES1_0	0x44600100
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
+/* GPIO */
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
 
 #endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 4fa4f4b..a81f8e5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,21 +22,89 @@
 #define _SYS_PROTO_H_
 
 #include <asm/arch/omap4.h>
+#include <asm/arch/clocks.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;
 };
+extern const struct omap_sysinfo sysinfo;
+
+extern struct omap4_prcm_regs *const prcm;
 
 void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap4_rev_string);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap4_sdram_size(void);
 
-extern const struct omap_sysinfo sysinfo;
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs at 100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap4_revision;
+	return *omap4_revision;
+}
 
 #endif
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 88b9c62..9adc563 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -25,6 +25,12 @@
 #define ARMV7_H
 #include <linux/types.h>
 
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0
 #define CCSIDR_LINE_SIZE_MASK		0x7
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..d3cb857
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+void preloader_console_init(void);
+
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
+#endif /* _OMAP_COMMON_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/omap_gpio.h
index 30f633c..3089e1c 100644
--- a/arch/arm/include/asm/arch-omap3/gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -38,36 +38,15 @@
 #ifndef _GPIO_H
 #define _GPIO_H
 
-#define OMAP24XX_GPIO_REVISION		0x0000
-#define OMAP24XX_GPIO_SYSCONFIG		0x0010
-#define OMAP24XX_GPIO_SYSSTATUS		0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
-#define OMAP24XX_GPIO_IRQENABLE2	0x002c
-#define OMAP24XX_GPIO_IRQENABLE1	0x001c
-#define OMAP24XX_GPIO_WAKE_EN		0x0020
-#define OMAP24XX_GPIO_CTRL		0x0030
-#define OMAP24XX_GPIO_OE		0x0034
-#define OMAP24XX_GPIO_DATAIN		0x0038
-#define OMAP24XX_GPIO_DATAOUT		0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
-#define OMAP24XX_GPIO_RISINGDETECT	0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
-#define OMAP24XX_GPIO_SETWKUENA		0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
-#define OMAP24XX_GPIO_SETDATAOUT	0x0094
+#include <asm/arch/cpu.h>
 
 struct gpio_bank {
 	void *base;
 	int method;
 };
 
+extern const struct gpio_bank *const omap_gpio_bank;
+
 #define METHOD_GPIO_24XX	4
 
 /* This is the interface */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 90709d0..14a56f6 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -84,26 +84,28 @@ extern void rtl8019_get_enetaddr (uchar * addr);
  ************************************************************************
  * May be supplied by boards if desired
  */
-void inline __coloured_LED_init (void) {}
-void coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init")));
-void inline __red_LED_on (void) {}
-void red_LED_on (void) __attribute__((weak, alias("__red_LED_on")));
-void inline __red_LED_off(void) {}
+inline void __coloured_LED_init(void) {}
+void coloured_LED_init(void)
+	__attribute__((weak, alias("__coloured_LED_init")));
+inline void __red_LED_on(void) {}
+void red_LED_on(void) __attribute__((weak, alias("__red_LED_on")));
+inline void __red_LED_off(void) {}
 void red_LED_off(void) __attribute__((weak, alias("__red_LED_off")));
-void inline __green_LED_on(void) {}
+inline void __green_LED_on(void) {}
 void green_LED_on(void) __attribute__((weak, alias("__green_LED_on")));
-void inline __green_LED_off(void) {}
+inline void __green_LED_off(void) {}
 void green_LED_off(void) __attribute__((weak, alias("__green_LED_off")));
-void inline __yellow_LED_on(void) {}
+inline void __yellow_LED_on(void) {}
 void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on")));
-void inline __yellow_LED_off(void) {}
+inline void __yellow_LED_off(void) {}
 void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off")));
-void inline __blue_LED_on(void) {}
+inline void __blue_LED_on(void) {}
 void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on")));
-void inline __blue_LED_off(void) {}
+inline void __blue_LED_off(void) {}
 void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off")));
 
-/************************************************************************
+/*
+ ************************************************************************
  * Init Utilities							*
  ************************************************************************
  * Some of this code should be moved into the core functions,
@@ -114,30 +116,30 @@ void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off")));
 #if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
 #define CONFIG_BAUDRATE 115200
 #endif
-static int init_baudrate (void)
+static int init_baudrate(void)
 {
 	char tmp[64];	/* long enough for environment variables */
-	int i = getenv_f("baudrate", tmp, sizeof (tmp));
+	int i = getenv_f("baudrate", tmp, sizeof(tmp));
 
 	gd->baudrate = (i > 0)
-			? (int) simple_strtoul (tmp, NULL, 10)
+			? (int) simple_strtoul(tmp, NULL, 10)
 			: CONFIG_BAUDRATE;
 
 	return (0);
 }
 
-static int display_banner (void)
+static int display_banner(void)
 {
-	printf ("\n\n%s\n\n", version_string);
-	debug ("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
+	printf("\n\n%s\n\n", version_string);
+	debug("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
 	       _TEXT_BASE,
-	       _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
+	       _bss_start_ofs + _TEXT_BASE, _bss_end_ofs + _TEXT_BASE);
 #ifdef CONFIG_MODEM_SUPPORT
-	debug ("Modem Support enabled\n");
+	debug("Modem Support enabled\n");
 #endif
 #ifdef CONFIG_USE_IRQ
-	debug ("IRQ Stack: %08lx\n", IRQ_STACK_START);
-	debug ("FIQ Stack: %08lx\n", FIQ_STACK_START);
+	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
+	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
 #endif
 
 	return (0);
@@ -150,23 +152,23 @@ static int display_banner (void)
  * gives a simple yet clear indication which part of the
  * initialization if failing.
  */
-static int display_dram_config (void)
+static int display_dram_config(void)
 {
 	int i;
 
 #ifdef DEBUG
-	puts ("RAM Configuration:\n");
+	puts("RAM Configuration:\n");
 
-	for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
-		printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
-		print_size (gd->bd->bi_dram[i].size, "\n");
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
 	}
 #else
 	ulong size = 0;
 
-	for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 		size += gd->bd->bi_dram[i].size;
-	}
+
 	puts("DRAM:  ");
 	print_size(size, "\n");
 #endif
@@ -175,11 +177,11 @@ static int display_dram_config (void)
 }
 
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-static int init_func_i2c (void)
+static int init_func_i2c(void)
 {
-	puts ("I2C:   ");
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	puts ("ready\n");
+	puts("I2C:   ");
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	puts("ready\n");
 	return (0);
 }
 #endif
@@ -218,7 +220,7 @@ static int arm_pci_init(void)
  */
 typedef int (init_fnc_t) (void);
 
-int print_cpuinfo (void);
+int print_cpuinfo(void);
 
 void __dram_init_banksize(void)
 {
@@ -257,7 +259,7 @@ init_fnc_t *init_sequence[] = {
 	NULL,
 };
 
-void board_init_f (ulong bootflag)
+void board_init_f(ulong bootflag)
 {
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
@@ -269,7 +271,7 @@ void board_init_f (ulong bootflag)
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-	memset ((void*)gd, 0, sizeof (gd_t));
+	memset((void *)gd, 0, sizeof(gd_t));
 
 	gd->mon_len = _bss_end_ofs;
 
@@ -283,11 +285,11 @@ void board_init_f (ulong bootflag)
 		}
 	}
 
-	debug ("monitor len: %08lX\n", gd->mon_len);
+	debug("monitor len: %08lX\n", gd->mon_len);
 	/*
 	 * Ram is setup, size stored in gd !!
 	 */
-	debug ("ramsize: %08lX\n", gd->ram_size);
+	debug("ramsize: %08lX\n", gd->ram_size);
 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
 	/*
 	 * Subtract specified amount of memory to hide so that it won't
@@ -308,7 +310,8 @@ void board_init_f (ulong bootflag)
 #ifndef CONFIG_ALT_LB_ADDR
 	/* reserve kernel log buffer */
 	addr -= (LOGBUFF_RESERVE);
-	debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
+	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
+		addr);
 #endif
 #endif
 
@@ -316,10 +319,11 @@ void board_init_f (ulong bootflag)
 	/*
 	 * reserve protected RAM
 	 */
-	i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
-	reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
+	i = getenv_r("pram", (char *)tmp, sizeof(tmp));
+	reg = (i > 0) ? simple_strtoul((const char *)tmp, NULL, 10) :
+		CONFIG_PRAM;
 	addr -= (reg << 10);		/* size is in kB */
-	debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
+	debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
 #endif /* CONFIG_PRAM */
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -330,19 +334,19 @@ void board_init_f (ulong bootflag)
 	addr &= ~(0x10000 - 1);
 
 	gd->tlb_addr = addr;
-	debug ("TLB table at: %08lx\n", addr);
+	debug("TLB table at: %08lx\n", addr);
 #endif
 
 	/* round down to next 4 kB limit */
 	addr &= ~(4096 - 1);
-	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
 
 #ifdef CONFIG_LCD
 #ifdef CONFIG_FB_ADDR
 	gd->fb_base = CONFIG_FB_ADDR;
 #else
 	/* reserve memory for LCD display (always full pages) */
-	addr = lcd_setmem (addr);
+	addr = lcd_setmem(addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_FB_ADDR */
 #endif /* CONFIG_LCD */
@@ -354,14 +358,14 @@ void board_init_f (ulong bootflag)
 	addr -= gd->mon_len;
 	addr &= ~(4096 - 1);
 
-	debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
 
 #ifndef CONFIG_SPL_BUILD
 	/*
 	 * reserve memory for malloc() arena
 	 */
 	addr_sp = addr - TOTAL_MALLOC_LEN;
-	debug ("Reserving %dk for malloc() at: %08lx\n",
+	debug("Reserving %dk for malloc() at: %08lx\n",
 			TOTAL_MALLOC_LEN >> 10, addr_sp);
 	/*
 	 * (permanently) allocate a Board Info struct
@@ -370,18 +374,18 @@ void board_init_f (ulong bootflag)
 	addr_sp -= sizeof (bd_t);
 	bd = (bd_t *) addr_sp;
 	gd->bd = bd;
-	debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
 			sizeof (bd_t), addr_sp);
 	addr_sp -= sizeof (gd_t);
 	id = (gd_t *) addr_sp;
-	debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
 
 	/* setup stackpointer for exeptions */
 	gd->irq_sp = addr_sp;
 #ifdef CONFIG_USE_IRQ
 	addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
-	debug ("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
 		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
 #endif
 	/* leave 3 words for abort-stack    */
@@ -394,11 +398,11 @@ void board_init_f (ulong bootflag)
 	gd->irq_sp = addr_sp;
 #endif
 
-	debug ("New Stack Pointer is: %08lx\n", addr_sp);
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
 
 #ifdef CONFIG_POST
 	post_bootmode_init();
-	post_run (NULL, POST_ROM | post_bootmode_get(0));
+	post_run(NULL, POST_ROM | post_bootmode_get(0));
 #endif
 
 	gd->bd->bi_baudrate = gd->baudrate;
@@ -409,10 +413,10 @@ void board_init_f (ulong bootflag)
 	gd->relocaddr = addr;
 	gd->start_addr_sp = addr_sp;
 	gd->reloc_off = addr - _TEXT_BASE;
-	debug ("relocation Offset is: %08lx\n", gd->reloc_off);
-	memcpy (id, (void *)gd, sizeof (gd_t));
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, sizeof(gd_t));
 
-	relocate_code (addr_sp, id, addr);
+	relocate_code(addr_sp, id, addr);
 
 	/* NOTREACHED - relocate_code() does not return */
 }
@@ -421,7 +425,8 @@ void board_init_f (ulong bootflag)
 static char *failed = "*** failed ***\n";
 #endif
 
-/************************************************************************
+/*
+ ************************************************************************
  *
  * This is the next part if the initialization sequence: we are now
  * running from RAM and have a "normal" C environment, i. e. global
@@ -431,7 +436,7 @@ static char *failed = "*** failed ***\n";
  ************************************************************************
  */
 
-void board_init_r (gd_t *id, ulong dest_addr)
+void board_init_r(gd_t *id, ulong dest_addr)
 {
 	char *s;
 	bd_t *bd;
@@ -452,20 +457,20 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	 */
 	dcache_enable();
 
-	debug ("monitor flash len: %08lX\n", monitor_flash_len);
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
 	board_init();	/* Setup chipselects */
 
 #ifdef CONFIG_SERIAL_MULTI
 	serial_initialize();
 #endif
 
-	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
 #ifdef CONFIG_LOGBUFFER
-	logbuff_init_ptrs ();
+	logbuff_init_ptrs();
 #endif
 #ifdef CONFIG_POST
-	post_output_backlog ();
+	post_output_backlog();
 #endif
 
 	/* The Malloc area is immediately below the monitor copy in DRAM */
@@ -473,34 +478,35 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
 
 #if !defined(CONFIG_SYS_NO_FLASH)
-	puts ("Flash: ");
+	puts("Flash: ");
 
-	if ((flash_size = flash_init ()) > 0) {
+	flash_size = flash_init();
+	if (flash_size > 0) {
 # ifdef CONFIG_SYS_FLASH_CHECKSUM
-		print_size (flash_size, "");
+		print_size(flash_size, "");
 		/*
 		 * Compute and print flash CRC if flashchecksum is set to 'y'
 		 *
 		 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
 		 */
-		s = getenv ("flashchecksum");
+		s = getenv("flashchecksum");
 		if (s && (*s == 'y')) {
-			printf ("  CRC: %08X",
-				crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
-			);
+			printf("  CRC: %08X", crc32(0,
+				(const unsigned char *) CONFIG_SYS_FLASH_BASE,
+				flash_size));
 		}
-		putc ('\n');
+		putc('\n');
 # else	/* !CONFIG_SYS_FLASH_CHECKSUM */
-		print_size (flash_size, "\n");
+		print_size(flash_size, "\n");
 # endif /* CONFIG_SYS_FLASH_CHECKSUM */
 	} else {
-		puts (failed);
-		hang ();
+		puts(failed);
+		hang();
 	}
 #endif
 
 #if defined(CONFIG_CMD_NAND)
-	puts ("NAND:  ");
+	puts("NAND:  ");
 	nand_init();		/* go init the NAND */
 #endif
 
@@ -519,44 +525,44 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif
 
 	/* initialize environment */
-	env_relocate ();
+	env_relocate();
 
 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
 	arm_pci_init();
 #endif
 
 	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
+	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
 
-	stdio_init ();	/* get the devices list going. */
+	stdio_init();	/* get the devices list going. */
 
-	jumptable_init ();
+	jumptable_init();
 
 #if defined(CONFIG_API)
 	/* Initialize API */
-	api_init ();
+	api_init();
 #endif
 
-	console_init_r ();	/* fully init console as a device */
+	console_init_r();	/* fully init console as a device */
 
 #if defined(CONFIG_ARCH_MISC_INIT)
 	/* miscellaneous arch dependent initialisations */
-	arch_misc_init ();
+	arch_misc_init();
 #endif
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
-	misc_init_r ();
+	misc_init_r();
 #endif
 
 	 /* set up exceptions */
-	interrupt_init ();
+	interrupt_init();
 	/* enable exceptions */
-	enable_interrupts ();
+	enable_interrupts();
 
 	/* Perform network card initialisation if necessary */
 #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
 	/* XXX: this needs to be moved to board init */
-	if (getenv ("ethaddr")) {
+	if (getenv("ethaddr")) {
 		uchar enetaddr[6];
 		eth_getenv_enetaddr("ethaddr", enetaddr);
 		smc_set_mac_addr(enetaddr);
@@ -564,17 +570,17 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
 
 	/* Initialize from environment */
-	if ((s = getenv ("loadaddr")) != NULL) {
-		load_addr = simple_strtoul (s, NULL, 16);
-	}
+	s = getenv("loadaddr");
+	if (s != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
 #if defined(CONFIG_CMD_NET)
-	if ((s = getenv ("bootfile")) != NULL) {
-		copy_filename (BootFile, s, sizeof (BootFile));
-	}
+	s = getenv("bootfile");
+	if (s != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
 #endif
 
 #ifdef BOARD_LATE_INIT
-	board_late_init ();
+	board_late_init();
 #endif
 
 #ifdef CONFIG_BITBANGMII
@@ -582,17 +588,17 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif
 #if defined(CONFIG_CMD_NET)
 #if defined(CONFIG_NET_MULTI)
-	puts ("Net:   ");
+	puts("Net:   ");
 #endif
 	eth_initialize(gd->bd);
 #if defined(CONFIG_RESET_PHY_R)
-	debug ("Reset Ethernet PHY\n");
+	debug("Reset Ethernet PHY\n");
 	reset_phy();
 #endif
 #endif
 
 #ifdef CONFIG_POST
-	post_run (NULL, POST_RAM | post_bootmode_get(0));
+	post_run(NULL, POST_RAM | post_bootmode_get(0));
 #endif
 
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
@@ -606,35 +612,35 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #ifdef CONFIG_PRAM
 		char *s;
 
-		if ((s = getenv ("pram")) != NULL) {
-			pram = simple_strtoul (s, NULL, 10);
-		} else {
+		s = getenv("pram");
+		if (s != NULL)
+			pram = simple_strtoul(s, NULL, 10);
+		else
 			pram = CONFIG_PRAM;
-		}
 #else
-		pram=0;
+		pram = 0;
 #endif
 #ifdef CONFIG_LOGBUFFER
 #ifndef CONFIG_ALT_LB_ADDR
 		/* Also take the logbuffer into account (pram is in kB) */
-		pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
+		pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
 #endif
 #endif
-		sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
-		setenv ("mem", (char *)memsz);
+		sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
+		setenv("mem", (char *)memsz);
 	}
 #endif
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */
 	for (;;) {
-		main_loop ();
+		main_loop();
 	}
 
 	/* NOTREACHED - no way out of command loop except booting */
 }
 
-void hang (void)
+void hang(void)
 {
-	puts ("### ERROR ### Please RESET the board ###\n");
+	puts("### ERROR ### Please RESET the board ###\n");
 	for (;;);
 }