diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-11-21 13:39:01 -0800 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-19 09:41:21 +0100 |
| commit | 97598fcf10eba577622f3387eaecd43dd710da0d (patch) | |
| tree | 68f59303d1d8f6ca2d941f8365fa00868091603e /arch | |
| parent | 1cd46ed2d30a931a66400635f158b14861f2d3b4 (diff) | |
| download | u-boot-imx-97598fcf10eba577622f3387eaecd43dd710da0d.zip u-boot-imx-97598fcf10eba577622f3387eaecd43dd710da0d.tar.gz u-boot-imx-97598fcf10eba577622f3387eaecd43dd710da0d.tar.bz2 | |
net: zynq_gem: Calculate clock dividers dynamically
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynq/sys_proto.h | 2 |
2 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 6710d92..d7c1882 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <malloc.h> #include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D @@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void) } /* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) +void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { + int ret; + zynq_slcr_unlock(); if (gem_id > 1) { @@ -59,14 +62,14 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) goto out; } + ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate); + if (ret) + goto out; + if (gem_id) { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem1_clk_ctrl); /* Configure GEM_RCLK_CTRL */ writel(1, &slcr_base->gem1_rclk_ctrl); } else { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem0_clk_ctrl); /* Configure GEM_RCLK_CTRL */ writel(1, &slcr_base->gem0_rclk_ctrl); } diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a485d79..0a2ba05 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -10,7 +10,7 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk); +extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); |