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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2011-02-09 09:24:10 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-10 11:17:55 -0500 |
| commit | 32c8cfb23cd8beb814edd217c02e6aa5c7a64acf (patch) | |
| tree | f7ce54174e4505b24df46aad21aa0dbbca53bacd /arch | |
| parent | 2a9fab82b74d59aa9150e905aa06a6bff32c5059 (diff) | |
| download | u-boot-imx-32c8cfb23cd8beb814edd217c02e6aa5c7a64acf.zip u-boot-imx-32c8cfb23cd8beb814edd217c02e6aa5c7a64acf.tar.gz u-boot-imx-32c8cfb23cd8beb814edd217c02e6aa5c7a64acf.tar.bz2 | |
fsl_esdhc: Deal with watermark level register related changes
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 59aeb31..41fd86c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -88,6 +88,7 @@ #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -131,6 +132,7 @@ #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 |