arm: rmobile: Add support koelsch board

The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB,
Quad SPI, Ethernet, and more.

This patch supports the following functions:
 - DDR3-SDRAM
 - SCIF

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

1 files changed, 69 insertions, 3 deletions

diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 8f26e6e..2afda0a 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -1,6 +1,5 @@
 /*
  * arch/arm/include/asm/arch-rmobile/r8a7791.h
- *     This file is r8a7791 processor definition.
  *
  * Copyright (C) 2013 Renesas Electronics Corporation
  *
@@ -64,12 +63,48 @@
 #define DBSC3_0_QOS_W14_BASE	0xE6792E00
 #define DBSC3_0_QOS_W15_BASE	0xE6792F00
 
+#define DBSC3_1_QOS_R0_BASE	0xE67A1000
+#define DBSC3_1_QOS_R1_BASE	0xE67A1100
+#define DBSC3_1_QOS_R2_BASE	0xE67A1200
+#define DBSC3_1_QOS_R3_BASE	0xE67A1300
+#define DBSC3_1_QOS_R4_BASE	0xE67A1400
+#define DBSC3_1_QOS_R5_BASE	0xE67A1500
+#define DBSC3_1_QOS_R6_BASE	0xE67A1600
+#define DBSC3_1_QOS_R7_BASE	0xE67A1700
+#define DBSC3_1_QOS_R8_BASE	0xE67A1800
+#define DBSC3_1_QOS_R9_BASE	0xE67A1900
+#define DBSC3_1_QOS_R10_BASE	0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE	0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE	0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE	0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE	0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE	0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE	0xE67A2000
+#define DBSC3_1_QOS_W1_BASE	0xE67A2100
+#define DBSC3_1_QOS_W2_BASE	0xE67A2200
+#define DBSC3_1_QOS_W3_BASE	0xE67A2300
+#define DBSC3_1_QOS_W4_BASE	0xE67A2400
+#define DBSC3_1_QOS_W5_BASE	0xE67A2500
+#define DBSC3_1_QOS_W6_BASE	0xE67A2600
+#define DBSC3_1_QOS_W7_BASE	0xE67A2700
+#define DBSC3_1_QOS_W8_BASE	0xE67A2800
+#define DBSC3_1_QOS_W9_BASE	0xE67A2900
+#define DBSC3_1_QOS_W10_BASE	0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE	0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE	0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE	0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE	0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE	0xE67A2F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
 #define CCI_400_MAXOT_1		0xF0091110
 #define CCI_400_MAXOT_2		0xF0092110
 #define CCI_400_QOSCNTL_1	0xF009110C
 #define CCI_400_QOSCNTL_2	0xF009210C
 
 #define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
 
 #define SYS_AXI_SYX64TO128_BASE	0xFF800300
 #define SYS_AXI_AVB_BASE	0xFF800340
@@ -95,11 +130,28 @@
 #define SYS_AXI_USB21_BASE	0xFF800C40
 #define SYS_AXI_USB22_BASE	0xFF800C80
 #define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
+#define SYS_AXI_MPXM_BASE	0xFF800840
+#define SYS_AXI_SAT0_BASE	0xFF800980
+#define SYS_AXI_SAT1_BASE	0xFF8009C0
+#define SYS_AXI_SDM0_BASE	0xFF800A00
+#define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_UDM0_BASE	0xFF800B80
+#define SYS_AXI_UDM1_BASE	0xFF800BC0
 
 #define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_DBG_BASE		0xFF810140
+#define RT_AXI_RDM_BASE		0xFF810180
 #define RT_AXI_RDS_BASE		0xFF8101C0
 #define RT_AXI_RTX64TO128_BASE	0xFF810200
 #define RT_AXI_STPRO_BASE	0xFF810240
+#define RT_AXI_SY2RT_BASE	0xFF810280
 
 #define MP_AXI_ADSP_BASE	0xFF820100
 #define MP_AXI_ASDS0_BASE	0xFF8201C0
@@ -123,6 +175,8 @@
 #define CCI_AXI_MMUS1_BASE	0xFF880280
 #define CCI_AXI_MMUMP_BASE	0xFF8802C0
 
+#define MEDIA_AXI_MXR_BASE	0xFE960080
+#define MEDIA_AXI_MXW_BASE	0xFE9600C0
 #define MEDIA_AXI_JPR_BASE	0xFE964100
 #define MEDIA_AXI_JPW_BASE	0xFE966100
 #define MEDIA_AXI_GCU0R_BASE	0xFE964140
@@ -567,18 +621,30 @@ struct r8a7791_dbsc3_qos {
 	u32 dbthres0;
 	u32 dbthres1;
 	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
 	u32 dblgqon;
 };
 
 /* MXI(QoS) */
 struct r8a7791_mxi {
-	u32 dummy0[10];	/* 0x00 .. 0x24 */
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[8];	/* 0x08 .. 0x24 */
 	u32 mxs3cracr;
-	u32 dummy1[5];	/* 0x2C .. 0x3C */
+	u32 dummy1[3];	/* 0x2C .. 0x34 */
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
 	u32 mxrtcr;
 	u32 mxwtcr;
 };
 
+struct r8a7791_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
 /* AXI(QoS) */
 struct r8a7791_axi_qos {
 	u32 qosconf;