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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-12 15:34:56 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-12 17:43:39 -0500 |
| commit | 5298f21ab3781a8cb7fecd5ef559c81e7605d1f5 (patch) | |
| tree | 62125bde75ee5fcda1387f6f2bd9b7ceb9f0d187 /arch | |
| parent | f3ef3609dbb5a9693b2ccdfd4545e73cd273d684 (diff) | |
| download | u-boot-imx-5298f21ab3781a8cb7fecd5ef559c81e7605d1f5.zip u-boot-imx-5298f21ab3781a8cb7fecd5ef559c81e7605d1f5.tar.gz u-boot-imx-5298f21ab3781a8cb7fecd5ef559c81e7605d1f5.tar.bz2 | |
ARM: DRA7xx: Change clk divider setting
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.
Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 82910e8..a0d69a7 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -169,13 +169,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ - {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { |