Merge branch 'master' of git://git.denx.de/u-boot-tegra

Conflicts:
	README

Signed-off-by: Tom Rini <trini@konsulko.com>

23 files changed, 1158 insertions, 88 deletions

diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
new file mode 100644
index 0000000..6f7fca0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on:
+ *
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		CPUDIR/start.o	(.text)
+		*(.text*)
+	} > .nor
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .nor
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss
+}
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index b69fd37..4cb8806 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -112,13 +112,20 @@ int armv7_init_nonsec(void)
 	for (i = 1; i <= itlinesnr; i++)
 		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
 
+	/*
+	 * Relocate secure section before any cpu runs in secure ram.
+	 * smp_kick_all_cpus may enable other cores and runs into secure
+	 * ram, so need to relocate secure section before enabling other
+	 * cores.
+	 */
+	relocate_secure_section();
+
 #ifndef CONFIG_ARMV7_PSCI
 	smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
 	smp_kick_all_cpus();
 #endif
 
 	/* call the non-sec switching code on this CPU also */
-	relocate_secure_section();
 	secure_ram_addr(_nonsec_init)();
 	return 0;
 }
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index df80a4e..b4eab0b 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -67,6 +67,9 @@ reset:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
+	/* Apply ARM core specific erratas */
+	bl	apply_core_errata
+
 	/*
 	 * Cache/BPB/TLB Invalidate
 	 * i-cache is invalidated before enabled in icache_enable()
@@ -97,6 +100,48 @@ master_cpu:
 
 /*-----------------------------------------------------------------------*/
 
+WEAK(apply_core_errata)
+
+	mov	x29, lr			/* Save LR */
+	/* For now, we support Cortex-A57 specific errata only */
+
+	/* Check if we are running on a Cortex-A57 core */
+	branch_if_a57_core x0, apply_a57_core_errata
+0:
+	mov	lr, x29			/* Restore LR */
+	ret
+
+apply_a57_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_828024
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable non-allocate hint of w-b-n-a memory type */
+	mov	x0, #0x1 << 49
+	/* Disable write streaming no L1-allocate threshold */
+	mov	x0, #0x3 << 25
+	/* Disable write streaming no-allocate threshold */
+	mov	x0, #0x3 << 27
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_826974
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable speculative load execution ahead of a DMB */
+	mov	x0, #0x1 << 59
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_833069
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Disable Enable Invalidates of BTB bit */
+	and	x0, x0, #0xE
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+	b 0b
+ENDPROC(apply_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
 WEAK(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/cpu/tegra210-common/pinmux.c
new file mode 100644
index 0000000..a29c76b
--- /dev/null
+++ b/arch/arm/cpu/tegra210-common/pinmux.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+			PMUX_FUNC_##f2,	\
+			PMUX_FUNC_##f3,	\
+		},			\
+	}
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra210_pingroups[] = {
+	/*  pin,                  f0,         f1,     f2,    f3 */
+	/* Offset 0x3000 */
+	PIN(SDMMC1_CLK_PM0,       SDMMC1,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC1_CMD_PM1,       SDMMC1,     SPI3,   RSVD2, RSVD3),
+	PIN(SDMMC1_DAT3_PM2,      SDMMC1,     SPI3,   RSVD2, RSVD3),
+	PIN(SDMMC1_DAT2_PM3,      SDMMC1,     SPI3,   RSVD2, RSVD3),
+	PIN(SDMMC1_DAT1_PM4,      SDMMC1,     SPI3,   RSVD2, RSVD3),
+	PIN(SDMMC1_DAT0_PM5,      SDMMC1,     RSVD1,  RSVD2, RSVD3),
+	PIN_RESERVED,
+	/* Offset 0x301c */
+	PIN(SDMMC3_CLK_PP0,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC3_CMD_PP1,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC3_DAT0_PP5,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC3_DAT1_PP4,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC3_DAT2_PP3,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(SDMMC3_DAT3_PP2,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN_RESERVED,
+	/* Offset 0x3038 */
+	PIN(PEX_L0_RST_N_PA0,     PE0,        RSVD1,  RSVD2, RSVD3),
+	PIN(PEX_L0_CLKREQ_N_PA1,  PE0,        RSVD1,  RSVD2, RSVD3),
+	PIN(PEX_WAKE_N_PA2,       PE,         RSVD1,  RSVD2, RSVD3),
+	PIN(PEX_L1_RST_N_PA3,     PE1,        RSVD1,  RSVD2, RSVD3),
+	PIN(PEX_L1_CLKREQ_N_PA4,  PE1,        RSVD1,  RSVD2, RSVD3),
+	PIN(SATA_LED_ACTIVE_PA5,  SATA,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI1_MOSI_PC0,        SPI1,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI1_MISO_PC1,        SPI1,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI1_SCK_PC2,         SPI1,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI1_CS0_PC3,         SPI1,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI1_CS1_PC4,         SPI1,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI2_MOSI_PB4,        SPI2,       DTV,    RSVD2, RSVD3),
+	PIN(SPI2_MISO_PB5,        SPI2,       DTV,    RSVD2, RSVD3),
+	PIN(SPI2_SCK_PB6,         SPI2,       DTV,    RSVD2, RSVD3),
+	PIN(SPI2_CS0_PB7,         SPI2,       DTV,    RSVD2, RSVD3),
+	PIN(SPI2_CS1_PDD0,        SPI2,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI4_MOSI_PC7,        SPI4,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI4_MISO_PD0,        SPI4,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI4_SCK_PC5,         SPI4,       RSVD1,  RSVD2, RSVD3),
+	PIN(SPI4_CS0_PC6,         SPI4,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_SCK_PEE0,        QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_CS_N_PEE1,       QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_IO0_PEE2,        QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_IO1_PEE3,        QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_IO2_PEE4,        QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN(QSPI_IO3_PEE5,        QSPI,       RSVD1,  RSVD2, RSVD3),
+	PIN_RESERVED,
+	/* Offset 0x30a4 */
+	PIN(DMIC1_CLK_PE0,        DMIC1,      I2S3,   RSVD2, RSVD3),
+	PIN(DMIC1_DAT_PE1,        DMIC1,      I2S3,   RSVD2, RSVD3),
+	PIN(DMIC2_CLK_PE2,        DMIC2,      I2S3,   RSVD2, RSVD3),
+	PIN(DMIC2_DAT_PE3,        DMIC2,      I2S3,   RSVD2, RSVD3),
+	PIN(DMIC3_CLK_PE4,        DMIC3,      I2S5A,  RSVD2, RSVD3),
+	PIN(DMIC3_DAT_PE5,        DMIC3,      I2S5A,  RSVD2, RSVD3),
+	PIN(GEN1_I2C_SCL_PJ1,     I2C1,       RSVD1,  RSVD2, RSVD3),
+	PIN(GEN1_I2C_SDA_PJ0,     I2C1,       RSVD1,  RSVD2, RSVD3),
+	PIN(GEN2_I2C_SCL_PJ2,     I2C2,       RSVD1,  RSVD2, RSVD3),
+	PIN(GEN2_I2C_SDA_PJ3,     I2C2,       RSVD1,  RSVD2, RSVD3),
+	PIN(GEN3_I2C_SCL_PF0,     I2C3,       RSVD1,  RSVD2, RSVD3),
+	PIN(GEN3_I2C_SDA_PF1,     I2C3,       RSVD1,  RSVD2, RSVD3),
+	PIN(CAM_I2C_SCL_PS2,      I2C3,       I2CVI,  RSVD2, RSVD3),
+	PIN(CAM_I2C_SDA_PS3,      I2C3,       I2CVI,  RSVD2, RSVD3),
+	PIN(PWR_I2C_SCL_PY3,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
+	PIN(PWR_I2C_SDA_PY4,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
+	PIN(UART1_TX_PU0,         UARTA,      RSVD1,  RSVD2, RSVD3),
+	PIN(UART1_RX_PU1,         UARTA,      RSVD1,  RSVD2, RSVD3),
+	PIN(UART1_RTS_PU2,        UARTA,      RSVD1,  RSVD2, RSVD3),
+	PIN(UART1_CTS_PU3,        UARTA,      RSVD1,  RSVD2, RSVD3),
+	PIN(UART2_TX_PG0,         UARTB,      I2S4A,  SPDIF, UART),
+	PIN(UART2_RX_PG1,         UARTB,      I2S4A,  SPDIF, UART),
+	PIN(UART2_RTS_PG2,        UARTB,      I2S4A,  RSVD2, UART),
+	PIN(UART2_CTS_PG3,        UARTB,      I2S4A,  RSVD2, UART),
+	PIN(UART3_TX_PD1,         UARTC,      SPI4,   RSVD2, RSVD3),
+	PIN(UART3_RX_PD2,         UARTC,      SPI4,   RSVD2, RSVD3),
+	PIN(UART3_RTS_PD3,        UARTC,      SPI4,   RSVD2, RSVD3),
+	PIN(UART3_CTS_PD4,        UARTC,      SPI4,   RSVD2, RSVD3),
+	PIN(UART4_TX_PI4,         UARTD,      UART,   RSVD2, RSVD3),
+	PIN(UART4_RX_PI5,         UARTD,      UART,   RSVD2, RSVD3),
+	PIN(UART4_RTS_PI6,        UARTD,      UART,   RSVD2, RSVD3),
+	PIN(UART4_CTS_PI7,        UARTD,      UART,   RSVD2, RSVD3),
+	PIN(DAP1_FS_PB0,          I2S1,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP1_DIN_PB1,         I2S1,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP1_DOUT_PB2,        I2S1,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP1_SCLK_PB3,        I2S1,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP2_FS_PAA0,         I2S2,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP2_DIN_PAA2,        I2S2,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP2_DOUT_PAA3,       I2S2,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP2_SCLK_PAA1,       I2S2,       RSVD1,  RSVD2, RSVD3),
+	PIN(DAP4_FS_PJ4,          I2S4B,      RSVD1,  RSVD2, RSVD3),
+	PIN(DAP4_DIN_PJ5,         I2S4B,      RSVD1,  RSVD2, RSVD3),
+	PIN(DAP4_DOUT_PJ6,        I2S4B,      RSVD1,  RSVD2, RSVD3),
+	PIN(DAP4_SCLK_PJ7,        I2S4B,      RSVD1,  RSVD2, RSVD3),
+	PIN(CAM1_MCLK_PS0,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
+	PIN(CAM2_MCLK_PS1,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
+	PIN(JTAG_RTCK,            JTAG,       RSVD1,  RSVD2, RSVD3),
+	PIN(CLK_32K_IN,           CLK,        RSVD1,  RSVD2, RSVD3),
+	PIN(CLK_32K_OUT_PY5,      SOC,        BLINK,  RSVD2, RSVD3),
+	PIN(BATT_BCL,             BCL,        RSVD1,  RSVD2, RSVD3),
+	PIN(CLK_REQ,              SYS,        RSVD1,  RSVD2, RSVD3),
+	PIN(CPU_PWR_REQ,          CPU,        RSVD1,  RSVD2, RSVD3),
+	PIN(PWR_INT_N,            PMI,        RSVD1,  RSVD2, RSVD3),
+	PIN(SHUTDOWN,             SHUTDOWN,   RSVD1,  RSVD2, RSVD3),
+	PIN(CORE_PWR_REQ,         CORE,       RSVD1,  RSVD2, RSVD3),
+	PIN(AUD_MCLK_PBB0,        AUD,        RSVD1,  RSVD2, RSVD3),
+	PIN(DVFS_PWM_PBB1,        RSVD0,      CLDVFS, SPI3,  RSVD3),
+	PIN(DVFS_CLK_PBB2,        RSVD0,      CLDVFS, SPI3,  RSVD3),
+	PIN(GPIO_X1_AUD_PBB3,     RSVD0,      RSVD1,  SPI3,  RSVD3),
+	PIN(GPIO_X3_AUD_PBB4,     RSVD0,      RSVD1,  SPI3,  RSVD3),
+	PIN(PCC7,                 RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(HDMI_CEC_PCC0,        CEC,        RSVD1,  RSVD2, RSVD3),
+	PIN(HDMI_INT_DP_HPD_PCC1, DP,         RSVD1,  RSVD2, RSVD3),
+	PIN(SPDIF_OUT_PCC2,       SPDIF,      RSVD1,  RSVD2, RSVD3),
+	PIN(SPDIF_IN_PCC3,        SPDIF,      RSVD1,  RSVD2, RSVD3),
+	PIN(USB_VBUS_EN0_PCC4,    USB,        RSVD1,  RSVD2, RSVD3),
+	PIN(USB_VBUS_EN1_PCC5,    USB,        RSVD1,  RSVD2, RSVD3),
+	PIN(DP_HPD0_PCC6,         DP,         RSVD1,  RSVD2, RSVD3),
+	PIN(WIFI_EN_PH0,          RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(WIFI_RST_PH1,         RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(WIFI_WAKE_AP_PH2,     RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(AP_WAKE_BT_PH3,       RSVD0,      UARTB,  SPDIF, RSVD3),
+	PIN(BT_RST_PH4,           RSVD0,      UARTB,  SPDIF, RSVD3),
+	PIN(BT_WAKE_AP_PH5,       RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(AP_WAKE_NFC_PH7,      RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(NFC_EN_PI0,           RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(NFC_INT_PI1,          RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(GPS_EN_PI2,           RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(GPS_RST_PI3,          RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(CAM_RST_PS4,          VGP1,       RSVD1,  RSVD2, RSVD3),
+	PIN(CAM_AF_EN_PS5,        VIMCLK,     VGP2,   RSVD2, RSVD3),
+	PIN(CAM_FLASH_EN_PS6,     VIMCLK,     VGP3,   RSVD2, RSVD3),
+	PIN(CAM1_PWDN_PS7,        VGP4,       RSVD1,  RSVD2, RSVD3),
+	PIN(CAM2_PWDN_PT0,        VGP5,       RSVD1,  RSVD2, RSVD3),
+	PIN(CAM1_STROBE_PT1,      VGP6,       RSVD1,  RSVD2, RSVD3),
+	PIN(LCD_TE_PY2,           DISPLAYA,   RSVD1,  RSVD2, RSVD3),
+	PIN(LCD_BL_PWM_PV0,       DISPLAYA,   PWM0,   SOR0,  RSVD3),
+	PIN(LCD_BL_EN_PV1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(LCD_RST_PV2,          RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(LCD_GPIO1_PV3,        DISPLAYB,   RSVD1,  RSVD2, RSVD3),
+	PIN(LCD_GPIO2_PV4,        DISPLAYB,   PWM1,   RSVD2, SOR1),
+	PIN(AP_READY_PV5,         RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(TOUCH_RST_PV6,        RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(TOUCH_CLK_PV7,        TOUCH,      RSVD1,  RSVD2, RSVD3),
+	PIN(MODEM_WAKE_AP_PX0,    RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(TOUCH_INT_PX1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(MOTION_INT_PX2,       RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(ALS_PROX_INT_PX3,     RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(TEMP_ALERT_PX4,       RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(BUTTON_POWER_ON_PX5,  RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(BUTTON_VOL_UP_PX6,    RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(BUTTON_VOL_DOWN_PX7,  RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(BUTTON_SLIDE_SW_PY0,  RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(BUTTON_HOME_PY1,      RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(PA6,                  SATA,       RSVD1,  RSVD2, RSVD3),
+	PIN(PE6,                  RSVD0,      I2S5A,  PWM2,  RSVD3),
+	PIN(PE7,                  RSVD0,      I2S5A,  PWM3,  RSVD3),
+	PIN(PH6,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(PK0,                  IQC0,       I2S5B,  RSVD2, RSVD3),
+	PIN(PK1,                  IQC0,       I2S5B,  RSVD2, RSVD3),
+	PIN(PK2,                  IQC0,       I2S5B,  RSVD2, RSVD3),
+	PIN(PK3,                  IQC0,       I2S5B,  RSVD2, RSVD3),
+	PIN(PK4,                  IQC1,       RSVD1,  RSVD2, RSVD3),
+	PIN(PK5,                  IQC1,       RSVD1,  RSVD2, RSVD3),
+	PIN(PK6,                  IQC1,       RSVD1,  RSVD2, RSVD3),
+	PIN(PK7,                  IQC1,       RSVD1,  RSVD2, RSVD3),
+	PIN(PL0,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
+	PIN(PL1,                  SOC,        RSVD1,  RSVD2, RSVD3),
+	PIN(PZ0,                  VIMCLK2,    RSVD1,  RSVD2, RSVD3),
+	PIN(PZ1,                  VIMCLK2,    SDMMC1, RSVD2, RSVD3),
+	PIN(PZ2,                  SDMMC3,     CCLA,   RSVD2, RSVD3),
+	PIN(PZ3,                  SDMMC3,     RSVD1,  RSVD2, RSVD3),
+	PIN(PZ4,                  SDMMC1,     RSVD1,  RSVD2, RSVD3),
+	PIN(PZ5,                  SOC,        RSVD1,  RSVD2, RSVD3),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 15db0f2..13ab42b 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -18,6 +18,10 @@
 		sdhci0 = "/sdhci@78000600";
 		sdhci1 = "/sdhci@78000400";
 		sdhci2 = "/sdhci@78000000";
+		spi0 = "/spi@7000d400";
+		spi1 = "/spi@7000dc00";
+		spi2 = "/spi@7000de00";
+		spi3 = "/spi@7000da00";
 		usb0 = "/usb@7d000000";
 		usb1 = "/usb@7d004000";
 		usb2 = "/usb@7d008000";
@@ -243,13 +247,15 @@
 	sdhci@78000000 {
 		status = "okay";
 		bus-width = <4>;
-		cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
+		/* SD1_CD# */
+		cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
 	};
 
 	sdhci@78000400 {
 		status = "okay";
 		bus-width = <8>;
-		cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+		/* MMC1_CD# */
+		cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
 	};
 
 	sdhci@78000600 {
@@ -262,12 +268,14 @@
 	usb@7d000000 {
 		status = "okay";
 		dr_mode = "peripheral";
+		/* USBO1_EN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
 	};
 
 	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
 	usb@7d004000 {
 		status = "okay";
+		/* USBH_EN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
 		phy_type = "utmi";
 	};
@@ -275,6 +283,7 @@
 	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
 	usb@7d008000 {
 		status = "okay";
+		/* USBH_EN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
 	};
 
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 6cd1902..36533dc 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -64,7 +64,7 @@
 	sdhci@78000200 {
 		status = "okay";
 		bus-width = <4>;
-		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
 	};
 
 	sdhci@78000600 {
@@ -83,12 +83,14 @@
 	usb@7d004000 {
 		status = "okay";
 		phy_type = "utmi";
+		/* VBUS_LAN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
 	};
 
 	/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
 	usb@7d008000 {
 		status = "okay";
+		/* USBH_PEN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h
new file mode 100644
index 0000000..23745bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/spl.h
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NOR		1
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 5c8be94..ca40e4e 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -74,3 +74,7 @@ static inline void config_vpr(void)
 {
 }
 #endif
+
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+bool tegra_cpu_is_non_secure(void);
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index da47769..4212e57 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -23,39 +23,82 @@ enum pmux_tristate {
 	PMUX_TRI_TRISTATE = 1,
 };
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 enum pmux_pin_io {
 	PMUX_PIN_OUTPUT = 0,
 	PMUX_PIN_INPUT = 1,
 	PMUX_PIN_NONE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 enum pmux_pin_lock {
 	PMUX_PIN_LOCK_DEFAULT = 0,
 	PMUX_PIN_LOCK_DISABLE,
 	PMUX_PIN_LOCK_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 enum pmux_pin_od {
 	PMUX_PIN_OD_DEFAULT = 0,
 	PMUX_PIN_OD_DISABLE,
 	PMUX_PIN_OD_ENABLE,
 };
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 enum pmux_pin_ioreset {
 	PMUX_PIN_IO_RESET_DEFAULT = 0,
 	PMUX_PIN_IO_RESET_DISABLE,
 	PMUX_PIN_IO_RESET_ENABLE,
 };
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 enum pmux_pin_rcv_sel {
 	PMUX_PIN_RCV_SEL_DEFAULT = 0,
 	PMUX_PIN_RCV_SEL_NORMAL,
 	PMUX_PIN_RCV_SEL_HIGH,
 };
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+enum pmux_pin_e_io_hv {
+	PMUX_PIN_E_IO_HV_DEFAULT = 0,
+	PMUX_PIN_E_IO_HV_NORMAL,
+	PMUX_PIN_E_IO_HV_HIGH,
+};
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+	PMUX_LPMD_X8 = 0,
+	PMUX_LPMD_X4,
+	PMUX_LPMD_X2,
+	PMUX_LPMD_X,
+	PMUX_LPMD_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+	PMUX_SCHMT_DISABLE = 0,
+	PMUX_SCHMT_ENABLE = 1,
+	PMUX_SCHMT_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+	PMUX_HSM_DISABLE = 0,
+	PMUX_HSM_ENABLE = 1,
+	PMUX_HSM_NONE = -1,
+};
+#endif
 
 /*
  * This defines the configuration for a pin, including the function assigned,
@@ -68,21 +111,37 @@ struct pmux_pingrp_config {
 	u32 func:8;		/* function to assign PMUX_FUNC_... */
 	u32 pull:2;		/* pull up/down/normal PMUX_PULL_...*/
 	u32 tristate:2;		/* tristate or normal PMUX_TRI_...  */
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 	u32 io:2;		/* input or output PMUX_PIN_...     */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 	u32 lock:2;		/* lock enable/disable PMUX_PIN...  */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 	u32 od:2;		/* open-drain or push-pull driver   */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 	u32 ioreset:2;		/* input/output reset PMUX_PIN...   */
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 	u32 rcv_sel:2;		/* select between High and Normal  */
 				/* VIL/VIH receivers */
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+	u32 e_io_hv:2;		/* select 3.3v tolerant receivers */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+	u32 schmt:2;		/* schmitt enable            */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+	u32 hsm:2;		/* high-speed mode enable    */
 #endif
 };
 
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
-/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
+/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
 void pinmux_set_tristate_input_clamping(void);
+void pinmux_clear_tristate_input_clamping(void);
 #endif
 
 /* Set the mux function for a pin group */
@@ -97,7 +156,7 @@ void pinmux_tristate_enable(enum pmux_pingrp pin);
 /* Set a pin group to normal (non tristate) */
 void pinmux_tristate_disable(enum pmux_pingrp pin);
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 /* Set a pin group as input or output */
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 #endif
@@ -111,7 +170,7 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 				int len);
 
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN	0
 #define PMUX_SLWF_MAX	3
@@ -129,29 +188,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define PMUX_DRVDN_MAX	127
 #define PMUX_DRVDN_NONE	-1
 
-/* Defines a pin group cfg's low-power mode select */
-enum pmux_lpmd {
-	PMUX_LPMD_X8 = 0,
-	PMUX_LPMD_X4,
-	PMUX_LPMD_X2,
-	PMUX_LPMD_X,
-	PMUX_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pmux_schmt {
-	PMUX_SCHMT_DISABLE = 0,
-	PMUX_SCHMT_ENABLE = 1,
-	PMUX_SCHMT_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pmux_hsm {
-	PMUX_HSM_DISABLE = 0,
-	PMUX_HSM_ENABLE = 1,
-	PMUX_HSM_NONE = -1,
-};
-
 /*
  * This defines the configuration for a pin group's pad control config
  */
@@ -161,9 +197,15 @@ struct pmux_drvgrp_config {
 	u32 slwr:3;		/* rising edge slew          */
 	u32 drvup:8;		/* pull-up drive strength    */
 	u32 drvdn:8;		/* pull-down drive strength  */
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 	u32 lpmd:3;		/* low-power mode selection  */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 	u32 schmt:2;		/* schmidt enable            */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 	u32 hsm:2;		/* high-speed mode enable    */
+#endif
 };
 
 /**
@@ -175,7 +217,7 @@ struct pmux_drvgrp_config {
 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 				int len);
 
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
 struct pmux_pingrp_desc {
 	u8 funcs[4];
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index b86562a..38d8b9c 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -313,9 +313,17 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 1884935..78bc9e6 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -335,9 +335,17 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_RCV_SEL
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index f7bc97f..bf35d50 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -233,6 +233,7 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA20_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h
new file mode 100644
index 0000000..af3b55f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/pinmux.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA210_PINMUX_H_
+#define _TEGRA210_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_SDMMC1_CLK_PM0,
+	PMUX_PINGRP_SDMMC1_CMD_PM1,
+	PMUX_PINGRP_SDMMC1_DAT3_PM2,
+	PMUX_PINGRP_SDMMC1_DAT2_PM3,
+	PMUX_PINGRP_SDMMC1_DAT1_PM4,
+	PMUX_PINGRP_SDMMC1_DAT0_PM5,
+	PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PP1,
+	PMUX_PINGRP_SDMMC3_DAT0_PP5,
+	PMUX_PINGRP_SDMMC3_DAT1_PP4,
+	PMUX_PINGRP_SDMMC3_DAT2_PP3,
+	PMUX_PINGRP_SDMMC3_DAT3_PP2,
+	PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
+	PMUX_PINGRP_PEX_WAKE_N_PA2,
+	PMUX_PINGRP_PEX_L1_RST_N_PA3,
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
+	PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
+	PMUX_PINGRP_SPI1_MOSI_PC0,
+	PMUX_PINGRP_SPI1_MISO_PC1,
+	PMUX_PINGRP_SPI1_SCK_PC2,
+	PMUX_PINGRP_SPI1_CS0_PC3,
+	PMUX_PINGRP_SPI1_CS1_PC4,
+	PMUX_PINGRP_SPI2_MOSI_PB4,
+	PMUX_PINGRP_SPI2_MISO_PB5,
+	PMUX_PINGRP_SPI2_SCK_PB6,
+	PMUX_PINGRP_SPI2_CS0_PB7,
+	PMUX_PINGRP_SPI2_CS1_PDD0,
+	PMUX_PINGRP_SPI4_MOSI_PC7,
+	PMUX_PINGRP_SPI4_MISO_PD0,
+	PMUX_PINGRP_SPI4_SCK_PC5,
+	PMUX_PINGRP_SPI4_CS0_PC6,
+	PMUX_PINGRP_QSPI_SCK_PEE0,
+	PMUX_PINGRP_QSPI_CS_N_PEE1,
+	PMUX_PINGRP_QSPI_IO0_PEE2,
+	PMUX_PINGRP_QSPI_IO1_PEE3,
+	PMUX_PINGRP_QSPI_IO2_PEE4,
+	PMUX_PINGRP_QSPI_IO3_PEE5,
+	PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
+	PMUX_PINGRP_DMIC1_DAT_PE1,
+	PMUX_PINGRP_DMIC2_CLK_PE2,
+	PMUX_PINGRP_DMIC2_DAT_PE3,
+	PMUX_PINGRP_DMIC3_CLK_PE4,
+	PMUX_PINGRP_DMIC3_DAT_PE5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
+	PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
+	PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
+	PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
+	PMUX_PINGRP_GEN3_I2C_SCL_PF0,
+	PMUX_PINGRP_GEN3_I2C_SDA_PF1,
+	PMUX_PINGRP_CAM_I2C_SCL_PS2,
+	PMUX_PINGRP_CAM_I2C_SDA_PS3,
+	PMUX_PINGRP_PWR_I2C_SCL_PY3,
+	PMUX_PINGRP_PWR_I2C_SDA_PY4,
+	PMUX_PINGRP_UART1_TX_PU0,
+	PMUX_PINGRP_UART1_RX_PU1,
+	PMUX_PINGRP_UART1_RTS_PU2,
+	PMUX_PINGRP_UART1_CTS_PU3,
+	PMUX_PINGRP_UART2_TX_PG0,
+	PMUX_PINGRP_UART2_RX_PG1,
+	PMUX_PINGRP_UART2_RTS_PG2,
+	PMUX_PINGRP_UART2_CTS_PG3,
+	PMUX_PINGRP_UART3_TX_PD1,
+	PMUX_PINGRP_UART3_RX_PD2,
+	PMUX_PINGRP_UART3_RTS_PD3,
+	PMUX_PINGRP_UART3_CTS_PD4,
+	PMUX_PINGRP_UART4_TX_PI4,
+	PMUX_PINGRP_UART4_RX_PI5,
+	PMUX_PINGRP_UART4_RTS_PI6,
+	PMUX_PINGRP_UART4_CTS_PI7,
+	PMUX_PINGRP_DAP1_FS_PB0,
+	PMUX_PINGRP_DAP1_DIN_PB1,
+	PMUX_PINGRP_DAP1_DOUT_PB2,
+	PMUX_PINGRP_DAP1_SCLK_PB3,
+	PMUX_PINGRP_DAP2_FS_PAA0,
+	PMUX_PINGRP_DAP2_DIN_PAA2,
+	PMUX_PINGRP_DAP2_DOUT_PAA3,
+	PMUX_PINGRP_DAP2_SCLK_PAA1,
+	PMUX_PINGRP_DAP4_FS_PJ4,
+	PMUX_PINGRP_DAP4_DIN_PJ5,
+	PMUX_PINGRP_DAP4_DOUT_PJ6,
+	PMUX_PINGRP_DAP4_SCLK_PJ7,
+	PMUX_PINGRP_CAM1_MCLK_PS0,
+	PMUX_PINGRP_CAM2_MCLK_PS1,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_CLK_32K_OUT_PY5,
+	PMUX_PINGRP_BATT_BCL,
+	PMUX_PINGRP_CLK_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_SHUTDOWN,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_AUD_MCLK_PBB0,
+	PMUX_PINGRP_DVFS_PWM_PBB1,
+	PMUX_PINGRP_DVFS_CLK_PBB2,
+	PMUX_PINGRP_GPIO_X1_AUD_PBB3,
+	PMUX_PINGRP_GPIO_X3_AUD_PBB4,
+	PMUX_PINGRP_PCC7,
+	PMUX_PINGRP_HDMI_CEC_PCC0,
+	PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
+	PMUX_PINGRP_SPDIF_OUT_PCC2,
+	PMUX_PINGRP_SPDIF_IN_PCC3,
+	PMUX_PINGRP_USB_VBUS_EN0_PCC4,
+	PMUX_PINGRP_USB_VBUS_EN1_PCC5,
+	PMUX_PINGRP_DP_HPD0_PCC6,
+	PMUX_PINGRP_WIFI_EN_PH0,
+	PMUX_PINGRP_WIFI_RST_PH1,
+	PMUX_PINGRP_WIFI_WAKE_AP_PH2,
+	PMUX_PINGRP_AP_WAKE_BT_PH3,
+	PMUX_PINGRP_BT_RST_PH4,
+	PMUX_PINGRP_BT_WAKE_AP_PH5,
+	PMUX_PINGRP_AP_WAKE_NFC_PH7,
+	PMUX_PINGRP_NFC_EN_PI0,
+	PMUX_PINGRP_NFC_INT_PI1,
+	PMUX_PINGRP_GPS_EN_PI2,
+	PMUX_PINGRP_GPS_RST_PI3,
+	PMUX_PINGRP_CAM_RST_PS4,
+	PMUX_PINGRP_CAM_AF_EN_PS5,
+	PMUX_PINGRP_CAM_FLASH_EN_PS6,
+	PMUX_PINGRP_CAM1_PWDN_PS7,
+	PMUX_PINGRP_CAM2_PWDN_PT0,
+	PMUX_PINGRP_CAM1_STROBE_PT1,
+	PMUX_PINGRP_LCD_TE_PY2,
+	PMUX_PINGRP_LCD_BL_PWM_PV0,
+	PMUX_PINGRP_LCD_BL_EN_PV1,
+	PMUX_PINGRP_LCD_RST_PV2,
+	PMUX_PINGRP_LCD_GPIO1_PV3,
+	PMUX_PINGRP_LCD_GPIO2_PV4,
+	PMUX_PINGRP_AP_READY_PV5,
+	PMUX_PINGRP_TOUCH_RST_PV6,
+	PMUX_PINGRP_TOUCH_CLK_PV7,
+	PMUX_PINGRP_MODEM_WAKE_AP_PX0,
+	PMUX_PINGRP_TOUCH_INT_PX1,
+	PMUX_PINGRP_MOTION_INT_PX2,
+	PMUX_PINGRP_ALS_PROX_INT_PX3,
+	PMUX_PINGRP_TEMP_ALERT_PX4,
+	PMUX_PINGRP_BUTTON_POWER_ON_PX5,
+	PMUX_PINGRP_BUTTON_VOL_UP_PX6,
+	PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
+	PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
+	PMUX_PINGRP_BUTTON_HOME_PY1,
+	PMUX_PINGRP_PA6,
+	PMUX_PINGRP_PE6,
+	PMUX_PINGRP_PE7,
+	PMUX_PINGRP_PH6,
+	PMUX_PINGRP_PK0,
+	PMUX_PINGRP_PK1,
+	PMUX_PINGRP_PK2,
+	PMUX_PINGRP_PK3,
+	PMUX_PINGRP_PK4,
+	PMUX_PINGRP_PK5,
+	PMUX_PINGRP_PK6,
+	PMUX_PINGRP_PK7,
+	PMUX_PINGRP_PL0,
+	PMUX_PINGRP_PL1,
+	PMUX_PINGRP_PZ0,
+	PMUX_PINGRP_PZ1,
+	PMUX_PINGRP_PZ2,
+	PMUX_PINGRP_PZ3,
+	PMUX_PINGRP_PZ4,
+	PMUX_PINGRP_PZ5,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
+	PMUX_DRVGRP_AP_READY,
+	PMUX_DRVGRP_AP_WAKE_BT,
+	PMUX_DRVGRP_AP_WAKE_NFC,
+	PMUX_DRVGRP_AUD_MCLK,
+	PMUX_DRVGRP_BATT_BCL,
+	PMUX_DRVGRP_BT_RST,
+	PMUX_DRVGRP_BT_WAKE_AP,
+	PMUX_DRVGRP_BUTTON_HOME,
+	PMUX_DRVGRP_BUTTON_POWER_ON,
+	PMUX_DRVGRP_BUTTON_SLIDE_SW,
+	PMUX_DRVGRP_BUTTON_VOL_DOWN,
+	PMUX_DRVGRP_BUTTON_VOL_UP,
+	PMUX_DRVGRP_CAM1_MCLK,
+	PMUX_DRVGRP_CAM1_PWDN,
+	PMUX_DRVGRP_CAM1_STROBE,
+	PMUX_DRVGRP_CAM2_MCLK,
+	PMUX_DRVGRP_CAM2_PWDN,
+	PMUX_DRVGRP_CAM_AF_EN,
+	PMUX_DRVGRP_CAM_FLASH_EN,
+	PMUX_DRVGRP_CAM_I2C_SCL,
+	PMUX_DRVGRP_CAM_I2C_SDA,
+	PMUX_DRVGRP_CAM_RST,
+	PMUX_DRVGRP_CLK_32K_IN,
+	PMUX_DRVGRP_CLK_32K_OUT,
+	PMUX_DRVGRP_CLK_REQ,
+	PMUX_DRVGRP_CORE_PWR_REQ,
+	PMUX_DRVGRP_CPU_PWR_REQ,
+	PMUX_DRVGRP_DAP1_DIN,
+	PMUX_DRVGRP_DAP1_DOUT,
+	PMUX_DRVGRP_DAP1_FS,
+	PMUX_DRVGRP_DAP1_SCLK,
+	PMUX_DRVGRP_DAP2_DIN,
+	PMUX_DRVGRP_DAP2_DOUT,
+	PMUX_DRVGRP_DAP2_FS,
+	PMUX_DRVGRP_DAP2_SCLK,
+	PMUX_DRVGRP_DAP4_DIN,
+	PMUX_DRVGRP_DAP4_DOUT,
+	PMUX_DRVGRP_DAP4_FS,
+	PMUX_DRVGRP_DAP4_SCLK,
+	PMUX_DRVGRP_DMIC1_CLK,
+	PMUX_DRVGRP_DMIC1_DAT,
+	PMUX_DRVGRP_DMIC2_CLK,
+	PMUX_DRVGRP_DMIC2_DAT,
+	PMUX_DRVGRP_DMIC3_CLK,
+	PMUX_DRVGRP_DMIC3_DAT,
+	PMUX_DRVGRP_DP_HPD0,
+	PMUX_DRVGRP_DVFS_CLK,
+	PMUX_DRVGRP_DVFS_PWM,
+	PMUX_DRVGRP_GEN1_I2C_SCL,
+	PMUX_DRVGRP_GEN1_I2C_SDA,
+	PMUX_DRVGRP_GEN2_I2C_SCL,
+	PMUX_DRVGRP_GEN2_I2C_SDA,
+	PMUX_DRVGRP_GEN3_I2C_SCL,
+	PMUX_DRVGRP_GEN3_I2C_SDA,
+	PMUX_DRVGRP_PA6,
+	PMUX_DRVGRP_PCC7,
+	PMUX_DRVGRP_PE6,
+	PMUX_DRVGRP_PE7,
+	PMUX_DRVGRP_PH6,
+	PMUX_DRVGRP_PK0,
+	PMUX_DRVGRP_PK1,
+	PMUX_DRVGRP_PK2,
+	PMUX_DRVGRP_PK3,
+	PMUX_DRVGRP_PK4,
+	PMUX_DRVGRP_PK5,
+	PMUX_DRVGRP_PK6,
+	PMUX_DRVGRP_PK7,
+	PMUX_DRVGRP_PL0,
+	PMUX_DRVGRP_PL1,
+	PMUX_DRVGRP_PZ0,
+	PMUX_DRVGRP_PZ1,
+	PMUX_DRVGRP_PZ2,
+	PMUX_DRVGRP_PZ3,
+	PMUX_DRVGRP_PZ4,
+	PMUX_DRVGRP_PZ5,
+	PMUX_DRVGRP_GPIO_X1_AUD,
+	PMUX_DRVGRP_GPIO_X3_AUD,
+	PMUX_DRVGRP_GPS_EN,
+	PMUX_DRVGRP_GPS_RST,
+	PMUX_DRVGRP_HDMI_CEC,
+	PMUX_DRVGRP_HDMI_INT_DP_HPD,
+	PMUX_DRVGRP_JTAG_RTCK,
+	PMUX_DRVGRP_LCD_BL_EN,
+	PMUX_DRVGRP_LCD_BL_PWM,
+	PMUX_DRVGRP_LCD_GPIO1,
+	PMUX_DRVGRP_LCD_GPIO2,
+	PMUX_DRVGRP_LCD_RST,
+	PMUX_DRVGRP_LCD_TE,
+	PMUX_DRVGRP_MODEM_WAKE_AP,
+	PMUX_DRVGRP_MOTION_INT,
+	PMUX_DRVGRP_NFC_EN,
+	PMUX_DRVGRP_NFC_INT,
+	PMUX_DRVGRP_PEX_L0_CLKREQ_N,
+	PMUX_DRVGRP_PEX_L0_RST_N,
+	PMUX_DRVGRP_PEX_L1_CLKREQ_N,
+	PMUX_DRVGRP_PEX_L1_RST_N,
+	PMUX_DRVGRP_PEX_WAKE_N,
+	PMUX_DRVGRP_PWR_I2C_SCL,
+	PMUX_DRVGRP_PWR_I2C_SDA,
+	PMUX_DRVGRP_PWR_INT_N,
+	PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
+	PMUX_DRVGRP_SATA_LED_ACTIVE,
+	PMUX_DRVGRP_SDMMC1,
+	PMUX_DRVGRP_SDMMC2,
+	PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
+	PMUX_DRVGRP_SDMMC4,
+	PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
+	PMUX_DRVGRP_SPDIF_IN,
+	PMUX_DRVGRP_SPDIF_OUT,
+	PMUX_DRVGRP_SPI1_CS0,
+	PMUX_DRVGRP_SPI1_CS1,
+	PMUX_DRVGRP_SPI1_MISO,
+	PMUX_DRVGRP_SPI1_MOSI,
+	PMUX_DRVGRP_SPI1_SCK,
+	PMUX_DRVGRP_SPI2_CS0,
+	PMUX_DRVGRP_SPI2_CS1,
+	PMUX_DRVGRP_SPI2_MISO,
+	PMUX_DRVGRP_SPI2_MOSI,
+	PMUX_DRVGRP_SPI2_SCK,
+	PMUX_DRVGRP_SPI4_CS0,
+	PMUX_DRVGRP_SPI4_MISO,
+	PMUX_DRVGRP_SPI4_MOSI,
+	PMUX_DRVGRP_SPI4_SCK,
+	PMUX_DRVGRP_TEMP_ALERT,
+	PMUX_DRVGRP_TOUCH_CLK,
+	PMUX_DRVGRP_TOUCH_INT,
+	PMUX_DRVGRP_TOUCH_RST,
+	PMUX_DRVGRP_UART1_CTS,
+	PMUX_DRVGRP_UART1_RTS,
+	PMUX_DRVGRP_UART1_RX,
+	PMUX_DRVGRP_UART1_TX,
+	PMUX_DRVGRP_UART2_CTS,
+	PMUX_DRVGRP_UART2_RTS,
+	PMUX_DRVGRP_UART2_RX,
+	PMUX_DRVGRP_UART2_TX,
+	PMUX_DRVGRP_UART3_CTS,
+	PMUX_DRVGRP_UART3_RTS,
+	PMUX_DRVGRP_UART3_RX,
+	PMUX_DRVGRP_UART3_TX,
+	PMUX_DRVGRP_UART4_CTS,
+	PMUX_DRVGRP_UART4_RTS,
+	PMUX_DRVGRP_UART4_RX,
+	PMUX_DRVGRP_UART4_TX,
+	PMUX_DRVGRP_USB_VBUS_EN0,
+	PMUX_DRVGRP_USB_VBUS_EN1,
+	PMUX_DRVGRP_WIFI_EN,
+	PMUX_DRVGRP_WIFI_RST,
+	PMUX_DRVGRP_WIFI_WAKE_AP,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_AUD,
+	PMUX_FUNC_BCL,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CCLA,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CORE,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DMIC1,
+	PMUX_FUNC_DMIC2,
+	PMUX_FUNC_DMIC3,
+	PMUX_FUNC_DP,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2CPMU,
+	PMUX_FUNC_I2CVI,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4A,
+	PMUX_FUNC_I2S4B,
+	PMUX_FUNC_I2S5A,
+	PMUX_FUNC_I2S5B,
+	PMUX_FUNC_IQC0,
+	PMUX_FUNC_IQC1,
+	PMUX_FUNC_JTAG,
+	PMUX_FUNC_PE,
+	PMUX_FUNC_PE0,
+	PMUX_FUNC_PE1,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_QSPI,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SHUTDOWN,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SOR0,
+	PMUX_FUNC_SOR1,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SYS,
+	PMUX_FUNC_TOUCH,
+	PMUX_FUNC_UART,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VIMCLK,
+	PMUX_FUNC_VIMCLK2,
+	PMUX_FUNC_RSVD0,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_E_IO_HV
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA210_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index a42e009..3358bf7 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -391,8 +391,15 @@ enum pmux_func {
 	PMUX_FUNC_COUNT,
 };
 
-#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-#define TEGRA_PMX_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
 #include <asm/arch-tegra/pinmux.h>
 
 #endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 3b3146a..3cf3307 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -74,6 +74,28 @@ lr	.req	x30
 .endm
 
 /*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro	branch_if_a57_core, xreg, a57_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	and	\xreg, \xreg, #0x00000FFF
+	cmp	\xreg, #0xD07		/* Cortex-A57 MPCore processor. */
+	b.eq	\a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro	branch_if_a53_core, xreg, a53_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	and	\xreg, \xreg, #0x00000FFF
+	cmp	\xreg, #0xD03		/* Cortex-A53 MPCore processor. */
+	b.eq	\a53_label
+.endm
+
+/*
  * Branch if current processor is a slave,
  * choose processor with all zero affinity value as the master.
  */
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 4dacfd9..06f4679 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -137,10 +137,15 @@ void show_regs (struct pt_regs *regs)
 
 	flags = condition_codes (regs);
 
-	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf("pc : [<%08lx>]	   lr : [<%08lx>]\n",
+	       instruction_pointer(regs), regs->ARM_lr);
+	if (gd->flags & GD_FLG_RELOC) {
+		printf("reloc pc : [<%08lx>]	   lr : [<%08lx>]\n",
+		       instruction_pointer(regs) - gd->reloc_off,
+		       regs->ARM_lr - gd->reloc_off);
+	}
+	printf("sp : %08lx  ip : %08lx	 fp : %08lx\n",
+	       regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
 	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
 		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
 	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 5a54262..291c511 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -5,6 +5,7 @@ choice
 
 config TARGET_EDMINIV2
 	bool "LaCie Ethernet Disk mini V2"
+	select SUPPORT_SPL
 
 endchoice
 
diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c
index f88db3b..2ecd385 100644
--- a/arch/arm/mach-orion5x/cpu.c
+++ b/arch/arm/mach-orion5x/cpu.c
@@ -234,7 +234,9 @@ int arch_cpu_init(void)
 	/* Enable and invalidate L2 cache in write through mode */
 	invalidate_l2_cache();
 
+#ifdef CONFIG_SPL_BUILD
 	orion5x_config_adr_windows();
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/mach-orion5x/include/mach/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h
index 08a450f..092dbd6 100644
--- a/arch/arm/mach-orion5x/include/mach/cpu.h
+++ b/arch/arm/mach-orion5x/include/mach/cpu.h
@@ -86,7 +86,7 @@ enum orion5x_cpu_attrib {
 #endif
 
 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
-#define ORION5X_ADR_PCIE_IO_REMAP_LO	0x90000000
+#define ORION5X_ADR_PCIE_IO_REMAP_LO	0xf0000000
 #endif
 
 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S
index 4dacc29..51a8b3c 100644
--- a/arch/arm/mach-orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
@@ -62,14 +62,16 @@
 /*
  * Low-level init happens right after start.S has switched to SVC32,
  * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
+ * from the boot chip select, so the first thing SPL should do is to
+ * set up the RAM to copy U-Boot into.
  */
 
 .globl lowlevel_init
 
 lowlevel_init:
 
+#ifdef CONFIG_SPL_BUILD
+
 	/* Use 'r4 as the base for internal register accesses */
 	ldr	r4, =ORION5X_REGS_PHY_BASE
 
@@ -273,5 +275,13 @@ lowlevel_init:
 	orr	r2, r2, r6
 	str	r2, [r3, #0x484]
 
+	/* enable for 2 GB DDR; detection should find out real amount */
+	sub	r6, r6, r6
+	str	r6, [r3, #0x500]
+	ldr	r6, =0x7fff0001
+	str	r6, [r3, #0x504]
+
+#endif /* CONFIG_SPL_BUILD */
+
 	/* Return to U-boot via saved link register */
 	mov	pc, lr
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index b6a84a5..0ebaf19 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -11,6 +11,7 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/mc.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/sys_proto.h>
@@ -28,27 +29,66 @@ enum {
 	UART_COUNT = 5,
 };
 
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+#if !defined(CONFIG_TEGRA124)
+#error tegra_cpu_is_non_secure has only been validated on Tegra124
+#endif
+bool tegra_cpu_is_non_secure(void)
+{
+	/*
+	 * This register reads 0xffffffff in non-secure mode. This register
+	 * only implements bits 31:20, so the lower bits will always read 0 in
+	 * secure mode. Thus, the lower bits are an indicator for secure vs.
+	 * non-secure mode.
+	 */
+	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+	uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
+	return (mc_s_cfg0 & 1) == 1;
+}
+#endif
+
 /* Read the RAM size directly from the memory controller */
 unsigned int query_sdram_size(void)
 {
 	struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
-	u32 size_mb;
+	u32 emem_cfg, size_bytes;
 
-	size_mb = readl(&mc->mc_emem_cfg);
+	emem_cfg = readl(&mc->mc_emem_cfg);
 #if defined(CONFIG_TEGRA20)
-	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
-	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
+	size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
 #else
-	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
-	size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
+	/*
+	 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
+	 * and will wrap. Clip the reported size to the maximum that a 32-bit
+	 * variable can represent (rounded to a page).
+	 */
+	if (emem_cfg >= 4096) {
+		size_bytes = U32_MAX & ~(0x1000 - 1);
+	} else {
+		/* RAM size EMC is programmed to. */
+		size_bytes = emem_cfg * 1024 * 1024;
+		/*
+		 * If all RAM fits within 32-bits, it can be accessed without
+		 * LPAE, so go test the RAM size. Otherwise, we can't access
+		 * all the RAM, and get_ram_size() would get confused, so
+		 * avoid using it. There's no reason we should need this
+		 * validation step anyway.
+		 */
+		if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
+			size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
+						  size_bytes);
+	}
 #endif
 
 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
 	/* External memory limited to 2047 MB due to IROM/HI-VEC */
-	if (size_mb == SZ_2G) size_mb -= SZ_1M;
+	if (size_bytes == SZ_2G)
+		size_bytes -= SZ_1M;
 #endif
 
-	return size_mb;
+	return size_bytes;
 }
 
 int dram_init(void)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 11c7435..7c274b5 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -20,6 +20,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
 #include <div64.h>
@@ -573,7 +574,10 @@ void clock_init(void)
 	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
 
 	/* Do any special system timer/TSC setup */
-	arch_timer_init();
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+	if (!tegra_cpu_is_non_secure())
+#endif
+		arch_timer_init();
 }
 
 static void set_avp_clock_source(u32 src)
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 6e3ab0c..912f65e 100644
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -24,31 +24,59 @@
 #define pmux_pin_tristate_isvalid(tristate) \
 	(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 /* return 1 if a pin_io_is in range */
 #define pmux_pin_io_isvalid(io) \
 	(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 /* return 1 if a pin_lock is in range */
 #define pmux_pin_lock_isvalid(lock) \
 	(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 /* return 1 if a pin_od is in range */
 #define pmux_pin_od_isvalid(od) \
 	(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 /* return 1 if a pin_ioreset_is in range */
 #define pmux_pin_ioreset_isvalid(ioreset) \
 	(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
 	 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 /* return 1 if a pin_rcv_sel_is in range */
 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
 	(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
 	 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+/* return 1 if a pin_e_io_hv is in range */
+#define pmux_pin_e_io_hv_isvalid(e_io_hv) \
+	(((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
+	 ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+#define pmux_lpmd_isvalid(lpm) \
+	(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
+#define pmux_schmt_isvalid(schmt) \
+	(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
+#define pmux_hsm_isvalid(hsm) \
+	(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+#endif
 
 #define _R(offset)	(u32 *)(NV_PA_APB_MISC_BASE + (offset))
 
@@ -78,15 +106,34 @@
 
 #endif /* CONFIG_TEGRA20 */
 
-#define DRV_REG(group)	_R(0x868 + ((group) * 4))
+#define DRV_REG(group)	_R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
 
+/*
+ * We could force arch-tegraNN/pinmux.h to define all of these. However,
+ * that's a lot of defines, and for now it's manageable to just put a
+ * special case here. It's possible this decision will change with future
+ * SoCs.
+ */
+#ifdef CONFIG_TEGRA210
+#define IO_SHIFT	6
+#define LOCK_SHIFT	7
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+#define HSM_SHIFT	9
+#endif
+#define E_IO_HV_SHIFT	10
+#define OD_SHIFT	11
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+#define SCHMT_SHIFT	12
+#endif
+#else
 #define IO_SHIFT	5
 #define OD_SHIFT	6
 #define LOCK_SHIFT	7
 #define IO_RESET_SHIFT	8
 #define RCV_SEL_SHIFT	9
+#endif
 
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
 /* This register/field only exists on Tegra114 and later */
 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
 #define CLAMP_INPUTS_WHEN_TRISTATED 1
@@ -94,11 +141,15 @@
 void pinmux_set_tristate_input_clamping(void)
 {
 	u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
-	u32 val;
 
-	val = readl(reg);
-	val |= CLAMP_INPUTS_WHEN_TRISTATED;
-	writel(val, reg);
+	setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
+}
+
+void pinmux_clear_tristate_input_clamping(void)
+{
+	u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+
+	clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
 }
 #endif
 
@@ -176,7 +227,7 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
 	pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
 }
 
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 {
 	u32 *reg = REG(pin);
@@ -196,7 +247,9 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 		val &= ~(1 << IO_SHIFT);
 	writel(val, reg);
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 {
 	u32 *reg = REG(pin);
@@ -221,7 +274,9 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 {
 	u32 *reg = REG(pin);
@@ -243,7 +298,9 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 static void pinmux_set_ioreset(enum pmux_pingrp pin,
 				enum pmux_pin_ioreset ioreset)
 {
@@ -266,8 +323,9 @@ static void pinmux_set_ioreset(enum pmux_pingrp pin,
 
 	return;
 }
+#endif
 
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 				enum pmux_pin_rcv_sel rcv_sel)
 {
@@ -290,8 +348,82 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
 
 	return;
 }
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
+				enum pmux_pin_e_io_hv e_io_hv)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
+		return;
+
+	/* Error check on pin and e_io_hv */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
+
+	val = readl(reg);
+	if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
+		val |= (1 << E_IO_HV_SHIFT);
+	else
+		val &= ~(1 << E_IO_HV_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
+{
+	u32 *reg = REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (schmt == PMUX_SCHMT_NONE)
+		return;
+
+	/* Error check pad */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_schmt_isvalid(schmt));
+
+	val = readl(reg);
+	if (schmt == PMUX_SCHMT_ENABLE)
+		val |= (1 << SCHMT_SHIFT);
+	else
+		val &= ~(1 << SCHMT_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
+{
+	u32 *reg = REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (hsm == PMUX_HSM_NONE)
+		return;
+
+	/* Error check pad */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_hsm_isvalid(hsm));
+
+	val = readl(reg);
+	if (hsm == PMUX_HSM_ENABLE)
+		val |= (1 << HSM_SHIFT);
+	else
+		val &= ~(1 << HSM_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+#endif
 
 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 {
@@ -300,14 +432,29 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
 	pinmux_set_func(pin, config->func);
 	pinmux_set_pullupdown(pin, config->pull);
 	pinmux_set_tristate(pin, config->tristate);
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
 	pinmux_set_io(pin, config->io);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
 	pinmux_set_lock(pin, config->lock);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
 	pinmux_set_od(pin, config->od);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 	pinmux_set_ioreset(pin, config->ioreset);
-#ifdef TEGRA_PMX_HAS_RCV_SEL
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 	pinmux_set_rcv_sel(pin, config->rcv_sel);
 #endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+	pinmux_set_e_io_hv(pin, config->e_io_hv);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+	pinmux_set_schmt(pin, config->schmt);
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+	pinmux_set_hsm(pin, config->hsm);
 #endif
 }
 
@@ -320,7 +467,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 		pinmux_config_pingrp(&config[i]);
 }
 
-#ifdef TEGRA_PMX_HAS_DRVGRPS
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
 
@@ -330,19 +477,31 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define pmux_drv_isvalid(drv) \
 	(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
 
-#define pmux_lpmd_isvalid(lpm) \
-	(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
-
-#define pmux_schmt_isvalid(schmt) \
-	(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
-
-#define pmux_hsm_isvalid(hsm) \
-	(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
-
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 #define HSM_SHIFT	2
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 #define SCHMT_SHIFT	3
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 #define LPMD_SHIFT	4
 #define LPMD_MASK	(3 << LPMD_SHIFT)
+#endif
+/*
+ * Note that the following DRV* and SLW* defines are accurate for many drive
+ * groups on many SoCs. We really need a per-group data structure to solve
+ * this, since the fields are in different positions/sizes in different
+ * registers (for different groups).
+ *
+ * On Tegra30/114/124, the DRV*_SHIFT values vary.
+ * On Tegra30, the SLW*_SHIFT values vary.
+ * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
+ *   below are wide enough to cover the widest fields, and hopefully don't
+ *   interfere with any other fields.
+ * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
+ *   wide enough to cover all cases, since that would cause the field to
+ *   overlap with other fields in the narrower cases.
+ */
 #define DRVDN_SHIFT	12
 #define DRVDN_MASK	(0x7F << DRVDN_SHIFT)
 #define DRVUP_SHIFT	20
@@ -436,6 +595,7 @@ static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
 	return;
 }
 
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 {
 	u32 *reg = DRV_REG(grp);
@@ -456,7 +616,9 @@ static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 {
 	u32 *reg = DRV_REG(grp);
@@ -479,7 +641,9 @@ static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 {
 	u32 *reg = DRV_REG(grp);
@@ -502,6 +666,7 @@ static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 
 	return;
 }
+#endif
 
 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 {
@@ -511,9 +676,15 @@ static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 	pinmux_set_drvdn_slwr(grp, config->slwr);
 	pinmux_set_drvup(grp, config->drvup);
 	pinmux_set_drvdn(grp, config->drvdn);
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 	pinmux_set_lpmd(grp, config->lpmd);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 	pinmux_set_schmt(grp, config->schmt);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 	pinmux_set_hsm(grp, config->hsm);
+#endif
 }
 
 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,