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| author | Liu Gang <Gang.Liu@freescale.com> | 2012-10-14 20:55:17 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 15:52:46 -0500 |
| commit | 19e4a00965f03d5d64af00b7b4258dff43e57d17 (patch) | |
| tree | 3f796e643b234fc61637d1b0163efa5a27f34153 /arch | |
| parent | d8812bdbba21eefdf773ab3a42dcdf966d68ab92 (diff) | |
| download | u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.zip u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.tar.gz u-boot-imx-19e4a00965f03d5d64af00b7b4258dff43e57d17.tar.bz2 | |
powerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.
So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/srio.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 |
3 files changed, 8 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e82c951..736293c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -524,7 +524,7 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER char *s = getenv("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index d4f8ece..6e6f7dc 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -24,6 +24,7 @@ #include <asm/fsl_srio.h> #include <asm/errno.h> +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 @@ -32,6 +33,7 @@ #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ #define SRIO_LCSBA1CSR 0x60000000 +#endif #if defined(CONFIG_FSL_CORENET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 @@ -297,7 +299,7 @@ void srio_init(void) } } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7c81b..03baaee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,6 +334,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -365,6 +366,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -405,6 +407,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -436,6 +439,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 |