ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

9 files changed, 7 insertions, 121 deletions

diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index 7225a30..7e71ca0 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -301,6 +301,8 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
 	.control_ldosram_iva_voltage_ctrl	= 0x4A002320,
 	.control_ldosram_mpu_voltage_ctrl	= 0x4A002324,
 	.control_ldosram_core_voltage_ctrl	= 0x4A002328,
+	.control_usbotghs_ctrl			= 0x4A00233C,
+	.control_padconf_core_base		= 0x4A100000,
 	.control_pbiaslite			= 0x4A100600,
 	.control_lpddr2io1_0			= 0x4A100638,
 	.control_lpddr2io1_1			= 0x4A10063C,
@@ -312,4 +314,5 @@ struct omap_sys_ctrl_regs const omap4_ctrl = {
 	.control_lpddr2io2_3			= 0x4A100654,
 	.control_efuse_1			= 0x4A100700,
 	.control_efuse_2			= 0x4A100704,
+	.control_padconf_wkup_base		= 0x4A31E000,
 };
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 5010739..f3b3155 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -313,6 +313,7 @@ struct prcm_regs const omap5_es1_prcm = {
 struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
+	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,
 	.control_smart1io_padconf_0		= 0x4A002DA8,
@@ -361,6 +362,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
+	.control_padconf_wkup_base		= 0x4AE0C800,
 	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
 	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
 	.control_padconf_mode			= 0x4AE0CDA8,
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index ed7a1c8..f544edf 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -34,25 +34,6 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		0x4A004120
-#define CM_CLKMODE_DPLL_PER		0x4A008140
-#define CM_CLKMODE_DPLL_MPU		0x4A004160
-#define CM_CLKSEL_CORE			0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL		0
-#define CM_IDLEST_DPLL		0x4
-#define CM_AUTOIDLE_DPLL	0x8
-#define CM_CLKSEL_DPLL		0xC
-#define CM_DIV_M2_DPLL		0x10
-#define CM_DIV_M3_DPLL		0x14
-#define CM_DIV_M4_DPLL		0x18
-#define CM_DIV_M5_DPLL		0x1C
-#define CM_DIV_M6_DPLL		0x20
-#define CM_DIV_M7_DPLL		0x24
-
-#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
-
 /* CM_DLL_CTRL */
 #define CM_DLL_CTRL_OVERRIDE_SHIFT	0
 #define CM_DLL_CTRL_OVERRIDE_MASK	(1 << 0)
@@ -94,8 +75,6 @@
 #define CM_CLKSEL_DCC_EN_SHIFT			22
 #define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
 
-#define OMAP4_DPLL_MAX_N	127
-
 /* CM_SYS_CLKSEL */
 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
 
@@ -181,9 +160,7 @@
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
 
 /* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
-#define OMAP_32K_CLK_FREQ		32768
 
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
@@ -234,11 +211,6 @@
 
 #define ALTCLKSRC_MODE_ACTIVE		1
 
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
-
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 3a0bfbf..311c6ff 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -115,18 +115,6 @@ struct watchdog {
 #define WD_UNLOCK1		0xAAAA
 #define WD_UNLOCK2		0x5555
 
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define RESETDONE		(0x1 << 0)
-
 #define TCLR_ST			(0x1 << 0)
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 55a0760..66afd92 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -47,14 +47,6 @@
 #define DRAM_ADDR_SPACE_START	OMAP44XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END	OMAP44XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE	0x4A100638
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
@@ -79,15 +71,9 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE	(OMAP44XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE	0x4A002000
-
 /*
  * Hardware Register Details
  */
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 68afa76..6673a02 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -35,19 +35,6 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		(OMAP54XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER		(OMAP54XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU		(OMAP54XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE			(OMAP54XX_L4_CORE_BASE + 0x4100)
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL		0
-#define CM_IDLEST_DPLL		0x4
-#define CM_AUTOIDLE_DPLL	0x8
-#define CM_CLKSEL_DPLL		0xC
-
-#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
-
 /* CM_DLL_CTRL */
 #define CM_DLL_CTRL_OVERRIDE_SHIFT		0
 #define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
@@ -93,8 +80,6 @@
 #define CM_CLKSEL_DCC_EN_SHIFT			22
 #define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
 
-#define OMAP4_DPLL_MAX_N	127
-
 /* CM_SYS_CLKSEL */
 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
 
@@ -195,9 +180,7 @@
 #define RSTTIME1_MASK				(0x3ff << 0)
 
 /* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
-#define OMAP_32K_CLK_FREQ		32768
 
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
@@ -247,11 +230,6 @@
 #define TPS62361_BASE_VOLT_MV	500
 #define TPS62361_VSEL0_GPIO	7
 
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
-
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 044ab55..4753f46 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -119,18 +119,6 @@ struct watchdog {
 #define WD_UNLOCK1		0xAAAA
 #define WD_UNLOCK2		0x5555
 
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define RESETDONE		(0x1 << 0)
-
 #define TCLR_ST			(0x1 << 0)
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 1c1a64b..4fcd99f 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,16 +44,8 @@
 #define DRAM_ADDR_SPACE_START	OMAP54XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END	OMAP54XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE	(CTRL_BASE + 0x0800)
-#define CONTROL_PADCONF_WKUP	(OMAP54XX_L4_WKUP_BASE + 0xc800)
-
-/* LPDDR2 IO regs. To be verified */
-#define LPDDR2_IO_REGS_BASE	0x4A100638
-
 /* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+#define CONTROL_ID_CODE		0x4A002204
 
 /* To be verified */
 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
@@ -62,11 +54,6 @@
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
 
-/* STD_FUSE_PROD_ID_1 */
-#define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218)
-#define PROD_ID_1_SILICON_TYPE_SHIFT	16
-#define PROD_ID_1_SILICON_TYPE_MASK	(3 << 16)
-
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
@@ -80,15 +67,9 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE	(OMAP54XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE	0x4A002000
-
 /*
  * Hardware Register Details
  */
@@ -191,16 +172,6 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
 
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
-#define OMAP4430_ES1_0	0x44300100
-#define OMAP4430_ES2_0	0x44300200
-#define OMAP4430_ES2_1	0x44300210
-#define OMAP4430_ES2_2	0x44300220
-#define OMAP4430_ES2_3	0x44300230
-#define OMAP4460_ES1_0	0x44600100
-#define OMAP4460_ES1_1	0x44600110
-
 /* CONTROL_SRCOMP_XXX_SIDE */
 #define OVERRIDE_XS_SHIFT		30
 #define OVERRIDE_XS_MASK		(1 << 30)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index f8f3719..712d78b 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -367,6 +367,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ldosram_iva_voltage_ctrl;
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
+	u32 control_usbotghs_ctrl;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
@@ -555,9 +556,6 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
 	       u32 txdone, u32 txdone_mask, u32 opp);
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
-/* Max value for DPLL multiplier M */
-#define OMAP_DPLL_MAX_N	127
-
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL			0
 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1