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authorDan Murphy <dmurphy@ti.com>2013-10-11 12:28:17 -0500
committerMarek Vasut <marex@denx.de>2013-10-20 23:42:41 +0200
commit834e91af432479e3808e9cbd1d38199f724fc5aa (patch)
tree1ee55275e290c7b2bc4ec4523d8ad1ed1eba8d5b /arch
parentba55453ccf6d82c46b9f3eef5b958aac58adb6fb (diff)
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usb: dra7xx: Add support for dra7xx xhci USB host
Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c1
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h4
-rw-r--r--arch/arm/include/asm/omap_common.h1
3 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e6686fd..304ac1c 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -793,6 +793,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
.cm_clkmode_dpll_gmac = 0x4a0052a8,
+ .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 5cbbc44..8869b50 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -202,6 +202,10 @@
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR 0x12
#define SMPS_REG_ADDR_12_MPU 0x23
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index bea1835..8a395e8 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -144,6 +144,7 @@ struct prcm_regs {
u32 cm_ssc_deltamstep_dpll_unipro;
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy_core_clkctrl;
+ u32 cm_coreaon_usb_phy2_core_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;