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| author | Stefano Babic <sbabic@denx.de> | 2010-03-28 13:43:26 +0200 |
|---|---|---|
| committer | trix <trix@windriver.com> | 2010-04-17 20:52:44 -0500 |
| commit | 07739bcef5da07cc4a4edef8b91014ccc332eda3 (patch) | |
| tree | 0b1ce6764252af15dfb2614372de98a44a7ec61f /arch | |
| parent | 84a6e0d0f8465627f24c5baefa1f425c89b848cd (diff) | |
| download | u-boot-imx-07739bcef5da07cc4a4edef8b91014ccc332eda3.zip u-boot-imx-07739bcef5da07cc4a4edef8b91014ccc332eda3.tar.gz u-boot-imx-07739bcef5da07cc4a4edef8b91014ccc332eda3.tar.bz2 | |
Moved board specific values in config file
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S index 31af9e2..783c81f 100644 --- a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S +++ b/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S @@ -158,6 +158,7 @@ /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x000010C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -171,6 +172,7 @@ ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x000020C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] mov r3, #DP_OP_216 @@ -201,9 +203,10 @@ /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =0x59E35100 + ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ |