Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	include/configs/trats.h
	include/configs/trats2.h
	include/mmc.h

22 files changed, 299 insertions, 367 deletions

diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c
deleted file mode 100644
index ebd7575..0000000
--- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
-	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
-	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
-	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
-	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
-	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
-	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
-	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
-	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
-	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
-	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
-	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
-	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
-	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
-	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
-	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
-	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
-	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
-	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
-	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
deleted file mode 100644
index 5fe8fa2..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/mb86r0x.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* ddr2 controller */
-	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
-	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
-	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
-	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
-	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
-	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
-	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
-	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
-	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
-	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
-	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
-	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
-	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
-	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
-	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
-	/* clock reset generator */
-	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
-	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
-	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
-	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
-	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
-	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
-	/* chip control module */
-	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
-	/* external bus interface */
-	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
-	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
-	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
-	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
-	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
-	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
-	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
-	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
-	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
deleted file mode 100644
index 0e2e8bf..0000000
--- a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	/* Clock Control Module */
-	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
-	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
-	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
-
-	/* Enhanced SDRAM Controller */
-	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
-	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
-	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
deleted file mode 100644
index 629b727..0000000
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
-	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
-	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
-
-	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
-	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
-	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
-	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
-	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
-	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
-	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
-
-	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
-	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
-	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
-	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
-	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
-
-	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, gpcr));
-	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
-		offsetof(struct system_control_regs, fmcr));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 20e1e40..6c59494 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -74,7 +74,7 @@ u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
 %.sig: %.csf
 	$(call if_changed,mkcst_mxs)
 
-quiet_cmd_mkimage_mxs = UIMAGE  $@
+quiet_cmd_mkimage_mxs = MKIMAGE $@
 cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c
deleted file mode 100644
index ddb1898..0000000
--- a/arch/arm/cpu/armv7/mx5/asm-offsets.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/imx-regs.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-
-	/* Round up to make sure size gives nice stack alignment */
-	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
-	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
-	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
-	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
-	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
-	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
-	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
-	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
-	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
-	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
-	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
-	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
-	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
-	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
-	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
-	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
-	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
-	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
-	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
-	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
-	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
-	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
-	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
-	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
-	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
-	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
-	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
-	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
-	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
-	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
-	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
-	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
-	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
-	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
-#if defined(CONFIG_MX53)
-	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
-#endif
-
-	/* DPLL */
-	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
-	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
-	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
-	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
-	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
-	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
-	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
-	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
index 32ddbda..0e4b3fc 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -9,7 +9,7 @@
 
 # The AVP is ARMv4T architecture so we must use special compiler
 # flags for any startup files it might use.
-CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t
+CFLAGS_warmboot_avp.o += -march=armv4t
 
 obj-y	+= clock.o funcmux.o pinmux.o
 obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 025cfed..b04dfbb 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -32,7 +32,7 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,cpp_cfg)
 
-quiet_cmd_mkimage = UIMAGE  $@
+quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 2df4114..8543f43 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #if defined(CONFIG_TI816X)
 #define BOOT_DEVICE_XIP		2
diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
index 3e9e606..9aa3f4a 100644
--- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
+++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
@@ -151,6 +151,7 @@ struct davinci_mmc {
 	uint host_caps;		/* Host capabilities */
 	uint voltages;		/* Host supported voltages */
 	uint version;		/* MMC Controller version */
+	struct mmc_config cfg;
 };
 
 enum {
diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h
index 5aa5d2d..5afe0d4 100644
--- a/arch/arm/include/asm/arch-davinci/spl.h
+++ b/arch/arm/include/asm/arch-davinci/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NAND	1
 #define BOOT_DEVICE_SPI		2
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index bccce63..fdf73b5 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -25,8 +25,9 @@
 #define EXYNOS4_SYSTIMER_BASE		0x10050000
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
 #define EXYNOS4_TZPC_BASE		0x10110000
-#define EXYNOS4_MIU_BASE		0x10600000
 #define EXYNOS4_DMC_CTRL_BASE		0x10400000
+#define EXYNOS4_MIU_BASE		0x10600000
+#define EXYNOS4_ACE_SFR_BASE		0x10830000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
@@ -48,7 +49,6 @@
 #define EXYNOS4_GPIO_PART4_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
@@ -68,6 +68,7 @@
 #define EXYNOS4X12_TZPC_BASE		0x10110000
 #define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE		0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
 #define EXYNOS4X12_FIMD_BASE		0x11C00000
@@ -87,7 +88,6 @@
 #define EXYNOS4X12_I2S_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
@@ -106,7 +106,7 @@
 #define EXYNOS5_SYSREG_BASE		0x10050000
 #define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
-#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
index f87c137..d0efec2 100644
--- a/arch/arm/include/asm/arch-mx35/spl.h
+++ b/arch/arm/include/asm/arch-mx35/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h
index 2ec319c..8350532 100644
--- a/arch/arm/include/asm/arch-omap3/spl.h
+++ b/arch/arm/include/asm/arch-omap3/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h
index 551b27d..fb842a2 100644
--- a/arch/arm/include/asm/arch-omap4/spl.h
+++ b/arch/arm/include/asm/arch-omap4/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index 4a279cf..f707998 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE        0
 #define BOOT_DEVICE_XIP         1
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index b6896af..310bbd7 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -11,6 +11,9 @@
 
 #include <fdtdec.h>
 
+/* for mmc_config definition */
+#include <mmc.h>
+
 #define MAX_HOSTS		4	/* Max number of 'hosts'/controllers */
 
 #ifndef __ASSEMBLY__
@@ -138,6 +141,7 @@ struct mmc_host {
 	struct fdt_gpio_state wp_gpio;		/* Write Protect GPIO */
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
+	struct mmc_config cfg;	/* mmc configuration */
 };
 
 void pad_init_mmc(struct mmc_host *host);
diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
new file mode 100644
index 0000000..b0c26e5
--- /dev/null
+++ b/arch/arm/lib/asm-offsets.c
@@ -0,0 +1,248 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kbuild.h>
+
+#if defined(CONFIG_MB86R0x)
+#include <asm/arch/mb86r0x.h>
+#endif
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
+	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include <asm/arch/imx-regs.h>
+#endif
+
+int main(void)
+{
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct mb86r0x_ddr2
+	 *   - struct mb86r0x_memc
+	 *   - struct esdramc_regs
+	 *   - struct max_regs
+	 *   - struct aips_regs
+	 *   - struct aipi_regs
+	 *   - struct clkctl
+	 *   - struct dpll
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
+#if defined(CONFIG_MB86R0x)
+	/* ddr2 controller */
+	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+	/* clock reset generator */
+	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+	/* chip control module */
+	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+	/* external bus interface */
+	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+#endif
+
+#if defined(CONFIG_MX25)
+	/* Clock Control Module */
+	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+	/* Enhanced SDRAM Controller */
+	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+#endif
+
+#if defined(CONFIG_MX27)
+	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, gpcr));
+	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, fmcr));
+#endif
+
+#if defined(CONFIG_MX35)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
+	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
+	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
+	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
+	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
+	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
+	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
+	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
+	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
+	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+	/* DPLL */
+	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+#endif
+
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
deleted file mode 100644
index cfe52d1..0000000
--- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <common.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
-#ifdef CONFIG_FTSMC020
-	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
-	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
-#endif
-	BLANK();
-#ifdef CONFIG_FTAHBC020S
-	OFFSET(FTAHBC020S_SLAVE_BSR_4,	ftahbc02s, s_bsr[4]);
-	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
-	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
-#endif
-	BLANK();
-#ifdef CONFIG_FTPMU010
-	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
-#endif
-	BLANK();
-#ifdef CONFIG_FTSDMC021
-	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
-	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
-	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
-	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
-	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
-	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
-	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
-	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
-#endif
-	return 0;
-}
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/lib/asm-offsets.c
index 4769a95..39e3480 100644
--- a/arch/nds32/cpu/n1213/ag102/asm-offsets.c
+++ b/arch/nds32/lib/asm-offsets.c
@@ -15,16 +15,43 @@
 
 int main(void)
 {
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct ftahbc02s
+	 *   - struct ftsdmc021
+	 *   - struct andes_pcu
+	 *   - struct dwcddr21mctl
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
 #ifdef CONFIG_FTSMC020
 	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
 	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
 #endif
 	BLANK();
 #ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_4,	ftahbc02s, s_bsr[4]);
 	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
 	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
 #endif
 	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	BLANK();
 #ifdef CONFIG_ANDES_PCU
 	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */
 #endif
@@ -50,5 +77,6 @@ int main(void)
 	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */
 	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */
 #endif
+
 	return 0;
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 9a20b97..df44451 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -734,6 +734,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500
@@ -778,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER		2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+
 
 #elif defined(CONFIG_PPC_C29X)
 #define CONFIG_MAX_CPUS			1
diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/lib/asm-offsets.c
index d65c6ab..d65c6ab 100644
--- a/arch/x86/cpu/coreboot/asm-offsets.c
+++ b/arch/x86/lib/asm-offsets.c