cleanup: Fix typos and misspellings in various files.

Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams <mike@mikebwilliams.com>

22 files changed, 29 insertions, 29 deletions

diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
index b4dc4a6..bd6a5b1 100644
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
@@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
 	/* Command 16 to read aBlocks from the MMC/SD - caed */
 	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
 
-	/* The addres on the MMC/SD-card is in bytes,
+	/* The address on the MMC/SD-card is in bytes,
 	addr is transformed from blocks to bytes and the result is
 	placed into the command */
 
@@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
 	/* Command 24 to write a block to the MMC/SD - card */
 	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
 
-	/* The addres on the MMC/SD-card is in bytes,
+	/* The address on the MMC/SD-card is in bytes,
 	addr is transformed from blocks to bytes and the result is
 	placed into the command */
 
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 091b7d8..ecb92ef 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -274,7 +274,7 @@ _dynsym_start_ofs:
 
 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
 
-/* Interupt-Controller base addresses */
+/* Interrupt-Controller base addresses */
 INTMR1:		.word	0x80000280 @ 32 bit size
 INTMR2:		.word	0x80001280 @ 16 bit size
 INTMR3:		.word	0x80002280 @  8 bit size
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
index c321e28..91607b5 100644
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -59,7 +59,7 @@ int timer_init(void)
 	when the value in TC_RC is reached */
 	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
 
-	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
 	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
 
 	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 2a53667..0090f89 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -142,11 +142,11 @@ copyex:
 
 # if defined(CONFIG_S3C2400)
 #  define pWTCON	0x15300000
-#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
+#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
 #else
 #  define pWTCON	0x53000000
-#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
+#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
 #  define INTSUBMSK	0x4A00001C
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 # endif
diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
index 09f69ce..642e67a 100644
--- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
+++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
@@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId,
 				     &dispatchQInfo[qId].statusMask);
 
 
-    /* Set the interupt source is this queue is in the range 0-31 */
+    /* Set the interrupt source is this queue is in the range 0-31 */
     if (qId < IX_QMGR_MIN_QUEUPP_QID)
     {
 	ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
index 0ee4123..4e0de82 100644
--- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
+++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
@@ -279,7 +279,7 @@ typedef struct
     BOOL               portInitialized;
     UINT32 npeId; /**< NpeId for this port */
     IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
-    IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
+    IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
 } IxEthAccPortDataInfo; 
 
 extern IxEthAccPortDataInfo  ixEthAccPortData[];
diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
index 7427cc4..90669c2 100644
--- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h
+++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h
@@ -717,7 +717,7 @@ typedef struct
  */
 typedef struct
 {
-    UINT32  rxBitField;			/**< Recieved bit field */
+    UINT32  rxBitField;			/**< Received bit field */
     UINT32  atmCellHeader;		/**< ATM Cell Header */
     UINT32  rsvdWord0;                  /**< Reserved field */
     UINT16  currMbufLen;		/**< Mbuf Length */
diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
index 165ed96..03d7e07 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h
@@ -570,7 +570,7 @@ typedef enum
  * @brief Queue interrupt source select.
  *
  * This enum defines the different source conditions on a queue that result in
- * an interupt being fired by the AQM. Interrupt source is configurable for
+ * an interrupt being fired by the AQM. Interrupt source is configurable for
  * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
  * NE(Nearly Empty) status flag.
  *
diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
index f7194e7..b65d621 100644
--- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
+++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
@@ -404,7 +404,7 @@
 *
 * @def IX_ETH_ACC_RX_FRAME_ETH_Q 
 *
-* @brief  Eth0/Eth1 NPE Frame Recieve Q.
+* @brief  Eth0/Eth1 NPE Frame Receive Q.
 *
 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
 * 
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
index 61bce5f..14e9854 100644
--- a/arch/arm/cpu/lh7a40x/start.S
+++ b/arch/arm/cpu/lh7a40x/start.S
@@ -124,7 +124,7 @@ reset:
 	msr	cpsr,r0
 
 #define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interupt-Controller enable clear register */
+#define pINTENC		0x8000050C  /* Interrupt-Controller enable clear register */
 #define pCLKSET		0x80000420  /* clock divisor register */
 
 	/* disable watchdog, set watchdog control register to
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index c3acf7a..7223c47 100644
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -263,7 +263,7 @@ _dynsym_start_ofs:
  */
 
 
-/* Interupt-Controller base address */
+/* Interrupt-Controller base address */
 IC_BASE:	.word	0x90050000
 #define ICMR	0x04
 
diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h
index cecec59..e8cea45 100644
--- a/arch/m68k/include/asm/fec.h
+++ b/arch/m68k/include/asm/fec.h
@@ -39,7 +39,7 @@ typedef struct cpm_buf_desc {
 	uint cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY		((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY		((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */
diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
index 8302404..6a4a51a 100644
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ b/arch/powerpc/include/asm/cpm_8260.h
@@ -117,7 +117,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index a74a3a1..1681ecd 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -110,7 +110,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h
index dfd1532..e790963 100644
--- a/arch/powerpc/include/asm/ppc440ep_gr.h
+++ b/arch/powerpc/include/asm/ppc440ep_gr.h
@@ -182,7 +182,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -192,7 +192,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h
index 6c21472..c841f0f 100644
--- a/arch/powerpc/include/asm/ppc440epx_grx.h
+++ b/arch/powerpc/include/asm/ppc440epx_grx.h
@@ -398,7 +398,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -408,7 +408,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h
index 6f8581b..9924525 100644
--- a/arch/powerpc/include/asm/ppc440gx.h
+++ b/arch/powerpc/include/asm/ppc440gx.h
@@ -71,7 +71,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -81,7 +81,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
index 4387495..cc2ff68 100644
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -67,7 +67,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -77,7 +77,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h
index bad9a40..d59d7d2 100644
--- a/arch/powerpc/include/asm/ppc440spe.h
+++ b/arch/powerpc/include/asm/ppc440spe.h
@@ -83,7 +83,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -93,7 +93,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c
index 8f99e1d..b1269d2 100644
--- a/arch/sparc/cpu/leon3/usb_uhci.c
+++ b/arch/sparc/cpu/leon3/usb_uhci.c
@@ -70,7 +70,7 @@
  *
  * Interrupt Transfers.
  * --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 7ccc076..6c84c43 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -66,7 +66,7 @@ _start:
 	movw	%ax, %es
 	movw	%ax, %ss
 
-	/* Clear the interupt vectors */
+	/* Clear the interrupt vectors */
 	lidt	blank_idt_ptr
 
 	/* Early platform init (setup gpio, etc ) */
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index be52fe4..f33f8ed 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -32,7 +32,7 @@
 /* arch/x86/cpu/interrupts.c */
 void set_vector(u8 intnum, void *routine);
 
-/* arch/x86/lib/interupts.c */
+/* arch/x86/lib/interrupts.c */
 void disable_irq(int irq);
 void enable_irq(int irq);