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author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-06-03 16:57:47 +0530 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2015-06-12 12:43:07 -0400 |
commit | ee4dc2590f00d0109bcdb282ad86fd3dce567e50 (patch) | |
tree | 88256743f6d869b712cd0861f8937e657791d8b1 /arch | |
parent | 536d87470869c4c3257d70f387146703a2dee7c5 (diff) | |
download | u-boot-imx-ee4dc2590f00d0109bcdb282ad86fd3dce567e50.zip u-boot-imx-ee4dc2590f00d0109bcdb282ad86fd3dce567e50.tar.gz u-boot-imx-ee4dc2590f00d0109bcdb282ad86fd3dce567e50.tar.bz2 |
ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 3022b9e..cf4452d 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -146,7 +146,7 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, @@ -171,7 +171,7 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400B, |