diff options
author | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:24:54 +0200 |
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committer | Stefano Babic <sbabic@denx.de> | 2016-06-18 10:25:13 +0200 |
commit | dc557e9a1fe00ca9d884bd88feef5bebf23fede4 (patch) | |
tree | ec09fdf8f7c4c44e30f4b38b7459a2cbbb71d094 /arch | |
parent | d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4 (diff) | |
parent | 6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff) | |
download | u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.zip u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.gz u-boot-imx-dc557e9a1fe00ca9d884bd88feef5bebf23fede4.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
355 files changed, 18117 insertions, 11687 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index ec12013..566f044 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1,13 +1,6 @@ config CREATE_ARCH_SYMLINK bool -config HAVE_GENERIC_BOARD - bool - -config SYS_GENERIC_BOARD - bool - depends on HAVE_GENERIC_BOARD - choice prompt "Architecture select" default SANDBOX @@ -15,57 +8,39 @@ choice config ARC bool "ARC architecture" select HAVE_PRIVATE_LIBGCC - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config ARM bool "ARM architecture" select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC if !ARM64 - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config AVR32 bool "AVR32 architecture" select CREATE_ARCH_SYMLINK - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD config BLACKFIN bool "Blackfin architecture" - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD config M68K bool "M68000 architecture" select HAVE_PRIVATE_LIBGCC - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD config MICROBLAZE bool "MicroBlaze architecture" - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config MIPS bool "MIPS architecture" select HAVE_PRIVATE_LIBGCC - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config NDS32 bool "NDS32 architecture" - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD config NIOS2 bool "Nios II architecture" - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL select OF_CONTROL select DM @@ -77,14 +52,10 @@ config OPENRISC config PPC bool "PowerPC architecture" select HAVE_PRIVATE_LIBGCC - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config SANDBOX bool "Sandbox" - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL select DM select DM_SPI_FLASH @@ -99,15 +70,12 @@ config SH config SPARC bool "SPARC architecture" - select HAVE_GENERIC_BOARD select CREATE_ARCH_SYMLINK config X86 bool "x86 architecture" select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC - select HAVE_GENERIC_BOARD - select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL select DM select DM_SERIAL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b65d8e..e75c4c0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -64,6 +64,20 @@ config SYS_CPU default "sa1100" if CPU_SA1100 default "armv8" if ARM64 +config SYS_ARM_ARCH + int + default 4 if CPU_ARM720T + default 4 if CPU_ARM920T + default 5 if CPU_ARM926EJS + default 5 if CPU_ARM946ES + default 6 if CPU_ARM1136 + default 6 if CPU_ARM1176 + default 7 if CPU_V7 + default 7 if CPU_V7M + default 5 if CPU_PXA + default 4 if CPU_SA1100 + default 8 if ARM64 + config SEMIHOSTING bool "support boot from semihosting" help @@ -77,6 +91,14 @@ config SYS_L2CACHE_OFF If SoC does not support L2CACHE or one do not want to enable L2CACHE, choose this option. +config ENABLE_ARM_SOC_BOOT0_HOOK + bool "prepare BOOT0 header" + help + If the SoC's BOOT0 requires a header area filled with (magic) + values, then choose this option, and create a define called + ARM_SOC_BOOT0_HOOK which contains the required assembler + preprocessor code. + choice prompt "Target select" default TARGET_HIKEY @@ -339,6 +361,11 @@ config TARGET_RASTABAN select CPU_V7 select SUPPORT_SPL +config TARGET_ETAMIN + bool "Support etamin" + select CPU_V7 + select SUPPORT_SPL + config TARGET_PXM2 bool "Support pxm2" select CPU_V7 @@ -374,18 +401,20 @@ config TARGET_AM335X_EVM select DM_GPIO select TI_I2C_BOARD_DETECT -config TARGET_AM335X_SL50 - bool "Support am335x_sl50" +config TARGET_AM335X_SHC + bool "Support am335x based shc board from bosch" select CPU_V7 select SUPPORT_SPL select DM select DM_SERIAL + select DM_GPIO -config TARGET_AM43XX_EVM - bool "Support am43xx_evm" +config TARGET_AM335X_SL50 + bool "Support am335x_sl50" select CPU_V7 select SUPPORT_SPL - select TI_I2C_BOARD_DETECT + select DM + select DM_SERIAL config TARGET_BAV335X bool "Support bav335x" @@ -426,7 +455,6 @@ config TARGET_BCMNSP config ARCH_EXYNOS bool "Samsung EXYNOS" - select CPU_V7 select DM select DM_SPI_FLASH select DM_SERIAL @@ -456,6 +484,13 @@ config ARCH_KEYSTONE select SUPPORT_SPL select CMD_POWEROFF +config ARCH_MESON + bool "Amlogic Meson" + help + Support for the Meson SoC family developed by Amlogic Inc., + targeted at media players and tablet computers. We currently + support the S905 (GXBaby) 64-bit SoC. + config ARCH_MX7 bool "Freescale MX7" select CPU_V7 @@ -507,6 +542,17 @@ config OMAP54XX select CPU_V7 select SUPPORT_SPL +config AM43XX + bool "AM43XX SoC" + select CPU_V7 + select SUPPORT_SPL + help + Support for AM43xx SOC from Texas Instruments. + The AM43xx high performance SOC features a Cortex-A9 + ARM core, a quad core PRU-ICSS for industrial Ethernet + protocols, dual camera support, optional 3D graphics + and an optional customer programmable secure boot. + config RMOBILE bool "Renesas ARM SoCs" select CPU_V7 @@ -538,7 +584,16 @@ config TARGET_CM_T43 config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" + select CMD_BOOTZ + select CMD_DHCP + select CMD_EXT2 + select CMD_EXT4 + select CMD_FAT + select CMD_FS_GENERIC select CMD_GPIO + select CMD_MII + select CMD_MMC if MMC + select CMD_PING select CMD_USB select DM select DM_ETH @@ -546,6 +601,7 @@ config ARCH_SUNXI select DM_KEYBOARD select DM_SERIAL select DM_USB + select HUSH_PARSER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE @@ -594,6 +650,7 @@ config ARCH_ZYNQMP select DM select OF_CONTROL select DM_SERIAL + select SUPPORT_SPL config TEGRA bool "NVIDIA Tegra" @@ -673,6 +730,33 @@ config TARGET_HIKEY Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. +config TARGET_LS1012AQDS + bool "Support ls1012aqds" + select ARM64 + help + Support for Freescale LS1012AQDS platform. + The LS1012A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + +config TARGET_LS1012ARDB + bool "Support ls1012ardb" + select ARM64 + help + Support for Freescale LS1012ARDB platform. + The LS1012A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + +config TARGET_LS1012AFRDM + bool "Support ls1012afrdm" + select ARM64 + help + Support for Freescale LS1012AFRDM platform. + The LS1012A Freedom board (FRDM) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 @@ -743,6 +827,7 @@ config ARCH_ROCKCHIP config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" + select ARM64 select OF_CONTROL endchoice @@ -771,16 +856,14 @@ source "arch/arm/cpu/armv7/mx6/Kconfig" source "arch/arm/cpu/armv7/mx5/Kconfig" -source "arch/arm/cpu/armv7/omap3/Kconfig" - -source "arch/arm/cpu/armv7/omap4/Kconfig" - -source "arch/arm/cpu/armv7/omap5/Kconfig" +source "arch/arm/cpu/armv7/omap-common/Kconfig" source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/mach-meson/Kconfig" + source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" @@ -805,6 +888,7 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" +source "board/bosch/shc/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" @@ -831,6 +915,9 @@ source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" +source "board/freescale/ls1012aqds/Kconfig" +source "board/freescale/ls1012ardb/Kconfig" +source "board/freescale/ls1012afrdm/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d516345..6a07cd1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -11,7 +11,7 @@ endif arch-$(CONFIG_CPU_ARM720T) =-march=armv4 arch-$(CONFIG_CPU_ARM920T) =-march=armv4t arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te -arch-$(CONFIG_CPU_ARM946ES) =-march=armv4 +arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te arch-$(CONFIG_CPU_SA1100) =-march=armv4 arch-$(CONFIG_CPU_PXA) = arch-$(CONFIG_CPU_ARM1136) =-march=armv5 @@ -50,6 +50,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig new file mode 100644 index 0000000..dc51e9b --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/Kconfig @@ -0,0 +1,40 @@ +if AM43XX +config TARGET_AM43XX_EVM + bool "Support am43xx_evm" + select TI_I2C_BOARD_DETECT + help + This option specifies support for the AM43xx + GP and HS EVM development platforms.The AM437x + GP EVM is a standalone test, development, and + evaluation module system that enables developers + to write software and develop hardware around + an AM43xx processor subsystem. + +config ISW_ENTRY_ADDR + hex "Address in memory or XIP flash of bootloader entry point" + help + After any reset, the boot ROM on the AM43XX SOC + searches the boot media for a valid boot image. + For non-XIP devices, the ROM then copies the + image into internal memory. + For all boot modes, after the ROM processes the + boot image it eventually computes the entry + point address depending on the device type + (secure/non-secure), boot media (xip/non-xip) and + image headers. + default 0x402F4000 + +config PUB_ROM_DATA_SIZE + hex "Size in bytes of the L3 SRAM reserved by ROM to store data" + help + During the device boot, the public ROM uses the top of + the public L3 OCMC RAM to store r/w data like stack, + heap, globals etc. When the ROM is copying the boot + image from the boot media into memory, the image must + not spill over into this area. This value can be used + during compile time to determine the maximum size of a + boot image. Once the ROM transfers control to the boot + image, this area is no longer used, and can be reclaimed + for run time use by the boot image. + default 0x8400 +endif diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index aae3f09..6fda482 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -18,3 +18,5 @@ obj-y += ddr.o obj-y += emif4.o obj-y += board.o obj-y += mux.o + +obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c new file mode 100644 index 0000000..316e677 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c @@ -0,0 +1,104 @@ +/* + * clk-synthesizer.c + * + * Clock synthesizer apis + * + * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/arch/clk_synthesizer.h> +#include <i2c.h> + +/** + * clk_synthesizer_reg_read - Read register from synthesizer. + * @addr: addr within the i2c device + * buf: Buffer to which value is to be read. + * + * For reading the register from this clock synthesizer, a command needs to + * be send along with enabling byte read more, and then read can happen. + * Returns 0 on success + */ +static int clk_synthesizer_reg_read(int addr, uint8_t *buf) +{ + int rc; + + /* Enable Bye read */ + addr = addr | CLK_SYNTHESIZER_BYTE_MODE; + + /* Send the command byte */ + rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); + if (rc) + printf("Failed to send command to clock synthesizer\n"); + + /* Read the Data */ + return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1); +} + +/** + * clk_synthesizer_reg_write - Write a value to register in synthesizer. + * @addr: addr within the i2c device + * val: Value to be written in the addr. + * + * Enable the byte read mode in the address and start the i2c transfer. + * Returns 0 on success + */ +static int clk_synthesizer_reg_write(int addr, uint8_t val) +{ + uint8_t cmd[2]; + int rc = 0; + + /* Enable byte write */ + cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE; + cmd[1] = val; + + rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2); + if (rc) + printf("Clock synthesizer reg write failed at addr = 0x%x\n", + addr); + return rc; +} + +/** + * setup_clock_syntherizer - Program the clock synthesizer to get the desired + * frequency. + * @data: Data containing the desired output + * + * This is a PLL-based high performance synthesizer which gives 3 outputs + * as per the PLL_DIV and load capacitor programmed. + */ +int setup_clock_synthesizer(struct clk_synth *data) +{ + int rc; + uint8_t val; + + rc = i2c_probe(CLK_SYNTHESIZER_I2C_ADDR); + if (rc) { + printf("i2c probe failed at address 0x%x\n", + CLK_SYNTHESIZER_I2C_ADDR); + return rc; + } + + rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val); + if (val != data->id) + return rc; + + /* Crystal Load capacitor selection */ + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); + if (rc) + return rc; + rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3); + if (rc) + return rc; + + return 0; +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index 92142c8..7b841b2 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -159,3 +159,76 @@ void enable_basic_clocks(void) /* Select the Master osc 24 MHZ as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); } + +/* + * Enable Spread Spectrum for the MPU by calculating the required + * values and setting the registers accordingly. + * @param permille The spreading in permille (10th of a percent) + */ +void set_mpu_spreadspectrum(int permille) +{ + u32 multiplier_m; + u32 predivider_n; + u32 cm_clksel_dpll_mpu; + u32 cm_clkmode_dpll_mpu; + u32 ref_clock; + u32 pll_bandwidth; + u32 mod_freq_divider; + u32 exponent; + u32 mantissa; + u32 delta_m_step; + + printf("Enabling Spread Spectrum of %d permille for MPU\n", + permille); + + /* Read PLL parameter m and n */ + cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu); + multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF; + predivider_n = cm_clksel_dpll_mpu & 0x7F; + + /* + * Calculate reference clock (clock after pre-divider), + * its max. PLL bandwidth, + * and resulting mod_freq_divider + */ + ref_clock = V_OSCK / (predivider_n + 1); + pll_bandwidth = ref_clock / 70; + mod_freq_divider = ref_clock / (4 * pll_bandwidth); + + /* Calculate Mantissa/Exponent */ + exponent = 0; + mantissa = mod_freq_divider; + while ((mantissa > 127) && (exponent < 7)) { + exponent++; + mantissa /= 2; + } + if (mantissa > 127) + mantissa = 127; + + mod_freq_divider = mantissa << exponent; + + /* + * Calculate Modulation steps + * As we use Downspread only, the spread is twice the value of + * permille, so Div2! + * As it takes the value in percent, divide by ten! + */ + delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18; + delta_m_step /= 100; + delta_m_step /= mod_freq_divider; + if (delta_m_step > 0xFFFFF) + delta_m_step = 0xFFFFF; + + /* Setup Spread Spectrum */ + writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu); + writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu); + cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu); + /* clear all SSC flags */ + cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT); + /* enable SSC with Downspread only */ + cm_clkmode_dpll_mpu |= CM_CLKMODE_DPLL_SSC_EN_MASK | + CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK; + writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu); + while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000)) + ; +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 5c2a2ab..73ea955 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -160,7 +160,7 @@ void disable_edma3_clocks(void) } #endif -#ifdef CONFIG_USB_DWC3 +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) void enable_usb_clocks(int index) { u32 *usbclkctrl = 0; diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 5294d16..6d95d32 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -3,9 +3,29 @@ # # SPDX-License-Identifier: GPL-2.0+ # + +include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk + ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_TI_SECURE_DEVICE),y) +# +# For booting from SPI use +# u-boot-spl_HS_SPI_X-LOADER to program flash +# +# For booting spl from all other media +# use u-boot-spl_HS_ISSW +# +# Refer to README.ti-secure for more info +# +ALL-y += u-boot-spl_HS_ISSW +ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER +else ALL-y += MLO ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap +endif else +ifeq ($(CONFIG_TI_SECURE_DEVICE),y) +ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER +endif ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 1dfbf54..0289058 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -20,7 +20,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig new file mode 100644 index 0000000..7b39506 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/Kconfig @@ -0,0 +1,17 @@ +config TI_SECURE_DEVICE + bool "HS Device Type Support" + depends on OMAP54XX || AM43XX + help + If a high secure (HS) device type is being used, this config + must be set. This option impacts various aspects of the + build system (to create signed boot images that can be + authenticated) and the code. See the doc/README.ti-secure + file for further details. + +source "arch/arm/cpu/armv7/omap3/Kconfig" + +source "arch/arm/cpu/armv7/omap4/Kconfig" + +source "arch/arm/cpu/armv7/omap5/Kconfig" + +source "arch/arm/cpu/armv7/am33xx/Kconfig" diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0456263..8333b20 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -200,7 +200,7 @@ void spl_board_init(void) #endif } -int board_mmc_init(bd_t *bis) +__weak int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ef2ac98..2de9935 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, /* Dpll locked with ideal values for nominal opps. */ debug("\n %s Dpll already locked with ideal" "nominal opp values", dpll); + + bypass_dpll(base); goto setup_post_dividers; } } @@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, writel(temp, &dpll_regs->cm_clksel_dpll); +setup_post_dividers: + setup_post_dividers(base, params); + /* Lock */ if (lock) do_lock_dpll(base); -setup_post_dividers: - setup_post_dividers(base, params); - /* Wait till the DPLL locks */ if (lock) wait_for_lock(base); diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk new file mode 100644 index 0000000..c7bb101 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk @@ -0,0 +1,66 @@ +# +# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# +quiet_cmd_mkomapsecimg = MKIMAGE $@ +ifneq ($(TI_SECURE_DEV_PKG),) +ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) +ifneq ($(CONFIG_SPL_BUILD),) +cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ + $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +else +cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ + $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +endif +else +cmd_mkomapsecimg = echo "WARNING:" \ + "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \ + "$@ was NOT created!" +endif +else +cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ + "variable must be defined for TI secure devices. $@ was NOT created!" +endif + +# Standard X-LOADER target (QPSI, NOR flash) +u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For MLO targets (SD card boot) the final file name +# that is copied to the SD card fAT partition must +# be MLO, so we make a copy of the output file to a +# new file with that name +u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + @if [ -f $@ ]; then \ + cp -f $@ MLO; \ + fi + +# Standard 2ND target (certain peripheral boot modes) +u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# Standard ULO target (certain peripheral boot modes) +u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# Standard ISSW target (certain devices, various boot modes) +u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For SPI flash on AM335x and AM43xx, these +# require special byte swap handling so we use +# the SPI_X-LOADER target instead of X-LOADER +# and let the create-boot-image.sh script handle +# that +u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin + $(call if_changed,mkomapsecimg) + +# For supporting single stage XiP QSPI on AM43xx, the +# image is a full u-boot file, not an SPL. In this case +# the mkomapsecimg command looks for a u-boot-HS_* prefix +u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin + $(call if_changed,mkomapsecimg) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 01c2d57..2f9693f 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -65,12 +65,30 @@ static void omap_rev_string(void) u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4; + const char *sec_s; + + switch (get_device_type()) { + case TST_DEVICE: + sec_s = "TST"; + break; + case EMU_DEVICE: + sec_s = "EMU"; + break; + case HS_DEVICE: + sec_s = "HS"; + break; + case GP_DEVICE: + sec_s = "GP"; + break; + default: + sec_s = "?"; + } + if (soc_variant) printf("OMAP"); else printf("DRA"); - printf("%x ES%x.%x\n", omap_variant, major_rev, - minor_rev); + printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); } #ifdef CONFIG_SPL_BUILD @@ -94,6 +112,16 @@ void __weak do_board_detect(void) { } +/** + * vcores_init() - Assign omap_vcores based on board + * + * Function to pick the vcores based on board. This is expected to be + * overridden in the SoC family board file where desired. + */ +void __weak vcores_init(void) +{ +} + void s_init(void) { } @@ -131,6 +159,7 @@ void early_system_init(void) #endif setup_early_clocks(); do_board_detect(); + vcores_init(); prcm_init(); } diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c index 52ea734..2d03ebf 100644 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ b/arch/arm/cpu/armv7/omap-common/utils.c @@ -108,6 +108,6 @@ void omap_die_id_display(void) omap_die_id(die_id); - printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1], - die_id[2], die_id[3]); + printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2], + die_id[1], die_id[0]); } diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 0c44ea5..5f55977 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -280,6 +280,8 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg omap_nand_switch_ecc(1, 1); else if (strncmp(argv[2], "bch8", 4) == 0) omap_nand_switch_ecc(1, 8); + else if (strncmp(argv[2], "bch16", 5) == 0) + omap_nand_switch_ecc(1, 16); else goto usage; } @@ -308,8 +310,8 @@ usage: U_BOOT_CMD( nandecc, 3, 1, do_switch_ecc, "switch OMAP3 NAND ECC calculation algorithm", - "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and" - " 8-bit BCH\n" + "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming" + " and 8-bit/16-bit BCH\n" " ecc calculation (second parameter may" " be omitted).\n" "nandecc sw - Switch to NAND software ecc algorithm." diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index f2930d5..3caba86 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -12,4 +12,5 @@ obj-y += sdram.o obj-y += prcm-regs.o obj-y += hw_data.o obj-y += abb.o +obj-y += fdt.o obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk index ef2725a..a7e55a5 100644 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -6,8 +6,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +include $(srctree)/$(CPUDIR)/omap-common/config_secure.mk + ifdef CONFIG_SPL_BUILD +ifeq ($(CONFIG_TI_SECURE_DEVICE),y) +ALL-y += u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER +else ALL-y += MLO +endif else ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c new file mode 100644 index 0000000..0493cd1 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/fdt.c @@ -0,0 +1,184 @@ +/* + * Copyright 2016 Texas Instruments, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <malloc.h> + +#include <asm/omap_common.h> +#include <asm/arch-omap5/sys_proto.h> + +#ifdef CONFIG_TI_SECURE_DEVICE + +/* Give zero values if not already defined */ +#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0) +#endif +#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ +#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0) +#endif + +static u32 hs_irq_skip[] = { + 8, /* Secure violation reporting interrupt */ + 15, /* One interrupt for SDMA by secure world */ + 118 /* One interrupt for Crypto DMA by secure world */ +}; + +static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + int len, i, old_cnt, new_cnt; + u32 *temp; + const u32 *p_data; + + /* + * Increase the size of the fdt + * so we have some breathing room + */ + ret = fdt_increase_size(fdt, 512); + if (ret < 0) { + printf("Could not increase size of device tree: %s\n", + fdt_strerror(ret)); + return ret; + } + + /* Reserve IRQs that are used/needed by secure world */ + path = "/ocp/crossbar"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + + /* Get current entries */ + p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len); + if (p_data) + old_cnt = len / sizeof(u32); + else + old_cnt = 0; + + new_cnt = sizeof(hs_irq_skip) / + sizeof(hs_irq_skip[0]); + + /* Create new/updated skip list for HS parts */ + temp = malloc(sizeof(u32) * (old_cnt + new_cnt)); + for (i = 0; i < new_cnt; i++) + temp[i] = cpu_to_fdt32(hs_irq_skip[i]); + for (i = 0; i < old_cnt; i++) + temp[i + new_cnt] = p_data[i]; + + /* Blow away old data and set new data */ + fdt_delprop(fdt, offs, "ti,irqs-skip"); + ret = fdt_setprop(fdt, offs, "ti,irqs-skip", + temp, + (old_cnt + new_cnt) * sizeof(u32)); + free(temp); + + /* Check if the update worked */ + if (ret < 0) { + printf("Could not add ti,irqs-skip property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + + return 0; +} + +static int ft_hs_disable_rng(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + + /* Make HW RNG reserved for secure world use */ + path = "/ocp/rng"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + ret = fdt_setprop_string(fdt, offs, + "status", "disabled"); + if (ret < 0) { + printf("Could not add status property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + return 0; +} + +#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \ + (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0)) +static int ft_hs_fixup_sram(void *fdt, bd_t *bd) +{ + const char *path; + int offs; + int ret; + u32 temp[2]; + + /* + * Update SRAM reservations on secure devices. The OCMC RAM + * is always reserved for secure use from the start of that + * memory region + */ + path = "/ocp/ocmcram@40300000/sram-hs"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + debug("Node %s not found.\n", path); + return 0; + } + + /* relative start offset */ + temp[0] = cpu_to_fdt32(0); + /* reservation size */ + temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ, + CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ)); + fdt_delprop(fdt, offs, "reg"); + ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32)); + if (ret < 0) { + printf("Could not add reg property to node %s: %s\n", + path, fdt_strerror(ret)); + return ret; + } + + return 0; +} +#else +static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; } +#endif + +static void ft_hs_fixups(void *fdt, bd_t *bd) +{ + /* Check we are running on an HS/EMU device type */ + if (GP_DEVICE != get_device_type()) { + if ((ft_hs_fixup_crossbar(fdt, bd) == 0) && + (ft_hs_disable_rng(fdt, bd) == 0) && + (ft_hs_fixup_sram(fdt, bd) == 0)) + return; + } else { + printf("ERROR: Incorrect device type (GP) detected!"); + } + /* Fixup failed or wrong device type */ + hang(); +} +#else +static void ft_hs_fixups(void *fdt, bd_t *bd) +{ +} +#endif + +/* + * Place for general cpu/SoC FDT fixups. Board specific + * fixups should remain in the board files which is where + * this function should be called from. + */ +void ft_cpu_setup(void *fdt, bd_t *bd) +{ + ft_hs_fixups(fdt, bd); +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 88e8920..5b91446a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -365,35 +365,35 @@ struct vcores_data omap5430_volts_es2 = { }; struct vcores_data dra752_volts = { - .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS7, .core.pmic = &tps659038, - .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8, .iva.pmic = &tps659038, @@ -401,15 +401,15 @@ struct vcores_data dra752_volts = { }; struct vcores_data dra722_volts = { - .mpu.value = VDD_MPU_DRA72x, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS65917_REG_ADDR_SMPS1, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - .core.value = VDD_CORE_DRA72x, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS65917_REG_ADDR_SMPS2, .core.pmic = &tps659038, @@ -418,22 +418,22 @@ struct vcores_data dra722_volts = { * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. */ - .gpu.value = VDD_GPU_DRA72x, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS65917_REG_ADDR_SMPS3, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - .eve.value = VDD_EVE_DRA72x, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS65917_REG_ADDR_SMPS3, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - .iva.value = VDD_IVA_DRA72x, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS65917_REG_ADDR_SMPS3, .iva.pmic = &tps659038, @@ -602,7 +602,7 @@ void disable_edma3_clocks(void) } #endif -#ifdef CONFIG_USB_DWC3 +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) void enable_usb_clocks(int index) { u32 cm_l3init_usb_otg_ss_clkctrl = 0; @@ -614,9 +614,14 @@ void enable_usb_clocks(int index) setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, OPTFCLKEN_REFCLK960M); - /* Enable 32 KHz clock for dwc3 */ + /* Enable 32 KHz clock for USB_PHY1 */ setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Enable 32 KHz clock for USB_PHY3 */ + if (is_dra7xx()) + setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); } else if (index == 1) { cm_l3init_usb_otg_ss_clkctrl = (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; @@ -664,9 +669,14 @@ void disable_usb_clocks(int index) clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, OPTFCLKEN_REFCLK960M); - /* Disable 32 KHz clock for dwc3 */ + /* Disable 32 KHz clock for USB_PHY1 */ clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Disable 32 KHz clock for USB_PHY3 */ + if (is_dra7xx()) + clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); } else if (index == 1) { cm_l3init_usb_otg_ss_clkctrl = (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 655e92b..b5f1d70 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_gmac = 0x4a0052a8, .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, + .cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698, .cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0, /* cm1.mpu */ diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 949abb1..b63036c 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -12,6 +12,9 @@ #include <asm/io.h> #include <asm/arch/pwm.h> #include <asm/arch/clk.h> + +/* Use the old PWM interface for now */ +#undef CONFIG_DM_PWM #include <pwm.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index a9f4fec..46f25e6 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -14,15 +14,15 @@ #include <linux/linkage.h> /* - * void __asm_flush_dcache_level(level) + * void __asm_dcache_level(level) * - * clean and invalidate one level cache. + * flush or invalidate one level cache. * * x0: cache level - * x1: 0 flush & invalidate, 1 invalidate only + * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ -ENTRY(__asm_flush_dcache_level) +ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ @@ -57,14 +57,14 @@ loop_way: b.ge loop_set ret -ENDPROC(__asm_flush_dcache_level) +ENDPROC(__asm_dcache_level) /* * void __asm_flush_dcache_all(int invalidate_only) * - * x0: 0 flush & invalidate, 1 invalidate only + * x0: 0 clean & invalidate, 1 invalidate only * - * clean and invalidate all data cache by SET/WAY. + * flush or invalidate all data cache by SET/WAY. */ ENTRY(__asm_dcache_all) mov x1, x0 @@ -87,7 +87,7 @@ loop_level: and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0 @@ -104,19 +104,13 @@ finished: ENDPROC(__asm_dcache_all) ENTRY(__asm_flush_dcache_all) - mov x16, lr mov x0, #0 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) ENTRY(__asm_invalidate_dcache_all) - mov x16, lr mov x0, #0x1 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) /* diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5f86ef9..eb2cbc3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,3 +28,7 @@ endif ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif + +ifneq ($(CONFIG_LS1012A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d939900..9a5a6b5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -396,9 +396,6 @@ static inline void final_mmu_setup(void) flush_dcache_range((ulong)level0_table, (ulong)level0_table + gd->arch.tlb_size); -#ifdef CONFIG_SYS_DPAA_FMAN - flush_dcache_all(); -#endif /* point TTBR to the new table */ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index a6ef830..a6ef830 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index f9323c1..f9323c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc new file mode 100644 index 0000000..8eee016 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -0,0 +1,129 @@ +SoC overview + + 1. LS1043A + 2. LS2080A + 3. LS1012A + +LS1043A +--------- +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Ethernet interfaces by FMan + - Up to 1 x XFI supporting 10G interface + - Up to 1 x QSGMII + - Up to 4 x SGMII supporting 1000Mbps + - Up to 2 x SGMII supporting 2500Mbps + - Up to 2 x RGMII supporting 1000Mbps + - High-speed peripheral interfaces + - Three PCIe 2.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 + +LS2080A +-------- +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 +processor cores with high-performance data path acceleration logic and network +and peripheral bus interfaces required for networking, telecom/datacom, +wireless infrastructure, and mil/aerospace applications. + +The LS2080A SoC includes the following function and features: + + - Eight 64-bit ARM Cortex-A57 CPUs + - 1 MB platform cache with ECC + - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support + - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by + the AIOP + - Data path acceleration architecture (DPAA2) incorporating acceleration for + the following functions: + - Packet parsing, classification, and distribution (WRIOP) + - Queue and Hardware buffer management for scheduling, packet sequencing, and + congestion management, buffer allocation and de-allocation (QBMan) + - Cryptography acceleration (SEC) at up to 10 Gbps + - RegEx pattern matching acceleration (PME) at up to 10 Gbps + - Decompression/compression acceleration (DCE) at up to 20 Gbps + - Accelerated I/O processing (AIOP) at up to 20 Gbps + - QDMA engine + - 16 SerDes lanes at up to 10.3125 GHz + - Ethernet interfaces + - Up to eight 10 Gbps Ethernet MACs + - Up to eight 1 / 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCIe 3.0 controllers, one supporting SR-IOV + - Additional peripheral interfaces + - Two serial ATA (SATA 3.0) controllers + - Two high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Serial peripheral interface (SPI) controller + - Quad Serial Peripheral Interface (QSPI) Controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash + - Support for hardware virtualization and partitioning enforcement + - QorIQ platform's trust architecture 3.0 + - Service processor (SP) provides pre-boot initialization and secure-boot + capabilities + +LS1012A +-------- +The LS1012A features an advanced 64-bit ARM v8 Cortex- +A53 processor, with 32 KB of parity protected L1-I cache, +32 KB of ECC protected L1-D cache, as well as 256 KB of +ECC protected L2 cache. + +The LS1012A SoC includes the following function and features: + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: + - ARM v8 cryptography extensions + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports + 16-/8-bit operation (no ECC support) + - ARM core-link CCI-400 cache coherent interconnect + - Packet Forwarding Engine (PFE) + - Cryptography acceleration (SEC) + - Ethernet interfaces supported by PFE: + - One Configurable x3 SerDes: + Two Serdes PLLs supported for usage by any SerDes data lane + Support for up to 6 GBaud operation + - High-speed peripheral interfaces: + - One PCI Express Gen2 controller, supporting x1 operation + - One serial ATA (SATA Gen 3.0) controller + - One USB 3.0/2.0 controller with integrated PHY + - One USB 2.0 controller with ULPI interface. . + - Additional peripheral interfaces: + - One quad serial peripheral interface (QuadSPI) controller + - One serial peripheral interface (SPI) controller + - Two enhanced secure digital host controllers + - Two I2C controllers + - One 16550 compliant DUART (two UART interfaces) + - Two general purpose IOs (GPIO) + - Two FlexTimers + - Five synchronous audio interfaces (SAI) + - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading + - Single-source clocking solution enabling generation of core, platform, + DDR, SerDes, and USB clocks from a single external crystal and internal + crystaloscillator + - Thermal monitor unit (TMU) with +/- 3C accuracy + - Two WatchDog timers + - ARM generic timer + - QorIQ platform's trust architecture 2.1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1e875c4..d17227a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -20,6 +20,8 @@ #ifdef CONFIG_MP #include <asm/arch/mp.h> #endif +#include <fsl_sec.h> +#include <asm/arch-fsl-layerscape/soc.h> int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -75,6 +77,23 @@ void ft_fixup_cpu(void *blob) void ft_cpu_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_LSCH2 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr = in_be32(&gur->svr); + + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif +#endif + #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 453a93d..3a77b21 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info) struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif -#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN) +#if (defined(CONFIG_FSL_ESDHC) &&\ + defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ + defined(CONFIG_SYS_DPAA_FMAN) + u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -56,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus = sysclk; #endif +#ifdef CONFIG_LS1012A + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; +#else sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; +#endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; @@ -80,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } +#ifdef CONFIG_LS1012A + sys_info->freq_systembus = sys_info->freq_ddrbus / 2; + sys_info->freq_ddrbus *= 2; +#endif + #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 04831ca..5af6b73 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -94,11 +94,13 @@ ENTRY(lowlevel_init) bl ccn504_set_qos #endif +#ifdef SMMU_BASE /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ str w0, [x1, #0x10] +#endif /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) @@ -181,6 +183,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) +#ifdef CONFIG_FSL_LSCH3 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -258,6 +261,7 @@ ENTRY(__asm_flush_l3_cache) mov lr, x29 ret ENDPROC(__asm_flush_l3_cache) +#endif #ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c new file mode 100644 index 0000000..ff0903c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -0,0 +1,74 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/immap_lsch2.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} }, + {0x0008, {NONE, NONE, NONE, SATA1} }, + {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} }, + {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} }, + {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {0x9508, {TX_CLK, PCIE1, NONE, SATA1} }, + {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} }, + {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0cb0100..dd633f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,10 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_SYS_FSL_DDR +#include <fsl_ddr_sdram.h> +#include <fsl_ddr.h> +#endif #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif @@ -222,7 +226,7 @@ int sata_init(void) } #endif -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_FSL_LSCH2) #ifdef CONFIG_SCSI_AHCI_PLAT int sata_init(void) { @@ -271,6 +275,39 @@ static void erratum_a009660(void) #endif } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -295,6 +332,7 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ + erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index c1229c8..5883c00 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif @@ -49,9 +49,6 @@ void board_init_f(ulong dummy) #ifdef CONFIG_LS2080A arch_cpu_init(); #endif -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2080A diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 9efcc5a..079e250 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -8,6 +8,7 @@ #include <config.h> #include <version.h> #include <asm/macro.h> +#include <asm/psci.h> #include <asm/system.h> /* @@ -73,3 +74,18 @@ void smc_call(struct pt_regs *args) "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); } + +void __noreturn psci_system_reset(bool conduit_smc) +{ + struct pt_regs regs; + + regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET; + + if (conduit_smc) + smc_call(®s); + else + hvc_call(®s); + + while (1) + ; +} diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e933021..c1a2f45 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -21,6 +21,16 @@ _start: b reset +#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK +/* + * Various SoCs need something special and SoC-specific up front in + * order to boot, allow them to set that in their boot0.h file and then + * use it here. + */ +#include <asm/arch/boot0.h> +ARM_SOC_BOOT0_HOOK +#endif + .align 3 .globl _TEXT_BASE diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index d0ed222..be8673a 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -9,3 +9,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-y += slcr.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 5dd3cd8..509f0aa 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -63,6 +63,11 @@ static struct mm_region zynqmp_mem_map[] = { }; struct mm_region *mem_map = zynqmp_mem_map; +u64 get_page_table_size(void) +{ + return 0x14000; +} + static unsigned int zynqmp_get_silicon_version_secure(void) { u32 ver; diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c new file mode 100644 index 0000000..e3e2a4f --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -0,0 +1,107 @@ +/* + * Copyright 2015 - 2016 Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> + +#include <asm/io.h> +#include <asm/spl.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +void board_init_f(ulong dummy) +{ + psu_init(); + board_early_init_r(); + +#ifdef CONFIG_DEBUG_UART + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ +#endif + /* Delay is required for clocks to be propagated */ + udelay(1000000); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* No need to call timer init - it is empty for ZynqMP */ + board_init_r(NULL, 0); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + preloader_console_init(); + board_init(); +} +#endif + +u32 spl_boot_device(void) +{ + u32 reg = 0; + u8 bootmode; + + reg = readl(&crlapb_base->boot_mode); + bootmode = reg & BOOT_MODES_MASK; + + switch (bootmode) { + case JTAG_MODE: + return BOOT_DEVICE_RAM; +#ifdef CONFIG_SPL_MMC_SUPPORT + case EMMC_MODE: + case SD_MODE: + case SD_MODE1: + return BOOT_DEVICE_MMC1; +#endif + default: + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_RAM: + return 0; + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +__weak void psu_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d1f8e22..a827613 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -21,11 +21,14 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5420-peach-pit.dtb \ exynos5800-peach-pi.dtb \ exynos5422-odroidxu3.dtb +dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ rk3288-jerry.dtb \ rk3288-rock2-square.dtb \ rk3036-sdk.dtb +dtb-$(CONFIG_ARCH_MESON) += \ + meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -45,6 +48,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra186-p2771-0000.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ @@ -88,9 +92,15 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb -dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb -dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb +dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-bonegreen.dtb \ + am335x-icev2.dtb +dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ + am43x-epos-evm.dtb \ + am437x-idk-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ @@ -100,7 +110,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb + socfpga_cyclone5_sr1500.dtb \ + socfpga_cyclone5_vining_fpga.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb @@ -113,7 +124,10 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ - fsl-ls1043a-rdb.dtb + fsl-ls1043a-rdb.dtb \ + fsl-ls1012a-qds.dtb \ + fsl-ls1012a-rdb.dtb \ + fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb @@ -218,7 +232,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN50I) += \ - pine64_plus.dtb + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index fec7834..40a3c35 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -13,6 +13,11 @@ }; }; + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ @@ -383,8 +388,7 @@ bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; - cd-inverted; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &aes { diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts index 81441cc..6b84937 100644 --- a/arch/arm/dts/am335x-bone.dts +++ b/arch/arm/dts/am335x-bone.dts @@ -13,9 +13,6 @@ / { model = "TI AM335x BeagleBone"; compatible = "ti,am335x-bone", "ti,am33xx"; - chosen { - stdout-path = &uart0; - }; }; &ldo3_reg { diff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts new file mode 100644 index 0000000..9c59da9 --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen.dts @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" + +/ { + model = "TI AM335x BeagleBone Green"; + compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&am33xx_pinmux { + uart2_pins: uart2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ + AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&rtc { + system-power-controller; +}; diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index c0bc2af..a6f20af 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -717,7 +717,7 @@ bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &mmc3 { diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts new file mode 100644 index 0000000..b3e9b61 --- /dev/null +++ b/arch/arm/dts/am335x-evmsk.dts @@ -0,0 +1,720 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x Starter Kit + * http://www.ti.com/tool/tmdssk3358 + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM335x EVM-SK"; + compatible = "ti,am335x-evmsk", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lis3_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lis3_reg"; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator@2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 29 0>; + startup-delay-us = <70000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@1 { + label = "evmsk:green:usr0"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "evmsk:green:usr1"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "evmsk:green:mmc0"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "evmsk:green:heartbeat"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + gpio_buttons: gpio_buttons@0 { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + switch@1 { + label = "button0"; + linux,code = <0x100>; + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + switch@2 { + label = "button1"; + linux,code = <0x101>; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; + + switch@3 { + label = "button2"; + linux,code = <0x102>; + gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + switch@4 { + label = "button3"; + linux,code = <0x103>; + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <8>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM335x-EVMSK"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24000000>; + }; + }; + + panel { + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + status = "okay"; + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; + }; + display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + + lcd_pins_default: lcd_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + lcd_pins_sleep: lcd_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ + AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ + AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ + AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ + AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ + AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ + AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ + AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ + AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ + AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ + AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ + >; + }; + + gpio_keys_s0: gpio_keys_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ + AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; + + ecap2_pins: backlight_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + + /* Slave 2 */ + AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ + AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ + >; + }; + + mcasp1_pins_sleep: mcasp1_pins_sleep { + pinctrl-single,pins = < + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; + + lis331dlh: lis331dlh@18 { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x18>; + Vdd-supply = <&lis3_reg>; + Vdd_IO-supply = <&lis3_reg>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <120>; + st,min-limit-y = <120>; + st,min-limit-z = <140>; + st,max-limit-x = <550>; + st,max-limit-y = <550>; + st,max-limit-z = <750>; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vaux2_reg>; + IOVDD-supply = <&vaux2_reg>; + DRVDD-supply = <&vaux2_reg>; + DVDD-supply = <&vbat>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&epwmss2 { + status = "okay"; + + ecap2: ecap@48304100 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + ti,non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ + ref-clock-frequency = <38400000>; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_pins_sleep>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; +}; + +&lcdc { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts new file mode 100644 index 0000000..debc6f6 --- /dev/null +++ b/arch/arm/dts/am335x-icev2.dts @@ -0,0 +1,430 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "TI AM3359 ICE-V2"; + compatible = "ti,am3359-icev2", "ti,am33xx"; + + chosen { + stdout-path = &uart3; + tick-timer = &timer2; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds@0 { + compatible = "gpio-leds"; + + led@0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Tricolor status LEDs */ + leds@1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led@0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led@1 { + label = "status0:green:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "status0:yellow:usr"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "status1:red:mmc0"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led@4 { + label = "status1:green:usr"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + user_leds: user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + >; + }; + + mmc0_pins_default: mmc0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ + >; + }; + + i2c0_pins_default: i2c0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; + + spi0_pins_default: spi0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1, RMII mode */ + AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */ + AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */ + AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */ + /* Slave 2, RMII mode */ + AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */ + AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */ + AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */ + AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */ + AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */ + AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */ + AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */ + AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + + /* Slave 2 reset value */ + AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + + status = "okay"; + clock-frequency = <400000>; + + tps: power-controller@2d { + reg = <0x2d>; + }; + + tpic2810: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1326000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; +}; + +&gpio0 { + /* Do not idle the GPIO used for holding the VTT regulator */ + ti,no-reset-on-init; + ti,no-idle-on-init; + + p7 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FET_SWITCH_CTRL"; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; + status = "okay"; +}; + +&gpio3 { + p4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PR1_MII_CTRL"; + }; + + p10 { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MUX_MII_CTRL"; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; + dual_emac; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ +}; diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index c95d1d3..3ffa8e0 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -547,6 +547,7 @@ active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; + syscon = <&scm_conf>; ranges; davinci_mdio: mdio@4a101000 { diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts new file mode 100644 index 0000000..478f0a6 --- /dev/null +++ b/arch/arm/dts/am437x-idk-evm.dts @@ -0,0 +1,420 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "TI AM437x Industrial Development Kit"; + compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + v24_0d: fixed-regulator-v24_0d { + compatible = "regulator-fixed"; + regulator-name = "V24_0D"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + regulator-boot-on; + }; + + v3_3d: fixed-regulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "V3_3D"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + vdd_corereg: fixed-regulator-vdd_corereg { + compatible = "regulator-fixed"; + regulator-name = "VDD_COREREG"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + vdd_core: fixed-regulator-vdd_core { + compatible = "regulator-fixed"; + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_corereg>; + }; + + v1_8dreg: fixed-regulator-v1_8dreg{ + compatible = "regulator-fixed"; + regulator-name = "V1_8DREG"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + v1_8d: fixed-regulator-v1_8d{ + compatible = "regulator-fixed"; + regulator-name = "V1_8D"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v1_8dreg>; + }; + + v1_5dreg: fixed-regulator-v1_5dreg{ + compatible = "regulator-fixed"; + regulator-name = "V1_5DREG"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v24_0d>; + }; + + v1_5d: fixed-regulator-v1_5d{ + compatible = "regulator-fixed"; + regulator-name = "V1_5D"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&v1_5dreg>; + }; + + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + label = "power-button"; + linux,code = <KEY_POWER>; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; + + /* fixed 32k external oscillator clock */ + clk_32k_rtc: clk_32k_rtc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; +}; + +&am43xx_pinmux { + gpio_keys_pins_default: gpio_keys_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ + >; + }; + + i2c0_pins_default: i2c0_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c0_pins_sleep: i2c0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c2_pins_default: i2c2_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ + AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ + >; + }; + + i2c2_pins_sleep: i2c2_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: pinmux_mmc1_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + ecap0_pins_default: backlight_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ + AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + qspi_pins_default: qspi_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ + AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ + AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ + AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ + AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */ + AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ + >; + }; + + qspi_pins_sleep: qspi_pins_sleep{ + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-1 = <&i2c0_pins_sleep>; + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + tps: tps62362@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1330000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + vin-supply = <&v3_3d>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_default>; + pinctrl-1 = <&i2c2_pins_sleep>; + clock-frequency = <100000>; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins_default>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + vmmc-supply = <&v3_3d>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_pins_default>; + pinctrl-1 = <&qspi_pins_sleep>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * MTD partition table. The ROM checks the first 512KiB for a + * valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; +}; + +&rtc { + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&cpu { + cpu0-supply = <&tps>; +}; diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts new file mode 100644 index 0000000..fa4d1e3 --- /dev/null +++ b/arch/arm/dts/am43x-epos-evm.dts @@ -0,0 +1,806 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM43x EPOS EVM */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/sound/tlv320aic31xx-micbias.h> + +/ { + model = "TI AM43x EPOS EVM"; + compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; + + aliases { + display0 = &lcd0; + }; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + lcd0: display { + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + label = "lcd"; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <16>; + hsync-len = <30>; + vback-porch = <10>; + vfront-porch = <22>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM43-EPOS-EVM"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1LP", "Microphone Jack", + "MIC1RP", "Microphone Jack", + "MIC1LP", "MICBIAS", + "MIC1RP", "MICBIAS", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPL", + "Speaker", "SPR"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <12000000>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3111>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&am43xx_pinmux { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ + AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + nand_flash_x8: nand_flash_x8 { + pinctrl-single,pins = < + AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ + AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; + + ecap0_pins: backlight_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ + AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ + AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ + AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ + AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ + AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ + AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + qspi1_default: qspi1_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) + AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) + AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + + hdq_pins: pinmux_hdq_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ + >; + }; + + dss_pins: dss_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ + AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) + AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ + AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ + AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ + AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ + AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ + AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ + >; + }; + + display_mux_pins: display_mux_pins { + pinctrl-single,pins = < + /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ + AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) + >; + }; + + vpfe1_pins_default: vpfe1_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ + AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ + AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ + AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ + AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ + AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ + AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ + AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ + AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ + AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ + AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ + AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ + >; + }; + + vpfe1_pins_sleep: vpfe1_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) + >; + }; + + mcasp1_pins: mcasp1_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ + AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ + >; + }; + + mcasp1_sleep_pins: mcasp1_sleep_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <16>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "vdcdc4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + at24@50 { + compatible = "at24,24c256"; + pagesize = <64>; + reg = <0x50>; + }; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + + attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; + + tlv320aic3111: tlv320aic3111@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3111"; + reg = <0x18>; + status = "okay"; + + ai31xx-micbias-vg = <MICBIAS_2_0V>; + + /* Regulators */ + HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + SPRVDD-supply = <&vbat>; /* vbat */ + SPLVDD-supply = <&vbat>; /* vbat */ + AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ + IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ + DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&display_mux_pins>; + status = "okay"; + + p1 { + /* + * SelLCDorHDMI selects between display and audio paths: + * Low: HDMI display with audio via HDMI + * High: LCD display with analog audio via aic3111 codec + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SelLCDorHDMI"; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; /* cs-on-ns */ + gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ + gpmc,we-on-ns = <0>; /* cs-on-ns */ + gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ + gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ + gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ + gpmc,access-ns = <30>; /* tCEA + 4*/ + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000C0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002C0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&ecap0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_default>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&hdq { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_pins>; + + port { + dpi_out: endpoint@0 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&vpfe1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe1_pins_default>; + pinctrl-1 = <&vpfe1_pins_sleep>; + + port { + vpfe1_ep: endpoint { + /* remote-endpoint = <&sensor>; add once we have it */ + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; + +&mcasp1 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp1_pins>; + pinctrl-1 = <&mcasp1_sleep_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&synctimer_32kclk { + assigned-clocks = <&mux_synctimer32k_ck>; + assigned-clock-parents = <&clkdiv32k_ick>; +}; diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index e7fecf7..0f242e6 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1411,7 +1411,7 @@ ti,irqs-safe-map = <0>; }; - mac: ethernet@4a100000 { + mac: ethernet@48484000 { compatible = "ti,cpsw"; ti,hwmods = "gmac"; clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; @@ -1426,6 +1426,7 @@ active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; + syscon = <&scm_conf>; reg = <0x48484000 0x1000 0x48485200 0x2E00>; #address-cells = <1>; diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi index 179584c..8650800 100644 --- a/arch/arm/dts/exynos5.dtsi +++ b/arch/arm/dts/exynos5.dtsi @@ -163,13 +163,14 @@ }; fimd@14400000 { + u-boot,dm-pre-reloc; compatible = "samsung,exynos-fimd"; reg = <0x14400000 0x10000>; #address-cells = <1>; #size-cells = <1>; }; - dp@145b0000 { + dp: dp@145b0000 { compatible = "samsung,exynos5-dp"; reg = <0x145b0000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index bda5499..29c13c1 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -198,6 +198,20 @@ reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; hotplug-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>; edid-emulation = <5>; + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; soundcodec@22 { @@ -223,6 +237,27 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&fet1>; + }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + spi@131b0000 { spi-max-frequency = <1000000>; spi-deactivate-delay = <100>; @@ -337,6 +372,15 @@ samsung,dynamic-range = <0>; samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; + samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; }; }; diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index 81b3d29..693501e 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -158,6 +158,27 @@ samsung,ycbcr-coeff = <0>; samsung,color-depth = <1>; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <1>; + enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&fet1>; + }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; }; &i2c_0 { @@ -385,6 +406,25 @@ }; }; +&dp { + status = "okay"; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <1>; + samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + &i2c_1 { status = "okay"; samsung,i2c-sda-delay = <100>; @@ -585,6 +625,19 @@ 0x04 0x59 0x60 /* MPU Clock source: LC => RCO */ 0x04 0x54 0x14 /* LC -> RCO */ 0x02 0xa1 0x91>; /* HPD high */ + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; soundcodec@20 { diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index 7eef3e3..d44c9f6 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -116,4 +116,11 @@ }; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + }; + }; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 16d52f4..2db4ad2 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -9,6 +9,8 @@ /dts-v1/; #include "exynos54xx.dtsi" +#include <dt-bindings/clock/maxim,max77802.h> +#include <dt-bindings/regulator/maxim,max77802.h> / { model = "Samsung/Google Peach Pit board based on Exynos5420"; @@ -29,6 +31,14 @@ i2c104 = &i2c_tunnel; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + power-supply = <&tps65090_fet1>; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3"; @@ -188,6 +198,20 @@ 0x04 0x59 0x60 0x04 0x54 0x14 /* LC -> RCO */ 0x02 0xa1 0x91>; /* HPD high */ + + ports { + port@0 { + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + + port@1 { + bridge_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; }; @@ -203,6 +227,18 @@ }; }; + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + spi@12d30000 { /* spi1 */ spi-max-frequency = <50000000>; firmware_storage_spi: flash@0 { @@ -254,6 +290,25 @@ }; }; +&dp { + status = "okay"; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x06>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + &spi_2 { spi-max-frequency = <3125000>; spi-deactivate-delay = <200>; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index daa6a33..b4ddf53 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -49,7 +49,7 @@ status = "disabled"; }; - i2c@12CA0000 { + hsi2c_4: i2c@12CA0000 { #address-cells = <1>; #size-cells = <0>; compatible = "samsung,exynos5-hsi2c"; @@ -178,7 +178,7 @@ samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>; }; - dp@145b0000 { + dp: dp@145b0000 { samsung,lt-status = <0>; samsung,master-mode = <0>; @@ -197,6 +197,13 @@ mem-type = "ddr3"; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + }; + xhci1: xhci@12400000 { compatible = "samsung,exynos5250-xhci"; reg = <0x12400000 0x10000>; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 76826dc..4c139bf 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -30,6 +30,27 @@ i2c104 = &i2c_tunnel; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + power-supply = <&tps65090_fet1>; + }; + + panel: panel { + compatible = "auo,b133htn01"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3"; @@ -132,6 +153,25 @@ }; }; +&dp { + status = "okay"; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + + ports { + port { + dp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &spi_2 { spi-max-frequency = <3125000>; spi-deactivate-delay = <200>; diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts new file mode 100644 index 0000000..f17a848 --- /dev/null +++ b/arch/arm/dts/exynos7420-espresso7420.dts @@ -0,0 +1,24 @@ +/* + * Samsung Espresso7420 board device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "exynos7420.dtsi" +/ { + model = "Samsung Espresso7420 board based on Exynos7420"; + compatible = "samsung,espresso7420", "samsung,exynos7420"; + + aliases { + serial2 = "/serial@14C30000"; + console = "/serial@14C30000"; + pinctrl0 = "/pinctrl@13470000"; + }; +}; + +&fin_pll { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi new file mode 100644 index 0000000..b398021 --- /dev/null +++ b/arch/arm/dts/exynos7420.dtsi @@ -0,0 +1,83 @@ +/* + * Samsung Exynos7420 SoC device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos7420-clk.h> +/ { + compatible = "samsung,exynos7420"; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + clock_topc: clock-controller@10570000 { + compatible = "samsung,exynos7-clock-topc"; + reg = <0x10570000 0x10000>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_top0: clock-controller@105d0000 { + compatible = "samsung,exynos7-clock-top0"; + reg = <0x105d0000 0xb000>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, + <&clock_topc DOUT_SCLK_BUS1_PLL>, + <&clock_topc DOUT_SCLK_CC_PLL>, + <&clock_topc DOUT_SCLK_MFC_PLL>; + clock-names = "fin_pll", "dout_sclk_bus0_pll", + "dout_sclk_bus1_pll", "dout_sclk_cc_pll", + "dout_sclk_mfc_pll"; + }; + + clock_peric1: clock-controller@14c80000 { + compatible = "samsung,exynos7-clock-peric1"; + reg = <0x14c80000 0xd00>; + u-boot,dm-pre-reloc; + #clock-cells = <1>; + clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, + <&clock_top0 CLK_SCLK_UART1>, + <&clock_top0 CLK_SCLK_UART2>, + <&clock_top0 CLK_SCLK_UART3>; + clock-names = "fin_pll", "dout_aclk_peric1_66", + "sclk_uart1", "sclk_uart2", "sclk_uart3"; + }; + + pinctrl@13470000 { + compatible = "samsung,exynos7420-pinctrl"; + reg = <0x13470000 0x1000>; + u-boot,dm-pre-reloc; + + serial2_bus: serial2-bus { + samsung,pins = "gpd1-4", "gpd1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + u-boot,dm-pre-reloc; + }; + }; + + serial@14C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x14C30000 0x100>; + u-boot,dm-pre-reloc; + clocks = <&clock_peric1 PCLK_UART2>, + <&clock_peric1 SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&serial2_bus>; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts new file mode 100644 index 0000000..983e599 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-frdm.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi new file mode 100644 index 0000000..25dcdd2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -0,0 +1,37 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A FREEDOM Board"; + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts new file mode 100644 index 0000000..76db36c --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-qds.dts @@ -0,0 +1,14 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-qds.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi new file mode 100644 index 0000000..dde7134 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A QDS Board"; + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&duart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts new file mode 100644 index 0000000..f683812 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-rdb.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-rdb.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi new file mode 100644 index 0000000..bf407ae --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -0,0 +1,39 @@ +/* + * Device Tree Include file for Freescale Layerscape-1012A family SoC. + * + * Copyright 2016, Freescale Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A RDB Board"; + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi new file mode 100644 index 0000000..546a87a --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -0,0 +1,119 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton64.dtsi" + +/ { + compatible = "fsl,ls1012a"; + interrupt-parent = <&gic>; + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1012a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x4000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + num-cs = <2>; + big-endian; + status = "disabled"; + }; + + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 66b409a..bf1dfe6 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -240,8 +240,9 @@ compatible = "fsl,vf610-qspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0x1550000 0x10000>, - <0x40000000 0x4000000>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x4000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <2>; big-endian; status = "disabled"; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts new file mode 100644 index 0000000..653c2fa --- /dev/null +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Kevin Hilman <khilman@kernel.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-gxbb.dtsi" + +/ { + compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; + model = "Hardkernel ODROID-C2"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi new file mode 100644 index 0000000..832815d --- /dev/null +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "amlogic,meson-gxbb"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0x0 0xc1100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; + + uart_A: serial@84c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x084c0 0x0 0x14>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@c4301000 { + compatible = "arm,gic-400"; + reg = <0x0 0xc4301000 0 0x1000>, + <0x0 0xc4302000 0 0x2000>, + <0x0 0xc4304000 0 0x2000>, + <0x0 0xc4306000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0x0 0xc8100000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x004c0 0x0 0x14>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + }; + + apb: apb@d0000000 { + compatible = "simple-bus"; + reg = <0x0 0xd0000000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index 5aec1b8..072eaa6 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -146,6 +146,22 @@ status = "okay"; }; +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts index 8d7446f..34073c9 100644 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ b/arch/arm/dts/rk3288-rock2-square.dts @@ -111,7 +111,7 @@ }; &gmac { - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts new file mode 100644 index 0000000..f168e4f --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "samtec VIN|ING FPGA"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb0; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q128@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; + + flash1: n25q00@1 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <1>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi index d968d76..d5a7249 100644 --- a/arch/arm/dts/pine64_common.dtsi +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi @@ -40,7 +40,23 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "a64.dtsi" +#include "sun50i-a64.dtsi" + +/ { + + aliases { + serial0 = &uart0; + }; + + soc { + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; &mmc0 { pinctrl-names = "default"; @@ -57,20 +73,8 @@ status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; - status = "okay"; -}; - -&uart4 { +&i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts index 5daff51..549dc15 100644 --- a/arch/arm/dts/pine64_plus.dts +++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts @@ -42,15 +42,11 @@ /dts-v1/; -/memreserve/ 0x45000000 0x00200000; -/memreserve/ 0x41010000 0x00010800; -/memreserve/ 0x40100000 0x00006000; - -#include "pine64_common.dtsi" +#include "sun50i-a64-pine64-common.dtsi" / { model = "Pine64+"; - compatible = "pine64,pine64_plus", "allwinner,a64"; + compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; chosen { stdout-path = "serial0:115200n8"; diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts index dcc998f..ebe029e 100644 --- a/arch/arm/dts/pine64.dts +++ b/arch/arm/dts/sun50i-a64-pine64.dts @@ -42,15 +42,11 @@ /dts-v1/; -/memreserve/ 0x45000000 0x00200000; -/memreserve/ 0x41010000 0x00010800; -/memreserve/ 0x40100000 0x00006000; - -#include "pine64_common.dtsi" +#include "sun50i-a64-pine64-common.dtsi" / { model = "Pine64"; - compatible = "pine64,pine64", "allwinner,a64"; + compatible = "pine64,pine64", "allwinner,sun50i-a64"; chosen { stdout-path = "serial0:115200n8"; diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index f3ad000..1bd436f 100644 --- a/arch/arm/dts/a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -1,7 +1,7 @@ /* * Copyright (C) 2016 ARM Ltd. * based on the Allwinner H3 dtsi: - * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -46,19 +46,10 @@ #include <dt-bindings/pinctrl/sun4i-a10.h> / { - compatible = "allwinner,a64"; interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -93,18 +84,29 @@ }; psci { - compatible = "arm,psci-0.2", "arm,psci"; + compatible = "arm,psci-0.2"; method = "smc"; - cpu_suspend = <0xc4000001>; - cpu_off = <0x84000002>; - cpu_on = <0xc4000003>; }; - memory { + memory { device_type = "memory"; reg = <0x40000000 0>; }; + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -136,7 +138,7 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { + pll1: pll1_clk@1c20000 { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-pll1-clk"; reg = <0x01c20000 0x4>; @@ -144,7 +146,7 @@ clock-output-names = "pll1"; }; - pll6: clk@01c20028 { + pll6: pll6_clk@1c20028 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-pll6-clk"; reg = <0x01c20028 0x4>; @@ -161,23 +163,24 @@ clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ - pll8: pll8_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; - clock-output-names = "pll8"; + pll7: pll7_clk@1c2002c { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c2002c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll7", "pll7x2"; }; - cpu: cpu_clk@01c20050 { + cpu: cpu_clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20050 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; clock-output-names = "cpu"; + critical-clocks = <0>; }; - axi: axi_clk@01c20050 { + axi: axi_clk@1c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20050 0x4>; @@ -185,7 +188,7 @@ clock-output-names = "axi"; }; - ahb1: ahb1_clk@01c20054 { + ahb1: ahb1_clk@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun6i-a31-ahb1-clk"; reg = <0x01c20054 0x4>; @@ -193,7 +196,7 @@ clock-output-names = "ahb1"; }; - ahb2: ahb2_clk@01c2005c { + ahb2: ahb2_clk@1c2005c { #clock-cells = <0>; compatible = "allwinner,sun8i-h3-ahb2-clk"; reg = <0x01c2005c 0x4>; @@ -201,7 +204,7 @@ clock-output-names = "ahb2"; }; - apb1: apb1_clk@01c20054 { + apb1: apb1_clk@1c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; @@ -209,7 +212,7 @@ clock-output-names = "apb1"; }; - apb2: apb2_clk@01c20058 { + apb2: apb2_clk@1c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; @@ -217,92 +220,95 @@ clock-output-names = "apb2"; }; - bus_gates: clk@01c20060 { + bus_gates: bus_gates_clk@1c20060 { #clock-cells = <1>; - compatible = "allwinner,a64-bus-gates-clk", - "allwinner,sun8i-h3-bus-gates-clk"; + compatible = "allwinner,sun50i-a64-bus-gates-clk", + "allwinner,sunxi-multi-bus-gates-clk"; reg = <0x01c20060 0x14>; - clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; - clock-names = "ahb1", "ahb2", "apb1", "apb2"; - clock-indices = <1>, - <5>, <6>, <8>, - <9>, <10>, <13>, - <14>, <17>, <18>, - <19>, <20>, - <21>, <23>, - <24>, <25>, - <28>, <29>, - <32>, <35>, - <36>, <37>, - <40>, <43>, - <44>, <52>, <53>, - <54>, <64>, - <65>, <69>, <72>, - <76>, <77>, <78>, - <96>, <97>, <98>, - <101>, - <112>, <113>, - <114>, <115>, - <116>, <135>; - clock-output-names = "bus_mipidsi", - "bus_ce", "bus_dma", "bus_mmc0", - "bus_mmc1", "bus_mmc2", "bus_nand", - "bus_sdram", "bus_gmac", "bus_ts", - "bus_hstimer", "bus_spi0", - "bus_spi1", "bus_otg", - "bus_otg_ehci0", "bus_ehci0", - "bus_otg_ohci0", "bus_ohci0", - "bus_ve", "bus_lcd0", - "bus_lcd1", "bus_deint", - "bus_csi", "bus_hdmi", - "bus_de", "bus_gpu", "bus_msgbox", - "bus_spinlock", "bus_codec", - "bus_spdif", "bus_pio", "bus_ths", - "bus_i2s0", "bus_i2s1", "bus_i2s2", - "bus_i2c0", "bus_i2c1", "bus_i2c2", - "bus_scr", - "bus_uart0", "bus_uart1", - "bus_uart2", "bus_uart3", - "bus_uart4", "bus_dbg"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; + ahb1_parent { + clocks = <&ahb1>; + clock-indices = <1>, <5>, + <6>, <8>, + <9>, <10>, + <13>, <14>, + <18>, <19>, + <20>, <21>, + <23>, <24>, + <25>, <28>, + <32>, <35>, + <36>, <37>, + <40>, <43>, + <44>, <52>, + <53>, <54>, + <135>; + clock-output-names = "bus_mipidsi", "bus_ce", + "bus_dma", "bus_mmc0", + "bus_mmc1", "bus_mmc2", + "bus_nand", "bus_sdram", + "bus_ts", "bus_hstimer", + "bus_spi0", "bus_spi1", + "bus_otg", "bus_otg_ehci0", + "bus_ehci0", "bus_otg_ohci0", + "bus_ve", "bus_lcd0", + "bus_lcd1", "bus_deint", + "bus_csi", "bus_hdmi", + "bus_de", "bus_gpu", + "bus_msgbox", "bus_spinlock", + "bus_dbg"; + }; + ahb2_parent { + clocks = <&ahb2>; + clock-indices = <17>, <29>; + clock-output-names = "bus_gmac", "bus_ohci0"; + }; + apb1_parent { + clocks = <&apb1>; + clock-indices = <64>, <65>, + <69>, <72>, + <76>, <77>, + <78>; + clock-output-names = "bus_codec", "bus_spdif", + "bus_pio", "bus_ths", + "bus_i2s0", "bus_i2s1", + "bus_i2s2"; + }; + abp2_parent { + clocks = <&apb2>; + clock-indices = <96>, <97>, + <98>, <101>, + <112>, <113>, + <114>, <115>, + <116>; + clock-output-names = "bus_i2c0", "bus_i2c1", + "bus_i2c2", "bus_scr", + "bus_uart0", "bus_uart1", + "bus_uart2", "bus_uart3", + "bus_uart4"; + }; }; - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; + mmc0_clk: mmc0_clk@1c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: mmc1_clk@1c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; + clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; + clock-output-names = "mmc1"; }; - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; + mmc2_clk: mmc2_clk@1c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - }; - - regulators { - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + clocks = <&osc24M>, <&pll6 1>, <&pll7 1>; + clock-output-names = "mmc2"; }; }; @@ -312,17 +318,14 @@ #size-cells = <1>; ranges; - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&bus_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&bus_gates 8>, <&mmc0_clk>, + <&mmc0_clk>, <&mmc0_clk>; + clock-names = "ahb", "mmc", + "output", "sample"; resets = <&ahb_rst 8>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -331,17 +334,14 @@ #size-cells = <0>; }; - mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + mmc1: mmc@1c10000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&bus_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&bus_gates 9>, <&mmc1_clk>, + <&mmc1_clk>, <&mmc1_clk>; + clock-names = "ahb", "mmc", + "output", "sample"; resets = <&ahb_rst 9>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; @@ -350,17 +350,14 @@ #size-cells = <0>; }; - mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + mmc2: mmc@1c11000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&bus_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; - clock-names = "ahb", - "mmc", - "output", - "sample"; + clocks = <&bus_gates 10>, <&mmc2_clk>, + <&mmc2_clk>, <&mmc2_clk>; + clock-names = "ahb", "mmc", + "output", "sample"; resets = <&ahb_rst 10>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; @@ -369,8 +366,8 @@ #size-cells = <0>; }; - pio: pinctrl@01c20800 { - compatible = "allwinner,a64-pinctrl"; + pio: pinctrl@1c20800 { + compatible = "allwinner,sun50i-a64-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, @@ -395,14 +392,28 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart1_pins: uart1@0 { + uart1_2pins: uart1_2@0 { + allwinner,pins = "PG6", "PG7"; + allwinner,function = "uart1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart1_4pins: uart1_4@0 { allwinner,pins = "PG6", "PG7", "PG8", "PG9"; allwinner,function = "uart1"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart2_pins: uart2@0 { + uart2_2pins: uart2_2@0 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "uart2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart2_4pins: uart2_4@0 { allwinner,pins = "PB0", "PB1", "PB2", "PB3"; allwinner,function = "uart2"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -416,14 +427,28 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart3_pins_b: uart3@1 { + uart3_2pins_b: uart3_2@1 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "uart3"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart3_4pins_b: uart3_4@1 { allwinner,pins = "PH4", "PH5", "PH6", "PH7"; allwinner,function = "uart3"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - uart4_pins: uart4@0 { + uart4_2pins: uart4_2@0 { + allwinner,pins = "PD2", "PD3"; + allwinner,function = "uart4"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart4_4pins: uart4_4@0 { allwinner,pins = "PD2", "PD3", "PD4", "PD5"; allwinner,function = "uart4"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -460,27 +485,48 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + i2c0_pins: i2c0_pins { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins: i2c1_pins { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins: i2c2_pins { + allwinner,pins = "PE14", "PE15"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; - ahb_rst: reset@01c202c0 { + ahb_rst: reset@1c202c0 { #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; + compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202c0 0xc>; }; - apb1_rst: reset@01c202d0 { + apb1_rst: reset@1c202d0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202d0 0x4>; }; - apb2_rst: reset@01c202d8 { + apb2_rst: reset@1c202d8 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x01c202d8 0x4>; }; - uart0: serial@01c28000 { + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -488,11 +534,10 @@ reg-io-width = <4>; clocks = <&bus_gates 112>; resets = <&apb2_rst 16>; - reset-names = "apb2"; status = "disabled"; }; - uart1: serial@01c28400 { + uart1: serial@1c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -500,11 +545,10 @@ reg-io-width = <4>; clocks = <&bus_gates 113>; resets = <&apb2_rst 17>; - reset-names = "apb2"; status = "disabled"; }; - uart2: serial@01c28800 { + uart2: serial@1c28800 { compatible = "snps,dw-apb-uart"; reg = <0x01c28800 0x400>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -512,11 +556,10 @@ reg-io-width = <4>; clocks = <&bus_gates 114>; resets = <&apb2_rst 18>; - reset-names = "apb2"; status = "disabled"; }; - uart3: serial@01c28c00 { + uart3: serial@1c28c00 { compatible = "snps,dw-apb-uart"; reg = <0x01c28c00 0x400>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -524,11 +567,10 @@ reg-io-width = <4>; clocks = <&bus_gates 115>; resets = <&apb2_rst 19>; - reset-names = "apb2"; status = "disabled"; }; - uart4: serial@01c29000 { + uart4: serial@1c29000 { compatible = "snps,dw-apb-uart"; reg = <0x01c29000 0x400>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -536,29 +578,47 @@ reg-io-width = <4>; clocks = <&bus_gates 116>; resets = <&apb2_rst 20>; - reset-names = "apb2"; status = "disabled"; }; - rtc: rtc@01f00000 { + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - }; - gic: interrupt-controller@{ - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 96>; + resets = <&apb2_rst 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; - reg = <0x01C81000 0x1000>, - <0x01C82000 0x2000>, - <0x01C84000 0x2000>, - <0x01C86000 0x2000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 97>; + resets = <&apb2_rst 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 98>; + resets = <&apb2_rst 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts new file mode 100644 index 0000000..5f29ee4 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000.dts @@ -0,0 +1,25 @@ +/dts-v1/; + +#include "tegra186.dtsi" + +/ { + model = "NVIDIA P2771-0000"; + compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + sdhci0 = "/sdhci@3460000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x60000000>; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + }; +}; diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi new file mode 100644 index 0000000..18b6a26 --- /dev/null +++ b/arch/arm/dts/tegra186.dtsi @@ -0,0 +1,56 @@ +#include "skeleton.dtsi" +#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "nvidia,tegra186"; + #address-cells = <2>; + #size-cells = <2>; + + gpio@2200000 { + compatible = "nvidia,tegra186-gpio"; + reg-names = "security", "gpio"; + reg = + <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; + interrupts = + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uarta: serial@3100000 { + compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03100000 0x0 0x10000>; + reg-shift = <2>; + status = "disabled"; + }; + + sdhci@3460000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03460000 0x0 0x200>; + interrupts = <GIC_SPI 31 0x04>; + status = "disabled"; + }; + + gpio@c2f0000 { + compatible = "nvidia,tegra186-gpio-aon"; + reg-names = "security", "gpio"; + reg = + <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; + interrupts = + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index 88e7f53..b148e9f 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -49,6 +49,18 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + /* for U-Boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi index 7d498ce..e485f90 100644 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi @@ -190,6 +190,42 @@ reg = <0x59801000 0x400>; }; + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 243 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio 3>, <&mio 6>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 244 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio 4>, <&mio 6>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 245 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio 5>, <&mio 6>; + }; + + mio: mioctrl@5b3e0000 { + compatible = "socionext,ph1-ld11-mioctrl"; + reg = <0x5b3e0000 0x800>; + #clock-cells = <1>; + }; + pinctrl: pinctrl@5f801000 { compatible = "socionext,ph1-ld11-pinctrl", "syscon"; reg = <0x5f801000 0xe00>; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index a327557..b618a3f 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -251,7 +251,7 @@ slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; + compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts new file mode 100644 index 0000000..03f1ad7 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -0,0 +1,212 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm018-dc4 + * + * (C) Copyright 2015 - 2016, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm018-dc4"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem0; + ethernet1 = &gem1; + ethernet2 = &gem2; + ethernet3 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; + +&gem0 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; +}; + +&gem1 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 91]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy7>; +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 92]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy3>; +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 93]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy8>; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index fb95b48..619450e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -253,9 +253,9 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf902f000 0x2000>, + <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, - <0x0 0xf906f000 0x2000>; + <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; @@ -264,6 +264,7 @@ amba: amba { compatible = "simple-bus"; + u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; @@ -674,6 +675,7 @@ }; sdhci0: sdhci@ff160000 { + u-boot,dm-pre-reloc; compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -685,6 +687,7 @@ }; sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -776,6 +779,7 @@ }; uart0: serial@ff000000 { + u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; @@ -786,6 +790,7 @@ }; uart1: serial@ff010000 { + u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h new file mode 100644 index 0000000..a5af012 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -0,0 +1,43 @@ +/* + * clk-synthesizer.h + * + * Clock synthesizer header + * + * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLK_SYNTHESIZER_H +#define __CLK_SYNTHESIZER_H + +#include <common.h> + +#define CLK_SYNTHESIZER_ID_REG 0x0 +#define CLK_SYNTHESIZER_XCSEL 0x05 +#define CLK_SYNTHESIZER_MUX_REG 0x14 +#define CLK_SYNTHESIZER_PDIV2_REG 0x16 +#define CLK_SYNTHESIZER_PDIV3_REG 0x17 + +#define CLK_SYNTHESIZER_BYTE_MODE 0x80 + +/** + * struct clk_synth: This structure holds data neeed for configuring + * for clock synthesizer. + * @id: The id of synthesizer + * @capacitor: value of the capacitor attached + * @mux: mux settings. + * @pdiv2: Div to be applied to second output + * @pdiv3: Div to be applied to third output + */ +struct clk_synth { + u32 id; + u32 capacitor; + u32 mux; + u32 pdiv2; + u32 pdiv3; +}; + +int setup_clock_synthesizer(struct clk_synth *data); + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index a6d2419..acf3fd5 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -44,6 +44,9 @@ /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 #define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) +#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) +#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) +#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 @@ -114,4 +117,5 @@ void enable_basic_clocks(void); void do_enable_clocks(u32 *const *, u32 *const *, u8); void do_disable_clocks(u32 *const *, u32 *const *, u8); +void set_mpu_spreadspectrum(int permille); #endif diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 112ac5e..62bca8c 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -99,7 +99,8 @@ struct cm_wkuppll { unsigned int timer0clkctrl; /* offset 0x10 */ unsigned int resv2[3]; unsigned int idlestdpllmpu; /* offset 0x20 */ - unsigned int resv3[2]; + unsigned int sscdeltamstepdllmpu; /* off 0x24 */ + unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */ unsigned int clkseldpllmpu; /* offset 0x2c */ unsigned int resv4[1]; unsigned int idlestdpllddr; /* offset 0x34 */ @@ -497,6 +498,8 @@ struct ctrl_stat { #define OMAP_GPIO_SYSSTATUS 0x0114 #define OMAP_GPIO_IRQSTATUS1 0x002c #define OMAP_GPIO_IRQSTATUS2 0x0030 +#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034 +#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038 #define OMAP_GPIO_CTRL 0x0130 #define OMAP_GPIO_OE 0x0134 #define OMAP_GPIO_DATAIN 0x0138 diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 97bbfe2..43e122e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -54,6 +54,21 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41J128M16JT-125 at 400MHz*/ +#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 +#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB +#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA +#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF +#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 +#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 +#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 +#define MT41J128MJT125_RATIO_400MHz 0x80 +#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 +#define MT41J128MJT125_RD_DQS_400MHz 0x3A +#define MT41J128MJT125_WR_DQS_400MHz 0x3B +#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 +#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 + /* Micron MT41K128M16JT-187E */ #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h new file mode 100644 index 0000000..7e72882 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h @@ -0,0 +1,15 @@ +/* + * Copyright 2016 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +/* BOOT0 header information */ +#define ARM_SOC_BOOT0_HOOK \ + .word 0xbabeface; \ + .word _end - _start + +#endif /* __BOOT0_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..44fe0c0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -14,8 +14,11 @@ #else #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ #endif + +#ifndef CONFIG_LS1012A #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#endif /* * Reserve secure memory @@ -134,8 +137,10 @@ #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009801 #define CONFIG_SYS_FSL_ERRATUM_A009803 #define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A010165 /* ARM A57 CORE ERRATA */ #define CONFIG_ARM_ERRATA_826974 @@ -143,6 +148,7 @@ #define CONFIG_ARM_ERRATA_829520 #define CONFIG_ARM_ERRATA_833471 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -191,10 +197,38 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_ERRATUM_A009660 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#elif defined(CONFIG_LS1012A) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ + +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 + +#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE + +#define SRDS_MAX_LANES 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_SEC_BE #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 702b9fa..1cebe2f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1043, LS1043, 4), CPU_TYPE_ENTRY(LS1023, LS1023, 2), CPU_TYPE_ENTRY(LS2040, LS2040, 4), + CPU_TYPE_ENTRY(LS1012, LS1012, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index f71c2c1..487cba8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -55,7 +55,7 @@ enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, }; -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { NONE = 0, PCIE1, @@ -134,6 +134,7 @@ enum srds_prtcl { SGMII_2500_FM2_DTSEC6, SGMII_2500_FM2_DTSEC9, SGMII_2500_FM2_DTSEC10, + TX_CLK, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 0bad0c7..e98e055 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -62,7 +60,11 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ +#ifdef CONFIG_LS1012A +#define PCIE_LUT_BASE 0xC0000 +#else #define PCIE_LUT_BASE 0x10000 +#endif #define PCIE_LUT_LCTRL0 0x7F8 #define PCIE_LUT_DBG 0x7FC @@ -157,6 +159,13 @@ struct sys_info { #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) + /* Device Configuration and Pin Control */ struct ccsr_gur { u32 porsr1; /* POR status 1 */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1d3b336..65b3357 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -77,8 +77,12 @@ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull +#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index a3ccdb0..db76066 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -69,7 +69,12 @@ enum csu_cslx_ind { CSU_CSLX_IIC4 = 77, CSU_CSLX_WDT4, CSU_CSLX_WDT3, + CSU_CSLX_ESDHC2 = 80, CSU_CSLX_WDT5 = 81, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, CSU_CSLX_FTM2 = 86, CSU_CSLX_FTM1, CSU_CSLX_FTM4, @@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = { {CSU_CSLX_IIC4, CSU_ALL_RW}, {CSU_CSLX_WDT4, CSU_ALL_RW}, {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, {CSU_CSLX_FTM2, CSU_ALL_RW}, {CSU_CSLX_FTM1, CSU_ALL_RW}, {CSU_CSLX_FTM4, CSU_ALL_RW}, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 831d817..02ecc62 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -41,6 +41,7 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE +#define SVR_LS1012 0x870400 #define SVR_LS1043 0x879200 #define SVR_LS1023 0x879208 #define SVR_LS2045 0x870120 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index d77c04a..04abec4 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -40,6 +40,7 @@ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 +#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 @@ -131,6 +132,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h new file mode 100644 index 0000000..f90f632 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/gxbb.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __GXBB_H__ +#define __GXBB_H__ + +#define GXBB_PERIPHS_BASE 0xc8834400 +#define GXBB_HIU_BASE 0xc883c000 +#define GXBB_ETH_BASE 0xc9410000 + +/* Peripherals registers */ +#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) + +/* GPIO registers 0 to 6 */ +#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) +#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) +#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) +#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) + +/* Pinmux registers 0 to 12 */ +#define GXBB_PINMUX(n) GXBB_PERIPHS_ADDR(0x2c + (n)) + +#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) +#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) + +#define GXBB_ETH_REG_0_PHY_INTF BIT(0) +#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) +#define GXBB_ETH_REG_0_CLK_EN BIT(12) + +/* HIU registers */ +#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) + +#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +/* Clock gates */ +#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) +#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) +#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) +#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) +#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) + +#define GXBB_GCLK_MPEG_1_ETH BIT(3) + +#endif /* __GXBB_H__ */ diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h new file mode 100644 index 0000000..225438d --- /dev/null +++ b/arch/arm/include/asm/arch-meson/sm.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MESON_SM_H__ +#define __MESON_SM_H__ + +ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size); + +#endif /* __MESON_SM_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3ab04bf..ac37e4f 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -227,8 +227,13 @@ #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) -#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR -#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index a3106e7..74917f0 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -218,10 +218,13 @@ #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 - -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000) - +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/imx-common/regs-lcdif.h> #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 53cc2b0..e8aa786 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -59,13 +59,8 @@ struct ctrl_id { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ -/* device type */ -#define DEVICE_MASK (0x7 << 8) +/* boot pin mask */ #define SYSBOOT_MASK 0x1F -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 /* device speed */ #define SKUID_CLK_MASK 0xf diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 38d50d6..551c927 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -239,19 +239,22 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 -/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA752 1100 -#define VDD_EVE_DRA752 1060 -#define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1060 -#define VDD_IVA_DRA752 1060 - -/* DRA72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA72x 1100 -#define VDD_EVE_DRA72x 1060 -#define VDD_GPU_DRA72x 1060 -#define VDD_CORE_DRA72x 1060 -#define VDD_IVA_DRA72x 1060 +/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA7_NOM 1150 +#define VDD_CORE_DRA7_NOM 1150 +#define VDD_EVE_DRA7_NOM 1060 +#define VDD_GPU_DRA7_NOM 1060 +#define VDD_IVA_DRA7_NOM 1060 + +/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ +#define VDD_EVE_DRA7_OD 1150 +#define VDD_GPU_DRA7_OD 1150 +#define VDD_IVA_DRA7_OD 1150 + +/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ +#define VDD_EVE_DRA7_HIGH 1250 +#define VDD_GPU_DRA7_HIGH 1250 +#define VDD_IVA_DRA7_HIGH 1250 /* Efuse register offsets for DRA7xx platform */ #define DRA752_EFUSE_BASE 0x4A002000 @@ -283,6 +286,20 @@ /* STD_FUSE_OPP_VMIN_MPU_4 */ #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) +/* Common voltage and Efuse register macros */ +/* DRA74x/DRA75x/DRA72x */ +#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM +#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM +#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM +#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM +#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM + +#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM +#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM +#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM +#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM +#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index b1513e9..683d905 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -116,4 +116,16 @@ struct watchdog { #define CPSW_BASE 0x48484000 #define CPSW_MDIO_BASE 0x48485000 +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII (GMII1_SEL_MII << 4) +#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4) +#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 804266a..ab0e7fa 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -51,6 +51,7 @@ void sdelay(unsigned long); void setup_early_clocks(void); void prcm_init(void); void do_board_detect(void); +void vcores_init(void); void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d2690c7..8a8ca9c 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -90,6 +90,23 @@ enum { SDIO0_DIV_MASK = 0x3f, }; +/* CRU_CLKSEL21_CON */ +enum { + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f, + + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = 1, + + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, +}; + /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 0117a17..aaffd19 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -718,6 +718,40 @@ enum { MSCH0_MAINPARTIALPOP_MASK = 1, }; +/* GRF_SOC_CON1 */ +enum { + RMII_MODE_SHIFT = 0xe, + RMII_MODE_MASK = 1, + RMII_MODE = 1, + + GMAC_CLK_SEL_SHIFT = 0xc, + GMAC_CLK_SEL_MASK = 3, + GMAC_CLK_SEL_125M = 0, + GMAC_CLK_SEL_25M = 0x3, + GMAC_CLK_SEL_2_5M = 0x2, + + RMII_CLK_SEL_SHIFT = 0xb, + RMII_CLK_SEL_MASK = 1, + RMII_CLK_SEL_2_5M = 0, + RMII_CLK_SEL_25M, + + GMAC_SPEED_SHIFT = 0xa, + GMAC_SPEED_MASK = 1, + GMAC_SPEED_10M = 0, + GMAC_SPEED_100M, + + GMAC_FLOWCTRL_SHIFT = 0x9, + GMAC_FLOWCTRL_MASK = 1, + + GMAC_PHY_INTF_SEL_SHIFT = 0x6, + GMAC_PHY_INTF_SEL_MASK = 0x7, + GMAC_PHY_INTF_SEL_RGMII = 0x1, + GMAC_PHY_INTF_SEL_RMII = 0x4, + + HOST_REMAP_SHIFT = 0x5, + HOST_REMAP_MASK = 1 +}; + /* GRF_SOC_CON2 */ enum { UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd, @@ -765,4 +799,23 @@ enum { PWM_PWM = 0, }; +/* GRF_SOC_CON3 */ +enum { + RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RXCLK_DLY_ENA_GMAC_MASK = 1, + RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RXCLK_DLY_ENA_GMAC_ENABLE, + + TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + TXCLK_DLY_ENA_GMAC_MASK = 1, + TXCLK_DLY_ENA_GMAC_DISABLE = 0, + TXCLK_DLY_ENA_GMAC_ENABLE, + + CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + CLK_RX_DL_CFG_GMAC_MASK = 0x7f, + + CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + CLK_TX_DL_CFG_GMAC_MASK = 0x7f, +}; + #endif diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h new file mode 100644 index 0000000..ea5675e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -0,0 +1,14 @@ +/* + * Configuration settings for the Allwinner A64 (sun50i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +/* reserve space for BOOT0 header information */ +#define ARM_SOC_BOOT0_HOOK \ + .space 1532 + +#endif /* __BOOT0_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index ca9a4f9..a0f33b0 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -18,6 +18,10 @@ #define SPL_ADDR 0x0 #endif +/* The low 8-bits of the 'boot_media' field in the SPL header */ +#define SUNXI_BOOTED_FROM_MMC0 0 +#define SUNXI_BOOTED_FROM_SPI 3 + /* boot head definition from sun4i boot code */ struct boot_file_head { uint32_t b_instruction; /* one intruction jumping to real code */ @@ -45,7 +49,9 @@ struct boot_file_head { uint8_t spl_signature[4]; }; uint32_t fel_script_address; - uint32_t reserved; /* padding, align to 32 bytes */ + uint32_t reserved1[3]; + uint32_t boot_media; /* written here by the boot ROM */ + uint32_t reserved2[5]; /* padding, align to 64 bytes */ }; #define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index daf5698..db60864 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,6 +6,8 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ +#include <dt-bindings/gpio/tegra-gpio.h> + #define TEGRA_GPIOS_PER_PORT 8 #define TEGRA_PORTS_PER_BANK 4 #define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a20bdaa..75e56c4 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -134,7 +134,9 @@ struct mmc_host { int id; /* device id/number, 0-3 */ int enabled; /* 1 to enable, 0 to disable */ int width; /* Bus Width, 1, 4 or 8 */ +#ifndef CONFIG_TEGRA186 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ +#endif struct gpio_desc cd_gpio; /* Change Detect GPIO */ struct gpio_desc pwr_gpio; /* Power GPIO */ struct gpio_desc wp_gpio; /* Write Protect GPIO */ diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h index 1a6dcb8..ba748a5 100644 --- a/arch/arm/include/asm/arch-tegra124/gpio.h +++ b/arch/arm/include/asm/arch-tegra124/gpio.h @@ -41,263 +41,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, - GPIO_PFF0, /* pin 248 */ - GPIO_PFF1, - GPIO_PFF2, - GPIO_PFF3, - GPIO_PFF4, - GPIO_PFF5, - GPIO_PFF6, - GPIO_PFF7, /* pin 255 */ -}; - #endif /* _TEGRA124_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h new file mode 100644 index 0000000..aaecfc7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra186/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_GPIO_H_ +#define _TEGRA186_GPIO_H_ + +#endif diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h new file mode 100644 index 0000000..8031f23 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra186/tegra.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2013-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _TEGRA186_TEGRA_H_ +#define _TEGRA186_TEGRA_H_ + +#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ +#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ +#define NV_PA_SDRAM_BASE 0x80000000 + +#include <asm/arch-tegra/tegra.h> + +#endif diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h index b40b1ff..af301e7 100644 --- a/arch/arm/include/asm/arch-tegra20/gpio.h +++ b/arch/arm/include/asm/arch-tegra20/gpio.h @@ -33,231 +33,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, /* pin 223 */ -}; - #endif /* TEGRA20_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h index 71af423..389d5b6 100644 --- a/arch/arm/include/asm/arch-tegra210/gpio.h +++ b/arch/arm/include/asm/arch-tegra210/gpio.h @@ -41,263 +41,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, - GPIO_PFF0, /* pin 248 */ - GPIO_PFF1, - GPIO_PFF2, - GPIO_PFF3, - GPIO_PFF4, - GPIO_PFF5, - GPIO_PFF6, - GPIO_PFF7, /* pin 255 */ -}; - #endif /* _TEGRA210_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h index d2c6c78..e384327 100644 --- a/arch/arm/include/asm/arch-tegra30/gpio.h +++ b/arch/arm/include/asm/arch-tegra30/gpio.h @@ -40,255 +40,4 @@ struct gpio_ctlr { struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; }; -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, - GPIO_PCC0, /* pin 224 */ - GPIO_PCC1, - GPIO_PCC2, - GPIO_PCC3, - GPIO_PCC4, - GPIO_PCC5, - GPIO_PCC6, - GPIO_PCC7, - GPIO_PDD0, /* pin 232 */ - GPIO_PDD1, - GPIO_PDD2, - GPIO_PDD3, - GPIO_PDD4, - GPIO_PDD5, - GPIO_PDD6, - GPIO_PDD7, - GPIO_PEE0, /* pin 240 */ - GPIO_PEE1, - GPIO_PEE2, - GPIO_PEE3, - GPIO_PEE4, - GPIO_PEE5, - GPIO_PEE6, - GPIO_PEE7, /* pin 247 */ -}; - #endif /* _TEGRA30_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 021626d..1db2bd6 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); +void psu_init(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 11b80fb..ae1e42f 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -15,6 +15,7 @@ */ #include <config.h> +#include <asm/unified.h> /* * Endian independent macros for shifting bytes within registers. diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8fb05e1..07f3848 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -145,6 +145,7 @@ struct prcm_regs { u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; + u32 cm_coreaon_usb_phy3_core_clkctrl; u32 cm_coreaon_l3init_60m_gfclk_clkctrl; /* cm2.core */ @@ -717,6 +718,17 @@ static inline u8 is_dra72x(void) #define DRA722_ES2_0 0x07220200 /* + * silicon device type + * Moving to common from cpu.h, since it is shared by various omap devices + */ +#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + + +/* * SRAM scratch space entries */ #define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 128a606..3704f07 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -18,7 +18,7 @@ #ifndef __ARM_PSCI_H__ #define __ARM_PSCI_H__ -/* PSCI interface */ +/* PSCI 0.1 interface */ #define ARM_PSCI_FN_BASE 0x95c1ba5e #define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) @@ -32,6 +32,21 @@ #define ARM_PSCI_RET_INVAL (-2) #define ARM_PSCI_RET_DENIED (-3) +/* PSCI 0.2 interface */ +#define ARM_PSCI_0_2_FN_BASE 0x84000000 +#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n)) + +#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0) +#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1) +#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2) +#define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3) +#define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4) +#define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5) +#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6) +#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7) +#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8) +#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9) + #ifndef __ASSEMBLY__ int psci_update_dt(void *fdt); void psci_board_init(void); diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h new file mode 100644 index 0000000..b8b85b7 --- /dev/null +++ b/arch/arm/include/asm/setjmp.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2016 + * Alexander Graf <agraf@suse.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SETJMP_H_ +#define _SETJMP_H_ 1 + +struct jmp_buf_data { + ulong target; + ulong regs[5]; +}; + +typedef struct jmp_buf_data jmp_buf[1]; + +static inline int setjmp(jmp_buf jmp) +{ + long r = 0; + +#ifdef CONFIG_ARM64 + asm volatile( + "adr x1, jmp_target\n" + "str x1, %1\n" + "stp x26, x27, %2\n" + "stp x28, x29, %3\n" + "mov x1, sp\n" + "str x1, %4\n" + "b 2f\n" + "jmp_target: " + "mov %0, #1\n" + "2:\n" + : "+r" (r), "=m" (jmp->target), + "=m" (jmp->regs[0]), "=m" (jmp->regs[2]), + "=m" (jmp->regs[4]) + : + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x19", "x20", "x21", "x22", + "x23", "x24", "x25", /* x26, x27, x28, x29, sp */ + "x30", "cc", "memory"); +#else + asm volatile( +#ifdef CONFIG_SYS_THUMB_BUILD + "adr r0, jmp_target + 1\n" +#else + "adr r0, jmp_target\n" +#endif + "mov r1, %1\n" + "mov r2, sp\n" + "stm r1, {r0, r2, r4, r5, r6, r7}\n" + "b 2f\n" + "jmp_target: " + "mov %0, #1\n" + "2:\n" + : "+l" (r) + : "l" (&jmp->target) + : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */ + "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr", + "cc", "memory"); +#endif + +printf("%s:%d target=%#lx\n", __func__, __LINE__, jmp->target); + + return r; +} + +static inline __noreturn void longjmp(jmp_buf jmp) +{ +#ifdef CONFIG_ARM64 + asm volatile( + "ldr x0, %0\n" + "ldr x1, %3\n" + "mov sp, x1\n" + "ldp x26, x27, %1\n" + "ldp x28, x25, %2\n" + "mov x29, x25\n" + "br x0\n" + : + : "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]), + "m" (jmp->regs[4]) + : "x0", "x1", "x25", "x26", "x27", "x28"); +#else + asm volatile( + "mov r1, %0\n" + "ldm r1, {r0, r2, r4, r5, r6, r7}\n" + "mov sp, r2\n" + "bx r0\n" + : + : "l" (&jmp->target) + : "r1"); +#endif + + while (1) { } +} + + +#endif /* _SETJMP_H_ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9ae890a..2bdc0be 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -128,6 +128,8 @@ void hvc_call(struct pt_regs *args); */ void smc_call(struct pt_regs *args); +void __noreturn psci_system_reset(bool smc); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 11407be..f343ac2 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -35,10 +35,12 @@ struct davinci_emif_regs { uint32_t sdrcr; union { uint32_t abncr[4]; - uint32_t ab1cr; - uint32_t ab2cr; - uint32_t ab3cr; - uint32_t ab4cr; + struct { + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; }; uint32_t sdtimr; uint32_t ddrsr; diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h new file mode 100644 index 0000000..1b26002 --- /dev/null +++ b/arch/arm/include/asm/unified.h @@ -0,0 +1,129 @@ +/* + * include/asm-arm/unified.h - Unified Assembler Syntax helper macros + * + * Copyright (C) 2008 ARM Limited + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_UNIFIED_H +#define __ASM_UNIFIED_H + +#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED) + .syntax unified +#endif + +#ifdef CONFIG_CPU_V7M +#define AR_CLASS(x...) +#define M_CLASS(x...) x +#else +#define AR_CLASS(x...) x +#define M_CLASS(x...) +#endif + +#ifdef CONFIG_THUMB2_KERNEL + +#if __GNUC__ < 4 +#error Thumb-2 kernel requires gcc >= 4 +#endif + +/* The CPSR bit describing the instruction set (Thumb) */ +#define PSR_ISETSTATE PSR_T_BIT + +#define ARM(x...) +#define THUMB(x...) x +#ifdef __ASSEMBLY__ +#define W(instr) instr.w +#else +#define WASM(instr) #instr ".w" +#endif + +#else /* !CONFIG_THUMB2_KERNEL */ + +/* The CPSR bit describing the instruction set (ARM) */ +#define PSR_ISETSTATE 0 + +#define ARM(x...) x +#define THUMB(x...) +#ifdef __ASSEMBLY__ +#define W(instr) instr +#else +#define WASM(instr) #instr +#endif + +#endif /* CONFIG_THUMB2_KERNEL */ + +#ifndef CONFIG_ARM_ASM_UNIFIED + +/* + * If the unified assembly syntax isn't used (in ARM mode), these + * macros expand to an empty string + */ +#ifdef __ASSEMBLY__ + .macro it, cond + .endm + .macro itt, cond + .endm + .macro ite, cond + .endm + .macro ittt, cond + .endm + .macro itte, cond + .endm + .macro itet, cond + .endm + .macro itee, cond + .endm + .macro itttt, cond + .endm + .macro ittte, cond + .endm + .macro ittet, cond + .endm + .macro ittee, cond + .endm + .macro itett, cond + .endm + .macro itete, cond + .endm + .macro iteet, cond + .endm + .macro iteee, cond + .endm +#else /* !__ASSEMBLY__ */ +__asm__( +" .macro it, cond\n" +" .endm\n" +" .macro itt, cond\n" +" .endm\n" +" .macro ite, cond\n" +" .endm\n" +" .macro ittt, cond\n" +" .endm\n" +" .macro itte, cond\n" +" .endm\n" +" .macro itet, cond\n" +" .endm\n" +" .macro itee, cond\n" +" .endm\n" +" .macro itttt, cond\n" +" .endm\n" +" .macro ittte, cond\n" +" .endm\n" +" .macro ittet, cond\n" +" .endm\n" +" .macro ittee, cond\n" +" .endm\n" +" .macro itett, cond\n" +" .endm\n" +" .macro itete, cond\n" +" .endm\n" +" .macro iteet, cond\n" +" .endm\n" +" .macro iteee, cond\n" +" .endm\n"); +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_ARM_ASM_UNIFIED */ + +#endif /* !__ASM_UNIFIED_H */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 7a0fb58..0e05e87 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -5,9 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \ - _lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \ - _uldivmod.o +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \ + lib1funcs.o uldivmod.o div0.o \ + div64.o muldi3.o ifdef CONFIG_CPU_V7M obj-y += vectors_m.o crt0.o @@ -46,7 +46,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_RESET +ifndef CONFIG_SYSRESET obj-y += reset.o endif @@ -62,9 +62,17 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o endif +asflags-y += -DCONFIG_ARM_ASM_UNIFIED +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +asflags-y += -D__LINUX_ARM_ARCH__=4 +else +asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) +endif + # some files can only build in ARM or THUMB2, not THUMB1 ifdef CONFIG_SYS_THUMB_BUILD +asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 # for C files, just apend -marm, which will override previous -mthumb* @@ -82,6 +90,5 @@ AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD - endif endif diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S deleted file mode 100644 index c463c68..0000000 --- a/arch/arm/lib/_divsi3.S +++ /dev/null @@ -1,143 +0,0 @@ -#include <linux/linkage.h> - -.macro ARM_DIV_BODY dividend, divisor, result, curbit - -#if __LINUX_ARM_ARCH__ >= 5 - - clz \curbit, \divisor - clz \result, \dividend - sub \result, \curbit, \result - mov \curbit, #1 - mov \divisor, \divisor, lsl \result - mov \curbit, \curbit, lsl \result - mov \result, #0 - -#else - - @ Initially shift the divisor left 3 bits if possible, - @ set curbit accordingly. This allows for curbit to be located - @ at the left end of each 4 bit nibbles in the division loop - @ to save one loop in most cases. - tst \divisor, #0xe0000000 - moveq \divisor, \divisor, lsl #3 - moveq \curbit, #8 - movne \curbit, #1 - - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. -1: cmp \divisor, #0x10000000 - cmplo \divisor, \dividend - movlo \divisor, \divisor, lsl #4 - movlo \curbit, \curbit, lsl #4 - blo 1b - - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. -1: cmp \divisor, #0x80000000 - cmplo \divisor, \dividend - movlo \divisor, \divisor, lsl #1 - movlo \curbit, \curbit, lsl #1 - blo 1b - - mov \result, #0 - -#endif - - @ Division loop -1: cmp \dividend, \divisor - subhs \dividend, \dividend, \divisor - orrhs \result, \result, \curbit - cmp \dividend, \divisor, lsr #1 - subhs \dividend, \dividend, \divisor, lsr #1 - orrhs \result, \result, \curbit, lsr #1 - cmp \dividend, \divisor, lsr #2 - subhs \dividend, \dividend, \divisor, lsr #2 - orrhs \result, \result, \curbit, lsr #2 - cmp \dividend, \divisor, lsr #3 - subhs \dividend, \dividend, \divisor, lsr #3 - orrhs \result, \result, \curbit, lsr #3 - cmp \dividend, #0 @ Early termination? - movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? - movne \divisor, \divisor, lsr #4 - bne 1b - -.endm - -.macro ARM_DIV2_ORDER divisor, order - -#if __LINUX_ARM_ARCH__ >= 5 - - clz \order, \divisor - rsb \order, \order, #31 - -#else - - cmp \divisor, #(1 << 16) - movhs \divisor, \divisor, lsr #16 - movhs \order, #16 - movlo \order, #0 - - cmp \divisor, #(1 << 8) - movhs \divisor, \divisor, lsr #8 - addhs \order, \order, #8 - - cmp \divisor, #(1 << 4) - movhs \divisor, \divisor, lsr #4 - addhs \order, \order, #4 - - cmp \divisor, #(1 << 2) - addhi \order, \order, #3 - addls \order, \order, \divisor, lsr #1 - -#endif - -.endm - - .align 5 -.globl __divsi3 -__divsi3: -ENTRY(__aeabi_idiv) - cmp r1, #0 - eor ip, r0, r1 @ save the sign of the result. - beq Ldiv0 - rsbmi r1, r1, #0 @ loops below use unsigned. - subs r2, r1, #1 @ division by 1 or -1 ? - beq 10f - movs r3, r0 - rsbmi r3, r0, #0 @ positive dividend value - cmp r3, r1 - bls 11f - tst r1, r2 @ divisor is power of 2 ? - beq 12f - - ARM_DIV_BODY r3, r1, r0, r2 - - cmp ip, #0 - rsbmi r0, r0, #0 - mov pc, lr - -10: teq ip, r0 @ same sign ? - rsbmi r0, r0, #0 - mov pc, lr - -11: movlo r0, #0 - moveq r0, ip, asr #31 - orreq r0, r0, #1 - mov pc, lr - -12: ARM_DIV2_ORDER r1, r2 - - cmp ip, #0 - mov r0, r3, lsr r2 - rsbmi r0, r0, #0 - mov pc, lr - -Ldiv0: - - str lr, [sp, #-4]! - bl __div0 - mov r0, #0 @ About as wrong as it could be. - ldr pc, [sp], #4 -ENDPROC(__aeabi_idiv) diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S deleted file mode 100644 index c5e1c22..0000000 --- a/arch/arm/lib/_modsi3.S +++ /dev/null @@ -1,99 +0,0 @@ -#include <linux/linkage.h> - -.macro ARM_MOD_BODY dividend, divisor, order, spare - -#if __LINUX_ARM_ARCH__ >= 5 - - clz \order, \divisor - clz \spare, \dividend - sub \order, \order, \spare - mov \divisor, \divisor, lsl \order - -#else - - mov \order, #0 - - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. -1: cmp \divisor, #0x10000000 - cmplo \divisor, \dividend - movlo \divisor, \divisor, lsl #4 - addlo \order, \order, #4 - blo 1b - - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. -1: cmp \divisor, #0x80000000 - cmplo \divisor, \dividend - movlo \divisor, \divisor, lsl #1 - addlo \order, \order, #1 - blo 1b - -#endif - - @ Perform all needed substractions to keep only the reminder. - @ Do comparisons in batch of 4 first. - subs \order, \order, #3 @ yes, 3 is intended here - blt 2f - -1: cmp \dividend, \divisor - subhs \dividend, \dividend, \divisor - cmp \dividend, \divisor, lsr #1 - subhs \dividend, \dividend, \divisor, lsr #1 - cmp \dividend, \divisor, lsr #2 - subhs \dividend, \dividend, \divisor, lsr #2 - cmp \dividend, \divisor, lsr #3 - subhs \dividend, \dividend, \divisor, lsr #3 - cmp \dividend, #1 - mov \divisor, \divisor, lsr #4 - subges \order, \order, #4 - bge 1b - - tst \order, #3 - teqne \dividend, #0 - beq 5f - - @ Either 1, 2 or 3 comparison/substractions are left. -2: cmn \order, #2 - blt 4f - beq 3f - cmp \dividend, \divisor - subhs \dividend, \dividend, \divisor - mov \divisor, \divisor, lsr #1 -3: cmp \dividend, \divisor - subhs \dividend, \dividend, \divisor - mov \divisor, \divisor, lsr #1 -4: cmp \dividend, \divisor - subhs \dividend, \dividend, \divisor -5: -.endm - - .align 5 -ENTRY(__modsi3) - cmp r1, #0 - beq Ldiv0 - rsbmi r1, r1, #0 @ loops below use unsigned. - movs ip, r0 @ preserve sign of dividend - rsbmi r0, r0, #0 @ if negative make positive - subs r2, r1, #1 @ compare divisor with 1 - cmpne r0, r1 @ compare dividend with divisor - moveq r0, #0 - tsthi r1, r2 @ see if divisor is power of 2 - andeq r0, r0, r2 - bls 10f - - ARM_MOD_BODY r0, r1, r2, r3 - -10: cmp ip, #0 - rsbmi r0, r0, #0 - mov pc, lr -ENDPROC(__modsi3) - -Ldiv0: - - str lr, [sp, #-4]! - bl __div0 - mov r0, #0 @ About as wrong as it could be. - ldr pc, [sp], #4 diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S deleted file mode 100644 index 3b653be..0000000 --- a/arch/arm/lib/_udivsi3.S +++ /dev/null @@ -1,95 +0,0 @@ -#include <linux/linkage.h> - -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -dividend .req r0 -divisor .req r1 -result .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __udivsi3 - .type __udivsi3 ,function - .globl __aeabi_uidiv - .type __aeabi_uidiv ,function - .align 0 - __udivsi3: - __aeabi_uidiv: - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - mov result, #0 - cmp dividend, divisor - bcc Lgot_result -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions, and note which bits - @ are done in the result. On the final pass, this may subtract - @ too much from the dividend, but the result will be ok, since the - @ "bit" will have been shifted out at the bottom. - cmp dividend, divisor - subcs dividend, dividend, divisor - orrcs result, result, curbit - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs result, result, curbit, lsr #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs result, result, curbit, lsr #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs result, result, curbit, lsr #3 - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 -Lgot_result: - mov r0, result - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __udivsi3 , . - __udivsi3 - -ENTRY(__aeabi_uidivmod) - - stmfd sp!, {r0, r1, ip, lr} - bl __aeabi_uidiv - ldmfd sp!, {r1, r2, ip, lr} - mul r3, r0, r2 - sub r1, r1, r3 - mov pc, lr -ENDPROC(__aeabi_uidivmod) - -ENTRY(__aeabi_idivmod) - - stmfd sp!, {r0, r1, ip, lr} - bl __aeabi_idiv - ldmfd sp!, {r1, r2, ip, lr} - mul r3, r0, r2 - sub r1, r1, r3 - mov pc, lr -ENDPROC(__aeabi_idivmod) diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S deleted file mode 100644 index b166737..0000000 --- a/arch/arm/lib/_umodsi3.S +++ /dev/null @@ -1,90 +0,0 @@ -#include <linux/linkage.h> - -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -/* # 145 "libgcc1.S" */ -dividend .req r0 -divisor .req r1 -overdone .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .type __umodsi3 ,function - .align 0 - ENTRY(__umodsi3) - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - cmp dividend, divisor - movcc pc, lr -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions. On the final pass, this may - @ subtract too much from the dividend, so keep track of which - @ subtractions are done, we can fix them up afterwards... - mov overdone, #0 - cmp dividend, divisor - subcs dividend, dividend, divisor - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs overdone, overdone, curbit, ror #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs overdone, overdone, curbit, ror #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs overdone, overdone, curbit, ror #3 - mov ip, curbit - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 - @ Any subtractions that we should not have done will be recorded in - @ the top three bits of "overdone". Exactly which were not needed - @ are governed by the position of the bit, stored in ip. - @ If we terminated early, because dividend became zero, - @ then none of the below will match, since the bit in ip will not be - @ in the bottom nibble. - ands overdone, overdone, #0xe0000000 - moveq pc, lr @ No fixups needed - tst overdone, ip, ror #3 - addne dividend, dividend, divisor, lsr #3 - tst overdone, ip, ror #2 - addne dividend, dividend, divisor, lsr #2 - tst overdone, ip, ror #1 - addne dividend, dividend, divisor, lsr #1 - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __umodsi3 , . - __umodsi3 -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ -ENDPROC(__umodsi3) diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/ashldi3.S index 9c34c21..e9ec890 100644 --- a/arch/arm/lib/_ashldi3.S +++ b/arch/arm/lib/ashldi3.S @@ -5,6 +5,7 @@ */ #include <linux/linkage.h> +#include <asm/assembler.h> #ifdef __ARMEB__ #define al r1 @@ -14,15 +15,20 @@ #define ah r1 #endif -.globl __ashldi3 -__ashldi3: +.pushsection .text.__ashldi3, "ax" +ENTRY(__ashldi3) ENTRY(__aeabi_llsl) subs r3, r2, #32 rsb ip, r2, #32 movmi ah, ah, lsl r2 movpl ah, al, lsl r3 - orrmi ah, ah, al, lsr ip + ARM( orrmi ah, ah, al, lsr ip ) + THUMB( lsrmi r3, al, ip ) + THUMB( orrmi ah, ah, r3 ) mov al, al, lsl r2 - mov pc, lr + ret lr + +ENDPROC(__ashldi3) ENDPROC(__aeabi_llsl) +.popsection diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/ashrdi3.S index c74fd64..6e15774 100644 --- a/arch/arm/lib/_ashrdi3.S +++ b/arch/arm/lib/ashrdi3.S @@ -5,6 +5,7 @@ */ #include <linux/linkage.h> +#include <asm/assembler.h> #ifdef __ARMEB__ #define al r1 @@ -14,15 +15,20 @@ #define ah r1 #endif -.globl __ashrdi3 -__ashrdi3: +.pushsection .text.__ashrdi3, "ax" +ENTRY(__ashrdi3) ENTRY(__aeabi_lasr) subs r3, r2, #32 rsb ip, r2, #32 movmi al, al, lsr r2 movpl al, ah, asr r3 - orrmi al, al, ah, lsl ip + ARM( orrmi al, al, ah, lsl ip ) + THUMB( lslmi r3, ah, ip ) + THUMB( orrmi al, al, r3 ) mov ah, ah, asr r2 - mov pc, lr + ret lr + +ENDPROC(__ashrdi3) ENDPROC(__aeabi_lasr) +.popsection diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S new file mode 100644 index 0000000..b417db2 --- /dev/null +++ b/arch/arm/lib/div64.S @@ -0,0 +1,214 @@ +/* + * linux/arch/arm/lib/div64.S + * + * Optimized computation of 64-bit dividend / 32-bit divisor + * + * Author: Nicolas Pitre + * Created: Oct 5, 2003 + * Copyright: Monta Vista Software, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#ifdef __UBOOT__ +#define UNWIND(x...) +#endif + +#ifdef __ARMEB__ +#define xh r0 +#define xl r1 +#define yh r2 +#define yl r3 +#else +#define xl r0 +#define xh r1 +#define yl r2 +#define yh r3 +#endif + +/* + * __do_div64: perform a division with 64-bit dividend and 32-bit divisor. + * + * Note: Calling convention is totally non standard for optimal code. + * This is meant to be used by do_div() from include/asm/div64.h only. + * + * Input parameters: + * xh-xl = dividend (clobbered) + * r4 = divisor (preserved) + * + * Output values: + * yh-yl = result + * xh = remainder + * + * Clobbered regs: xl, ip + */ + +.pushsection .text.__do_div64, "ax" +ENTRY(__do_div64) +UNWIND(.fnstart) + + @ Test for easy paths first. + subs ip, r4, #1 + bls 9f @ divisor is 0 or 1 + tst ip, r4 + beq 8f @ divisor is power of 2 + + @ See if we need to handle upper 32-bit result. + cmp xh, r4 + mov yh, #0 + blo 3f + + @ Align divisor with upper part of dividend. + @ The aligned divisor is stored in yl preserving the original. + @ The bit position is stored in ip. + +#if __LINUX_ARM_ARCH__ >= 5 + + clz yl, r4 + clz ip, xh + sub yl, yl, ip + mov ip, #1 + mov ip, ip, lsl yl + mov yl, r4, lsl yl + +#else + + mov yl, r4 + mov ip, #1 +1: cmp yl, #0x80000000 + cmpcc yl, xh + movcc yl, yl, lsl #1 + movcc ip, ip, lsl #1 + bcc 1b + +#endif + + @ The division loop for needed upper bit positions. + @ Break out early if dividend reaches 0. +2: cmp xh, yl + orrcs yh, yh, ip + subscs xh, xh, yl + movsne ip, ip, lsr #1 + mov yl, yl, lsr #1 + bne 2b + + @ See if we need to handle lower 32-bit result. +3: cmp xh, #0 + mov yl, #0 + cmpeq xl, r4 + movlo xh, xl + retlo lr + + @ The division loop for lower bit positions. + @ Here we shift remainer bits leftwards rather than moving the + @ divisor for comparisons, considering the carry-out bit as well. + mov ip, #0x80000000 +4: movs xl, xl, lsl #1 + adcs xh, xh, xh + beq 6f + cmpcc xh, r4 +5: orrcs yl, yl, ip + subcs xh, xh, r4 + movs ip, ip, lsr #1 + bne 4b + ret lr + + @ The top part of remainder became zero. If carry is set + @ (the 33th bit) this is a false positive so resume the loop. + @ Otherwise, if lower part is also null then we are done. +6: bcs 5b + cmp xl, #0 + reteq lr + + @ We still have remainer bits in the low part. Bring them up. + +#if __LINUX_ARM_ARCH__ >= 5 + + clz xh, xl @ we know xh is zero here so... + add xh, xh, #1 + mov xl, xl, lsl xh + mov ip, ip, lsr xh + +#else + +7: movs xl, xl, lsl #1 + mov ip, ip, lsr #1 + bcc 7b + +#endif + + @ Current remainder is now 1. It is worthless to compare with + @ divisor at this point since divisor can not be smaller than 3 here. + @ If possible, branch for another shift in the division loop. + @ If no bit position left then we are done. + movs ip, ip, lsr #1 + mov xh, #1 + bne 4b + ret lr + +8: @ Division by a power of 2: determine what that divisor order is + @ then simply shift values around + +#if __LINUX_ARM_ARCH__ >= 5 + + clz ip, r4 + rsb ip, ip, #31 + +#else + + mov yl, r4 + cmp r4, #(1 << 16) + mov ip, #0 + movhs yl, yl, lsr #16 + movhs ip, #16 + + cmp yl, #(1 << 8) + movhs yl, yl, lsr #8 + addhs ip, ip, #8 + + cmp yl, #(1 << 4) + movhs yl, yl, lsr #4 + addhs ip, ip, #4 + + cmp yl, #(1 << 2) + addhi ip, ip, #3 + addls ip, ip, yl, lsr #1 + +#endif + + mov yh, xh, lsr ip + mov yl, xl, lsr ip + rsb ip, ip, #32 + ARM( orr yl, yl, xh, lsl ip ) + THUMB( lsl xh, xh, ip ) + THUMB( orr yl, yl, xh ) + mov xh, xl, lsl ip + mov xh, xh, lsr ip + ret lr + + @ eq -> division by 1: obvious enough... +9: moveq yl, xl + moveq yh, xh + moveq xh, #0 + reteq lr +UNWIND(.fnend) + +UNWIND(.fnstart) +UNWIND(.pad #4) +UNWIND(.save {lr}) +Ldiv0_64: + @ Division by 0: + str lr, [sp, #-8]! + bl __div0 + + @ as wrong as it could be... + mov yl, #0 + mov yh, #0 + mov xh, #0 + ldr pc, [sp], #8 + +UNWIND(.fnend) +ENDPROC(__do_div64) +.popsection diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S new file mode 100644 index 0000000..76968ce --- /dev/null +++ b/arch/arm/lib/lib1funcs.S @@ -0,0 +1,429 @@ +/* + * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines + * + * Author: Nicolas Pitre <nico@fluxnic.net> + * - contributed to gcc-3.4 on Sep 30, 2003 + * - adapted for the Linux kernel on Oct 2, 2003 + */ + +/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <linux/linkage.h> +#include <asm/assembler.h> + +/* + * U-Boot compatibility bit, define empty UNWIND() macro as, since we + * do not support stack unwinding and define CONFIG_AEABI to make all + * of the functions available without diverging from Linux code. + */ +#ifdef __UBOOT__ +#define UNWIND(x...) +#define CONFIG_AEABI +#endif + +.macro ARM_DIV_BODY dividend, divisor, result, curbit + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \curbit, \divisor + clz \result, \dividend + sub \result, \curbit, \result + mov \curbit, #1 + mov \divisor, \divisor, lsl \result + mov \curbit, \curbit, lsl \result + mov \result, #0 + +#else + + @ Initially shift the divisor left 3 bits if possible, + @ set curbit accordingly. This allows for curbit to be located + @ at the left end of each 4 bit nibbles in the division loop + @ to save one loop in most cases. + tst \divisor, #0xe0000000 + moveq \divisor, \divisor, lsl #3 + moveq \curbit, #8 + movne \curbit, #1 + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + movlo \curbit, \curbit, lsl #4 + blo 1b + + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + movlo \curbit, \curbit, lsl #1 + blo 1b + + mov \result, #0 + +#endif + + @ Division loop +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + orrhs \result, \result, \curbit + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + orrhs \result, \result, \curbit, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + orrhs \result, \result, \curbit, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + orrhs \result, \result, \curbit, lsr #3 + cmp \dividend, #0 @ Early termination? + movsne \curbit, \curbit, lsr #4 @ No, any more bits to do? + movne \divisor, \divisor, lsr #4 + bne 1b + +.endm + + +.macro ARM_DIV2_ORDER divisor, order + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \order, \divisor + rsb \order, \order, #31 + +#else + + cmp \divisor, #(1 << 16) + movhs \divisor, \divisor, lsr #16 + movhs \order, #16 + movlo \order, #0 + + cmp \divisor, #(1 << 8) + movhs \divisor, \divisor, lsr #8 + addhs \order, \order, #8 + + cmp \divisor, #(1 << 4) + movhs \divisor, \divisor, lsr #4 + addhs \order, \order, #4 + + cmp \divisor, #(1 << 2) + addhi \order, \order, #3 + addls \order, \order, \divisor, lsr #1 + +#endif + +.endm + + +.macro ARM_MOD_BODY dividend, divisor, order, spare + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \order, \divisor + clz \spare, \dividend + sub \order, \order, \spare + mov \divisor, \divisor, lsl \order + +#else + + mov \order, #0 + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + addlo \order, \order, #4 + blo 1b + + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + addlo \order, \order, #1 + blo 1b + +#endif + + @ Perform all needed subtractions to keep only the reminder. + @ Do comparisons in batch of 4 first. + subs \order, \order, #3 @ yes, 3 is intended here + blt 2f + +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + cmp \dividend, #1 + mov \divisor, \divisor, lsr #4 + subsge \order, \order, #4 + bge 1b + + tst \order, #3 + teqne \dividend, #0 + beq 5f + + @ Either 1, 2 or 3 comparison/subtractions are left. +2: cmn \order, #2 + blt 4f + beq 3f + cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +3: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +4: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor +5: +.endm + + +.pushsection .text.__udivsi3, "ax" +ENTRY(__udivsi3) +ENTRY(__aeabi_uidiv) +UNWIND(.fnstart) + + subs r2, r1, #1 + reteq lr + bcc Ldiv0 + cmp r0, r1 + bls 11f + tst r1, r2 + beq 12f + + ARM_DIV_BODY r0, r1, r2, r3 + + mov r0, r2 + ret lr + +11: moveq r0, #1 + movne r0, #0 + ret lr + +12: ARM_DIV2_ORDER r1, r2 + + mov r0, r0, lsr r2 + ret lr + +UNWIND(.fnend) +ENDPROC(__udivsi3) +ENDPROC(__aeabi_uidiv) +.popsection + +.pushsection .text.__umodsi3, "ax" +ENTRY(__umodsi3) +UNWIND(.fnstart) + + subs r2, r1, #1 @ compare divisor with 1 + bcc Ldiv0 + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + retls lr + + ARM_MOD_BODY r0, r1, r2, r3 + + ret lr + +UNWIND(.fnend) +ENDPROC(__umodsi3) +.popsection + +.pushsection .text.__divsi3, "ax" +ENTRY(__divsi3) +ENTRY(__aeabi_idiv) +UNWIND(.fnstart) + + cmp r1, #0 + eor ip, r0, r1 @ save the sign of the result. + beq Ldiv0 + rsbmi r1, r1, #0 @ loops below use unsigned. + subs r2, r1, #1 @ division by 1 or -1 ? + beq 10f + movs r3, r0 + rsbmi r3, r0, #0 @ positive dividend value + cmp r3, r1 + bls 11f + tst r1, r2 @ divisor is power of 2 ? + beq 12f + + ARM_DIV_BODY r3, r1, r0, r2 + + cmp ip, #0 + rsbmi r0, r0, #0 + ret lr + +10: teq ip, r0 @ same sign ? + rsbmi r0, r0, #0 + ret lr + +11: movlo r0, #0 + moveq r0, ip, asr #31 + orreq r0, r0, #1 + ret lr + +12: ARM_DIV2_ORDER r1, r2 + + cmp ip, #0 + mov r0, r3, lsr r2 + rsbmi r0, r0, #0 + ret lr + +UNWIND(.fnend) +ENDPROC(__divsi3) +ENDPROC(__aeabi_idiv) +.popsection + +.pushsection .text.__modsi3, "ax" +ENTRY(__modsi3) +UNWIND(.fnstart) + + cmp r1, #0 + beq Ldiv0 + rsbmi r1, r1, #0 @ loops below use unsigned. + movs ip, r0 @ preserve sign of dividend + rsbmi r0, r0, #0 @ if negative make positive + subs r2, r1, #1 @ compare divisor with 1 + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + bls 10f + + ARM_MOD_BODY r0, r1, r2, r3 + +10: cmp ip, #0 + rsbmi r0, r0, #0 + ret lr + +UNWIND(.fnend) +ENDPROC(__modsi3) +.popsection + +#ifdef CONFIG_AEABI + +.pushsection .text.__aeabi_uidivmod, "ax" +ENTRY(__aeabi_uidivmod) +UNWIND(.fnstart) +UNWIND(.save {r0, r1, ip, lr} ) + + stmfd sp!, {r0, r1, ip, lr} + bl __aeabi_uidiv + ldmfd sp!, {r1, r2, ip, lr} + mul r3, r0, r2 + sub r1, r1, r3 + ret lr + +UNWIND(.fnend) +ENDPROC(__aeabi_uidivmod) +.popsection + +.pushsection .text.__aeabi_uidivmod, "ax" +ENTRY(__aeabi_idivmod) +UNWIND(.fnstart) +UNWIND(.save {r0, r1, ip, lr} ) + + stmfd sp!, {r0, r1, ip, lr} + bl __aeabi_idiv + ldmfd sp!, {r1, r2, ip, lr} + mul r3, r0, r2 + sub r1, r1, r3 + ret lr + +UNWIND(.fnend) +ENDPROC(__aeabi_idivmod) +.popsection + +#endif + +.pushsection .text.Ldiv0, "ax" +Ldiv0: +UNWIND(.fnstart) +UNWIND(.pad #4) +UNWIND(.save {lr}) + + str lr, [sp, #-8]! + bl __div0 + mov r0, #0 @ About as wrong as it could be. + ldr pc, [sp], #8 + +UNWIND(.fnend) +ENDPROC(Ldiv0) +.popsection + +/* Thumb-1 specialities */ +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2) +.pushsection .text.__gnu_thumb1_case_sqi, "ax" +ENTRY(__gnu_thumb1_case_sqi) + push {r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r1, r1, #1 + ldrsb r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r1} + bx lr +ENDPROC(__gnu_thumb1_case_sqi) +.popsection + +.pushsection .text.__gnu_thumb1_case_uqi, "ax" +ENTRY(__gnu_thumb1_case_uqi) + push {r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r1, r1, #1 + ldrb r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r1} + bx lr +ENDPROC(__gnu_thumb1_case_uqi) +.popsection + +.pushsection .text.__gnu_thumb1_case_shi, "ax" +ENTRY(__gnu_thumb1_case_shi) + push {r0, r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r0, r0, #1 + lsls r1, r1, #1 + ldrsh r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r0, r1} + bx lr +ENDPROC(__gnu_thumb1_case_shi) +.popsection + +.pushsection .text.__gnu_thumb1_case_uhi, "ax" +ENTRY(__gnu_thumb1_case_uhi) + push {r0, r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r0, r0, #1 + lsls r1, r1, #1 + ldrh r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r0, r1} + bx lr +ENDPROC(__gnu_thumb1_case_uhi) +.popsection +#endif diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/lshrdi3.S index 1f9b916..ead33e5 100644 --- a/arch/arm/lib/_lshrdi3.S +++ b/arch/arm/lib/lshrdi3.S @@ -5,6 +5,7 @@ */ #include <linux/linkage.h> +#include <asm/assembler.h> #ifdef __ARMEB__ #define al r1 @@ -14,15 +15,20 @@ #define ah r1 #endif -.globl __lshrdi3 -__lshrdi3: +.pushsection .text.__lshldi3, "ax" +ENTRY(__lshrdi3) ENTRY(__aeabi_llsr) subs r3, r2, #32 rsb ip, r2, #32 movmi al, al, lsr r2 movpl al, ah, lsr r3 - orrmi al, al, ah, lsl ip + ARM( orrmi al, al, ah, lsl ip ) + THUMB( lslmi r3, ah, ip ) + THUMB( orrmi al, al, r3 ) mov ah, ah, lsr r2 - mov pc, lr + ret lr + +ENDPROC(__lshrdi3) ENDPROC(__aeabi_llsr) +.popsection diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 7d9fc0f..00602e9 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -13,12 +13,6 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) -#define W(instr) instr.w -#else -#define W(instr) instr -#endif - #define LDR1W_SHIFT 0 #define STR1W_SHIFT 0 diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S new file mode 100644 index 0000000..d7c93e7 --- /dev/null +++ b/arch/arm/lib/muldi3.S @@ -0,0 +1,48 @@ +/* + * linux/arch/arm/lib/muldi3.S + * + * Author: Nicolas Pitre + * Created: Oct 19, 2005 + * Copyright: Monta Vista Software, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +#ifdef __ARMEB__ +#define xh r0 +#define xl r1 +#define yh r2 +#define yl r3 +#else +#define xl r0 +#define xh r1 +#define yl r2 +#define yh r3 +#endif + +.pushsection .text.__muldi3, "ax" +ENTRY(__muldi3) +ENTRY(__aeabi_lmul) + + mul xh, yl, xh + mla xh, xl, yh, xh + mov ip, xl, lsr #16 + mov yh, yl, lsr #16 + bic xl, xl, ip, lsl #16 + bic yl, yl, yh, lsl #16 + mla xh, yh, ip, xh + mul yh, xl, yh + mul xl, yl, xl + mul ip, yl, ip + adds xl, xl, yh, lsl #16 + adc xh, xh, yh, lsr #16 + adds xl, xl, ip, lsl #16 + adc xh, xh, ip, lsr #16 + ret lr + +ENDPROC(__muldi3) +ENDPROC(__aeabi_lmul) +.popsection diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/uldivmod.S index 426c2f2..7246996 100644 --- a/arch/arm/lib/_uldivmod.S +++ b/arch/arm/lib/uldivmod.S @@ -9,10 +9,6 @@ #include <linux/linkage.h> #include <asm/assembler.h> -/* We don't use Thumb instructions for now */ -#define ARM(x...) x -#define THUMB(x...) - /* * A, Q = r0 + (r1 << 32) * B, R = r2 + (r3 << 32) @@ -37,7 +33,9 @@ THUMB( TMP .req r8 ) +.pushsection .text.__aeabi_uldivmod, "ax" ENTRY(__aeabi_uldivmod) + stmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) lr} @ Test if B == 0 orrs ip, B_0, B_1 @ Z set -> B == 0 @@ -226,7 +224,9 @@ THUMB( orrpl A_0, A_0, TMP ) @ Shift A to the right by the appropriate amount. rsb D_1, D_0, #32 mov Q_0, A_0, lsr D_0 - orr Q_0, A_1, lsl D_1 + ARM( orr Q_0, Q_0, A_1, lsl D_1 ) + THUMB( lsl A_1, D_1 ) + THUMB( orr Q_0, A_1 ) mov Q_1, A_1, lsr D_0 @ Move C to R mov R_0, C_0 @@ -243,3 +243,4 @@ L_div_by_0: mov R_1, #0 ldmfd sp!, {r4, r5, r6, r7, THUMB(TMP,) pc} ENDPROC(__aeabi_uldivmod) +.popsection diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 49238ed..5cc132b 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -60,6 +60,16 @@ _start: ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK +/* + * Various SoCs need something special and SoC-specific up front in + * order to boot, allow them to set that in their boot0.h file and then + * use it here. + */ +#include <asm/arch/boot0.h> +ARM_SOC_BOOT0_HOOK +#endif + /* ************************************************************************* * diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 9ce775e..73a9c74 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_PTC + bool "SAMA5D2 PTC board" + select CPU_V7 + select SUPPORT_SPL + config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" select CPU_V7 @@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_ptc/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 4424523..d2abf31 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 81e9f69..76fcada 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -162,6 +162,11 @@ int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) if (div > 0xff) return -EINVAL; + if (clk_source == GCK_CSS_UPLL_CLK) { + if (at91_upll_clk_enable()) + return -ENODEV; + } + writel(id, &pmc->pcr); regval = readl(&pmc->pcr); regval &= ~AT91_PMC_PCR_GCKCSS; @@ -231,6 +236,12 @@ u32 at91_get_periph_generated_clk(u32 id) case AT91_PMC_PCR_GCKCSS_PLLA_CLK: freq = gd->arch.plla_rate_hz; break; + case AT91_PMC_PCR_GCKCSS_UPLL_CLK: + freq = AT91_UTMI_PLL_CLK_FREQ; + break; + case AT91_PMC_PCR_GCKCSS_MCK_CLK: + freq = gd->arch.mck_rate_hz; + break; default: printf("Improper GCK clock source selection!\n"); freq = 0; diff --git a/arch/arm/mach-at91/bootparams_atmel.S b/arch/arm/mach-at91/bootparams_atmel.S new file mode 100644 index 0000000..568094b --- /dev/null +++ b/arch/arm/mach-at91/bootparams_atmel.S @@ -0,0 +1,18 @@ +/* + * Atmel SAMA5Dx boot parameter handling + * + * Copyright (c) 2016 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/system.h> +#include <linux/linkage.h> + +ENTRY(save_boot_params) + ldr r0, =bootrom_stash + str r4, [r0, #0] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 8577c74..ca7d7d0 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -20,6 +20,8 @@ #define GCK_CSS_MCK_CLK 4 #define GCK_CSS_AUDIO_CLK 5 +#define AT91_UTMI_PLL_CLK_FREQ 480000000 + static inline unsigned long get_cpu_clk_rate(void) { DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index b040256..b805a2c 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -32,6 +32,30 @@ struct atmel_sfr { #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 +/* Bit field in EBICFG */ +#define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0) +#define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0) +#define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0) +#define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0) +#define AT91_SFR_EBICFG_PULL0 (0x3 << 2) +#define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2) +#define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2) +#define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2) +#define AT91_SFR_EBICFG_SCH0 (0x1 << 4) +#define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4) +#define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4) +#define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8) +#define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8) +#define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8) +#define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8) +#define AT91_SFR_EBICFG_PULL1 (0x3 << 10) +#define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10) +#define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10) +#define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10) +#define AT91_SFR_EBICFG_SCH1 (0x1 << 12) +#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) +#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) + /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index dd5a2a7..ee841da 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -135,7 +135,11 @@ /* * Address Memory Space */ +#define ATMEL_BASE_CS0 0x10000000 #define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_CS1 0x60000000 +#define ATMEL_BASE_CS2 0x70000000 +#define ATMEL_BASE_CS3 0x80000000 #define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 #define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 #define ATMEL_BASE_SDMMC0 0xa0000000 @@ -165,6 +169,7 @@ */ #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) +#define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700) #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) @@ -225,6 +230,18 @@ /* No PMECC Galois table in ROM */ #define NO_GALOIS_TABLE_IN_ROM +/* Boot modes stored by BootROM in r4 */ +#define ATMEL_SAMA5D2_BOOT_FROM_OFF 0 +#define ATMEL_SAMA5D2_BOOT_FROM_MASK 0xf +#define ATMEL_SAMA5D2_BOOT_FROM_SPI (0 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_MCI (1 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_SMC (2 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_TWI (3 << 0) +#define ATMEL_SAMA5D2_BOOT_FROM_QSPI (4 << 0) + +#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF 4 +#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK 0xf + #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); unsigned int get_extension_chip_id(void); diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 27a405a..c4ed224 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -23,6 +23,40 @@ void at91_disable_wdt(void) } #endif +#if defined(CONFIG_SAMA5D2) +struct { + u32 r4; +} bootrom_stash __attribute__((section(".data"))); + +u32 spl_boot_device(void) +{ + u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) & + ATMEL_SAMA5D2_BOOT_FROM_MASK; + u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) & + ATMEL_SAMA5D2_BOOT_DEV_ID_MASK; + +#if defined(CONFIG_SYS_USE_MMC) + if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) { + if (off == 0) + return BOOT_DEVICE_MMC1; + if (off == 1) + return BOOT_DEVICE_MMC2; + printf("ERROR: MMC controller %i not present!\n", dev); + hang(); + } +#endif + +#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH) + if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI) + return BOOT_DEVICE_SPI; +#endif + + printf("ERROR: SMC/TWI/QSPI boot device not supported!\n" + " Boot device %i, controller number %i\n", dev, off); + + return BOOT_DEVICE_NONE; +} +#else u32 spl_boot_device(void) { #ifdef CONFIG_SYS_USE_MMC @@ -34,12 +68,14 @@ u32 spl_boot_device(void) #endif return BOOT_DEVICE_NONE; } +#endif u32 spl_boot_mode(void) { switch (spl_boot_device()) { #ifdef CONFIG_SYS_USE_MMC case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; break; #endif diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index a6a7597..c25fcf3 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -1,9 +1,40 @@ if ARCH_EXYNOS choice - prompt "EXYNOS board select" + prompt "EXYNOS architecture type select" optional +config ARCH_EXYNOS4 + bool "Exynos4 SoC family" + select CPU_V7 + help + Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There + are multiple SoCs in this family including Exynos4210, Exynos4412, + and Exynos4212. + +config ARCH_EXYNOS5 + bool "Exynos5 SoC family" + select CPU_V7 + help + Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and + Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs + in this family including Exynos5250, Exynos5420 and Exynos5800. + +config ARCH_EXYNOS7 + bool "Exynos7 SoC family" + select ARM64 + help + Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or + Cortex-A53 CPU (and some in a big.LITTLE configuration). There are + multiple SoCs in this family including Exynos7420. + +endchoice + +if ARCH_EXYNOS4 + +choice + prompt "EXYNOS4 board select" + config TARGET_SMDKV310 select SUPPORT_SPL bool "Exynos4210 SMDKV310 board" @@ -25,6 +56,14 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board" +endchoice +endif + +if ARCH_EXYNOS5 + +choice + prompt "EXYNOS5 board select" + config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" select OF_CONTROL @@ -68,6 +107,25 @@ config TARGET_PEACH_PIT select OF_CONTROL endchoice +endif + +if ARCH_EXYNOS7 + +choice + prompt "EXYNOS7 board select" + +config TARGET_ESPRESSO7420 + bool "ESPRESSO7420 board" + select ARM64 + select SUPPORT_SPL + select OF_CONTROL + select SPL_DISABLE_OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS7420 + select CLK_EXYNOS + +endchoice +endif config SYS_SOC default "exynos" @@ -81,5 +139,6 @@ source "board/samsung/odroid/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" +source "board/samsung/espresso7420/Kconfig" endif diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 8542f89..0cc6c32 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o +obj-y += soc.o +obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o +obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o @@ -13,6 +15,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o -obj-y += spl_boot.o +obj-y += spl_boot.o tzpc.o obj-y += lowlevel_init.o endif diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index 14a1692..1f722df 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420) IS_EXYNOS_TYPE(exynos5422, 0x5422) #define SAMSUNG_BASE(device, base) \ -static inline unsigned int __attribute__((no_instrument_function)) \ +static inline unsigned long __attribute__((no_instrument_function)) \ samsung_get_base_##device(void) \ { \ if (cpu_is_exynos4()) { \ @@ -288,9 +288,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) SAMSUNG_BASE(i2c, I2C_BASE) SAMSUNG_BASE(i2s, I2S_BASE) SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE) diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h index 17e8f56..1079e1e 100644 --- a/arch/arm/mach-exynos/include/mach/dp_info.h +++ b/arch/arm/mach-exynos/include/mach/dp_info.h @@ -61,7 +61,7 @@ struct edp_video_info { unsigned int color_depth; }; -struct edp_device_info { +struct exynos_dp_priv { struct edp_disp_info disp_info; struct edp_link_train_info lt_info; struct edp_video_info video_info; @@ -72,6 +72,7 @@ struct edp_device_info { unsigned char dpcd_rev; /*support enhanced frame cap */ unsigned char dpcd_efc; + struct exynos_dp *regs; }; enum analog_power_block { @@ -185,7 +186,7 @@ enum { struct exynos_dp_platform_data { - struct edp_device_info *edp_dev_info; + struct exynos_dp_priv *edp_dev_info; }; #ifdef CONFIG_EXYNOS_DP diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index 7fc8e61..81363bd 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h @@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin { }; struct gpio_info { - unsigned int reg_addr; /* Address of register for this part */ + unsigned long reg_addr; /* Address of register for this part */ unsigned int max_gpio; /* Maximum GPIO in this part */ }; diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h index c9e8e06..43b5c01 100644 --- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h +++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h @@ -320,7 +320,7 @@ struct mipi_dsim_lcd_device { int reverse_panel; struct mipi_dsim_device *master; - void *platform_data; + struct exynos_platform_mipi_dsim *platform_data; }; /* @@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver { }; #ifdef CONFIG_EXYNOS_MIPI_DSIM -int exynos_mipi_dsi_init(void); +int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd); #else -static inline int exynos_mipi_dsi_init(void) +static inline int exynos_mipi_dsi_init( + struct exynos_platform_mipi_dsim *dsim_pd) { return 0; } @@ -369,7 +370,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev); void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); -void exynos_init_dsim_platform_data(vidinfo_t *vid); +struct vidinfo; +void exynos_init_dsim_platform_data(struct vidinfo *vid); /* panel driver init based on mipi dsi interface */ void s6e8ax0_init(void); diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index 3f97b31..88f70d9 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -1717,7 +1717,7 @@ void set_usbdrd_phy_ctrl(unsigned int enable); #define POWER_USB_DRD_PHY_CTRL_EN (1 << 0) #define POWER_USB_DRD_PHY_CTRL_DISABLE (0 << 0) -void set_dp_phy_ctrl(unsigned int enable); +void exynos_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 6c39cb2..1e090fd 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -216,9 +216,12 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \ + !defined(CONFIG_SPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); #endif +#endif mem_ctrl_init(actions & DO_MEM_RESET); tzpc_init(); } diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c new file mode 100644 index 0000000..ba6d99d --- /dev/null +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham <thomas.ab@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_EXYNOS7420 +static struct mm_region exynos7420_mem_map[] = { + { + .base = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + .base = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* List terminator */ + .base = 0, + .size = 0, + .attrs = 0, + }, +}; + +struct mm_region *mem_map = exynos7420_mem_map; +#endif diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 12eb79c..fec2df9 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -506,6 +506,9 @@ static int exynos5_pinmux_config(int peripheral, int flags) */ gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE); break; + case PERIPH_ID_PWM0: + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2)); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; @@ -548,6 +551,9 @@ static int exynos5420_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C10: exynos5420_i2c_config(peripheral); break; + case PERIPH_ID_PWM0: + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index cd2d661..c923460 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -147,7 +147,7 @@ static void exynos5_dp_phy_control(unsigned int enable) writel(cfg, &power->dptx_phy_control); } -void set_dp_phy_ctrl(unsigned int enable) +void exynos_dp_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_dp_phy_control(enable); diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 0f116b1..f9c7468 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -11,7 +11,9 @@ void reset_cpu(ulong addr) { +#ifdef CONFIG_CPU_V7 writel(0x1, samsung_get_base_swreset()); +#endif } #ifndef CONFIG_SYS_DCACHE_OFF @@ -21,3 +23,11 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifdef CONFIG_ARM64 +void lowlevel_init(void) +{ + armv8_switch_to_el2(); + armv8_switch_to_el1(); +} +#endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index ca2a119..0f6bf61 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -74,4 +74,16 @@ #define K2G_GPIO_DIR_OFFSET 0x0 #define K2G_GPIO_SETDATA_OFFSET 0x8 +/* BOOTCFG RESETMUX8 */ +#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328) + +/* RESETMUX register definitions */ +#define RSTMUX_LOCK8_SHIFT 0x0 +#define RSTMUX_LOCK8_MASK (0x1 << 0) +#define RSTMUX_OMODE8_SHIFT 0x1 +#define RSTMUX_OMODE8_MASK (0x7 << 1) +#define RSTMUX_OMODE8_DEV_RESET 0x2 +#define RSTMUX_OMODE8_INT 0x3 +#define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4 + #endif /* __ASM_ARCH_HARDWARE_K2G_H */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig new file mode 100644 index 0000000..77d3cfe --- /dev/null +++ b/arch/arm/mach-meson/Kconfig @@ -0,0 +1,31 @@ +if ARCH_MESON + +config MESON_GXBB + bool "Support Meson GXBaby" + select ARM64 + select DM + select DM_SERIAL + help + The Amlogic Meson GXBaby (S905) is an ARM SoC with a + quad-core Cortex-A53 CPU and a Mali-450 GPU. + +if MESON_GXBB + +config TARGET_ODROID_C2 + bool "ODROID-C2" + help + ODROID-C2 is a single board computer based on Meson GXBaby + with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD + slot, eMMC, IR receiver and a 40-pin GPIO header. + +endif + +config SYS_SOC + default "meson" + +config SYS_MALLOC_F_LEN + default 0x1000 + +source "board/hardkernel/odroid-c2/Kconfig" + +endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile new file mode 100644 index 0000000..bf49b8b --- /dev/null +++ b/arch/arm/mach-meson/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o sm.o diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c new file mode 100644 index 0000000..64fa3c1 --- /dev/null +++ b/arch/arm/mach-meson/board.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <linux/err.h> +#include <asm/arch/gxbb.h> +#include <asm/arch/sm.h> +#include <asm/armv8/mmu.h> +#include <asm/unaligned.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + const fdt64_t *val; + int offset; + int len; + + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + + /* Use unaligned access since cache is still disabled */ + gd->ram_size = get_unaligned_be64(&val[1]); + + return 0; +} + +void dram_init_banksize(void) +{ + /* Reserve first 16 MiB of RAM for firmware */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); + gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024); +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(true); +} + +static struct mm_region gxbb_mem_map[] = { + { + .base = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .base = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = gxbb_mem_map; diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c new file mode 100644 index 0000000..1b35a22 --- /dev/null +++ b/arch/arm/mach-meson/sm.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Secure monitor calls. + */ + +#include <common.h> +#include <asm/arch/gxbb.h> +#include <linux/kernel.h> + +#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020 +#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021 +#define FN_EFUSE_READ 0x82000030 +#define FN_EFUSE_WRITE 0x82000031 + +static void *shmem_input; +static void *shmem_output; + +static void meson_init_shmem(void) +{ + struct pt_regs regs; + + if (shmem_input && shmem_output) + return; + + regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE; + smc_call(®s); + shmem_input = (void *)regs.regs[0]; + + regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE; + smc_call(®s); + shmem_output = (void *)regs.regs[0]; + + debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output); +} + +ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + + meson_init_shmem(); + + regs.regs[0] = FN_EFUSE_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + + smc_call(®s); + + if (regs.regs[0] == 0) + return -1; + + memcpy(buffer, shmem_output, min(size, regs.regs[0])); + + return regs.regs[0]; +} diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d3bddb7..2a8afac 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -41,6 +41,9 @@ config DM_I2C config DM_GPIO default y +config BLK + default y + source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c index fefb568..b3d2113 100644 --- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -7,24 +7,24 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3036.h> #include <asm/arch/hardware.h> #include <linux/err.h> -int rk3036_reset_request(struct udevice *dev, enum reset_t type) +int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3036_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; default: @@ -34,12 +34,12 @@ int rk3036_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3036_reset = { - .request = rk3036_reset_request, +static struct sysreset_ops rk3036_sysreset = { + .request = rk3036_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3036) = { - .name = "rk3036_reset", - .id = UCLASS_RESET, - .ops = &rk3036_reset, +U_BOOT_DRIVER(sysreset_rk3036) = { + .name = "rk3036_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3036_sysreset, }; diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c index bf7540a..0aad1c2 100644 --- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c @@ -7,25 +7,25 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3288.h> #include <asm/arch/hardware.h> #include <linux/err.h> -int rk3288_reset_request(struct udevice *dev, enum reset_t type) +int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3288_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; @@ -36,12 +36,12 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3288_reset = { - .request = rk3288_reset_request, +static struct sysreset_ops rk3288_sysreset = { + .request = rk3288_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3288) = { - .name = "rk3288_reset", - .id = UCLASS_RESET, - .ops = &rk3288_reset, +U_BOOT_DRIVER(sysreset_rk3288) = { + .name = "rk3288_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3288_sysreset, }; diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c index 2627eec..a6cabfb 100644 --- a/arch/arm/mach-snapdragon/reset.c +++ b/arch/arm/mach-snapdragon/reset.c @@ -9,12 +9,12 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -static int msm_reset_request(struct udevice *dev, enum reset_t type) +static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) { phys_addr_t addr = dev_get_addr(dev); if (!addr) @@ -23,18 +23,18 @@ static int msm_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops msm_reset_ops = { - .request = msm_reset_request, +static struct sysreset_ops msm_sysreset_ops = { + .request = msm_sysreset_request, }; -static const struct udevice_id msm_reset_ids[] = { +static const struct udevice_id msm_sysreset_ids[] = { { .compatible = "qcom,pshold" }, { } }; U_BOOT_DRIVER(msm_reset) = { - .name = "msm_reset", - .id = UCLASS_RESET, - .of_match = msm_reset_ids, - .ops = &msm_reset_ops, + .name = "msm_sysreset", + .id = UCLASS_SYSRESET, + .of_match = msm_sysreset_ids, + .ops = &msm_sysreset_ops, }; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index dea4ce5..1484607 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_SAMTEC_VINING_FPGA + bool "samtec VIN|ING FPGA (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -53,12 +57,14 @@ config SYS_BOARD default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 + default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES + default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -73,5 +79,6 @@ config SYS_CONFIG_NAME default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA endif diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index ad3d6c4..25367cf 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o obj-$(CONFIG_AXP152_POWER) += pmic_bus.o obj-$(CONFIG_AXP209_POWER) += pmic_bus.o obj-$(CONFIG_AXP221_POWER) += pmic_bus.o +obj-$(CONFIG_AXP809_POWER) += pmic_bus.o obj-$(CONFIG_AXP818_POWER) += pmic_bus.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 20149da..bd15b9b 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -247,6 +247,15 @@ u32 spl_boot_device(void) return -1; /* Never reached */ } +/* + * Properly announce BOOT_DEVICE_BOARD as "FEL". + * Overrides weak function from common/spl/spl.c + */ +void spl_board_announce_boot_device(void) +{ + printf("FEL"); +} + /* No confirmation data available in SPL yet. Hardcode bootmode */ u32 spl_boot_mode(void) { diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 5b81a8d..7c57f02 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -36,7 +36,7 @@ int pmic_bus_init(void) if (!needs_init) return 0; -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, @@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data) return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); #elif defined CONFIG_AXP209_POWER return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); # else @@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data) return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); #elif defined CONFIG_AXP209_POWER return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); # else diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ba6983f..b18a12e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -22,6 +22,7 @@ config TEGRA_ARMV7_COMMON select SPL select SUPPORT_SPL select TEGRA_COMMON + select TEGRA_GPIO config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -50,6 +51,12 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" + select TEGRA_GPIO + select TEGRA_ARMV8_COMMON + +config TEGRA186 + bool "Tegra186 family" + select TEGRA186_GPIO select TEGRA_ARMV8_COMMON endchoice @@ -75,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig" source "arch/arm/mach-tegra/tegra114/Kconfig" source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" +source "arch/arm/mach-tegra/tegra186/Kconfig" endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index b2dbc69..12ee1cd 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifndef CONFIG_TEGRA186 ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += cpu.o @@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif +endif obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ obj-$(CONFIG_TEGRA114) += tegra114/ obj-$(CONFIG_TEGRA124) += tegra124/ +obj-$(CONFIG_TEGRA186) += tegra186/ obj-$(CONFIG_TEGRA210) += tegra210/ diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c new file mode 100644 index 0000000..f4b6152 --- /dev/null +++ b/arch/arm/mach-tegra/board186.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/mmc.h> +#include <asm/arch-tegra/tegra_mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = (1.5 * 1024 * 1024 * 1024); + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +void pad_init_mmc(struct mmc_host *host) +{ +} + +int board_mmc_init(bd_t *bd) +{ + tegra_mmc_init(); + + return 0; +} + +int ft_system_setup(void *blob, bd_t *bd) +{ + return 0; +} diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig new file mode 100644 index 0000000..97cf23f --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/Kconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TEGRA186 + +choice + prompt "Tegra186 board select" + +config TARGET_P2771_0000 + bool "NVIDIA Tegra186 P2771-0000 board" + help + P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The + combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB + micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO + expansion headers. + +endchoice + +config SYS_SOC + default "tegra186" + +source "board/nvidia/p2771-0000/Kconfig" + +endif diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile new file mode 100644 index 0000000..ce4610d --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -0,0 +1,8 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += ../arm64-mmu.o +obj-y += ../board186.o +obj-y += ../lowlevel_init.o +obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 87d1675..ae763ad 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" select CPU_V7 +config ARCH_UNIPHIER_LD11 + bool "UniPhier PH1-LD11 SoC" + select ARM64 + select SPL_SEPARATE_BSS + config ARCH_UNIPHIER_LD20 bool "UniPhier PH1-LD20 SoC" select ARM64 diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 64412e0..5971ad2 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void) rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - readq(rom_boot_rsv0); /* relax */ unmap_sysmem(rom_boot_rsv0); uniphier_smp_setup(); - asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ + asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */ + "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ } diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 2a7ae1b..f853701 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -62,6 +62,13 @@ int board_early_init_f(void) uniphier_pxs2_clk_init(); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + case SOC_UNIPHIER_LD11: + uniphier_ld20_pin_init(); + led_puts("U1"); + uniphier_ld11_clk_init(); + break; +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: uniphier_ld20_pin_init(); diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 845f047..a454126 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -39,6 +39,9 @@ static int uniphier_set_fdt_file(void) int buf_len = 256; int ret; + if (getenv("fdt_file")) + return 0; /* do nothing if it is already set */ + ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat); if (ret) return -EINVAL; @@ -56,9 +59,7 @@ static int uniphier_set_fdt_file(void) strncat(dtb_name, ".dtb", buf_len); - setenv("fdt_file", dtb_name); - - return 0; + return setenv("fdt_file", dtb_name); } int board_late_init(void) diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index f0547c3..ed308f3 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -165,6 +165,23 @@ static const struct uniphier_board_data uniphier_ld6b_data = { }; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) +static const struct uniphier_board_data uniphier_ld11_data = { + .dram_freq = 1600, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x20000000, + .width = 16, + }, + .dram_ch[1] = { + .base = 0xa0000000, + .size = 0x20000000, + .width = 16, + }, +}; +#endif + #if defined(CONFIG_ARCH_UNIPHIER_LD20) static const struct uniphier_board_data uniphier_ld20_data = { .dram_freq = 1866, @@ -216,6 +233,9 @@ static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + { "socionext,ph1-ld11", &uniphier_ld11_data, }, +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) { "socionext,ph1-ld20", &uniphier_ld20_data, }, #endif diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 6cd096e..a898021 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,6 +11,11 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o +else obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o +endif diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c index b092c1b..24255a0 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c @@ -9,6 +9,7 @@ #include <linux/io.h> #include "../sg-regs.h" +#include "../soc-info.h" #include "boot-device.h" static struct boot_device_info boot_device_table[] = { @@ -43,7 +44,7 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, - {BOOT_DEVICE_NOR, "NOR Boot (XECS1)"}, + {BOOT_DEVICE_NOR, "NOR (XECS1)"}, }; static int get_boot_mode_sel(void) @@ -54,8 +55,24 @@ static int get_boot_mode_sel(void) u32 uniphier_ld20_boot_device(void) { int boot_mode; + u32 usb_boot_mask; - if (~readl(SG_PINMON0) & 0x00000780) + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + case SOC_UNIPHIER_LD11: + usb_boot_mask = 0x00000080; + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + usb_boot_mask = 0x00000780; + break; +#endif + default: + BUG(); + } + + if (~readl(SG_PINMON0) & usb_boot_mask) return BOOT_DEVICE_USB; boot_mode = get_boot_mode_sel(); diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c index 0597618..b066ed9 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c @@ -36,14 +36,14 @@ struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_MMC1, "eMMC (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V)"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NOR, "NOR Boot"}, + {BOOT_DEVICE_NOR, "NOR (XECS0)"}, }; static int get_boot_mode_sel(void) diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c index f9726f1..450c43b 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c @@ -37,7 +37,7 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"}, {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V)"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c index 4b06f74..20ff773 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c @@ -32,17 +32,17 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"}, {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"}, - {BOOT_DEVICE_SPI, "SPI 3Byte CS0"}, - {BOOT_DEVICE_SPI, "SPI 4Byte CS0"}, - {BOOT_DEVICE_SPI, "SPI 3Byte CS1"}, - {BOOT_DEVICE_SPI, "SPI 4Byte CS1"}, - {BOOT_DEVICE_SPI, "SPI 4Byte CS0"}, - {BOOT_DEVICE_SPI, "SPI 3Byte CS0"}, + {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"}, + {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"}, + {BOOT_DEVICE_SPI, "SPI (3Byte CS1)"}, + {BOOT_DEVICE_SPI, "SPI (4Byte CS1)"}, + {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"}, + {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"}, {BOOT_DEVICE_NONE, "Reserved"}, }; diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c index a4a3c47..ddf8259 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c @@ -12,7 +12,7 @@ #include "boot-device.h" static struct boot_device_info boot_device_table[] = { - {BOOT_DEVICE_NOR, "NOR boot"}, + {BOOT_DEVICE_NOR, "NOR (XECS0)"}, {BOOT_DEVICE_NONE, "External Master"}, {BOOT_DEVICE_NONE, "Reserved"}, {BOOT_DEVICE_NONE, "Reserved"}, diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index b180f44..d34b9af 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -39,7 +39,8 @@ u32 spl_boot_device_raw(void) case SOC_UNIPHIER_LD6B: return uniphier_pxs2_boot_device(); #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: case SOC_UNIPHIER_LD20: return uniphier_ld20_boot_device(); #endif @@ -50,11 +51,30 @@ u32 spl_boot_device_raw(void) u32 spl_boot_device(void) { - u32 ret; + u32 mode; - ret = spl_boot_device_raw(); + mode = spl_boot_device_raw(); - return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret; + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + case SOC_UNIPHIER_PXS2: + case SOC_UNIPHIER_LD6B: + if (mode == BOOT_DEVICE_USB) + mode = BOOT_DEVICE_NOR; + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: + case SOC_UNIPHIER_LD20: + if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB) + mode = BOOT_DEVICE_BOARD; + break; +#endif + default: + break; + } + + return mode; } u32 spl_boot_mode(void) diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index fa97dc5..a8ee382 100644 --- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -39,7 +39,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) uniphier_pxs2_boot_mode_show(); break; #endif -#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD11: case SOC_UNIPHIER_LD20: uniphier_ld20_boot_mode_show(); break; diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c new file mode 100644 index 0000000..86292b6 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <linux/io.h> +#include <asm/processor.h> + +#include "../soc-info.h" + +void spl_board_announce_boot_device(void) +{ + printf("eMMC"); +} + +struct uniphier_romfunc_table { + void *mmc_send_cmd; + void *mmc_card_blockaddr; + void *mmc_switch_part; + void *mmc_load_image; +}; + +static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = { + .mmc_send_cmd = (void *)0x20d8, + .mmc_card_blockaddr = (void *)0x1b68, + .mmc_switch_part = (void *)0x1c38, + .mmc_load_image = (void *)0x2e48, +}; + +static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = { + .mmc_send_cmd = (void *)0x2130, + .mmc_card_blockaddr = (void *)0x1ba0, + .mmc_switch_part = (void *)0x1c70, + .mmc_load_image = (void *)0x2ef0, +}; + +int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32), + int (**card_blockaddr)(u32), + int (**switch_part)(int), + int (**load_image)(u32, uintptr_t, u32)) +{ + const struct uniphier_romfunc_table *table; + + switch (uniphier_get_soc_type()) { + case SOC_UNIPHIER_LD11: + table = &uniphier_ld11_romfunc_table; + break; + case SOC_UNIPHIER_LD20: + table = &uniphier_ld20_romfunc_table; + break; + default: + printf("unsupported SoC\n"); + return -EINVAL; + } + + *send_cmd = table->mmc_send_cmd; + *card_blockaddr = table->mmc_card_blockaddr; + *switch_part = table->mmc_switch_part; + *load_image = table->mmc_load_image; + + return 0; +} + +int spl_board_load_image(void) +{ + int (*send_cmd)(u32 cmd, u32 arg); + int (*card_blockaddr)(u32 rca); + int (*switch_part)(int part); + int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt); + u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + const u32 rca = 0x1000; /* RCA assigned by Boot ROM */ + int ret; + + ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr, + &switch_part, &load_image); + if (ret) + return ret; + + /* + * deselect card before SEND_CSD command. + * Do not check the return code. It fails, but it is OK. + */ + (*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */ + + /* reset CMD Line */ + writeb(0x6, 0x5a00022f); + while (readb(0x5a00022f)) + cpu_relax(); + + ret = (*card_blockaddr)(rca); + if (ret) { + debug("card is block addressing\n"); + } else { + debug("card is byte addressing\n"); + dev_addr *= 512; + } + + ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */ + if (ret) + printf("failed to select card\n"); + + ret = (*switch_part)(1); /* Switch to Boot Partition 1 */ + if (ret) + printf("failed to switch partition\n"); + + ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1); + if (ret) { + printf("failed to load image\n"); + return ret; + } + + ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE); + if (ret) + return ret; + + ret = (*load_image)(dev_addr, spl_image.load_addr, + spl_image.size / 512); + if (ret) { + printf("failed to load image\n"); + return ret; + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 93e9d91..1428e0c 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c new file mode 100644 index 0000000..92a0733 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/bitops.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sg-regs.h" + +void uniphier_ld11_clk_init(void) +{ + if (readl(SG_PINMON0) & BIT(27)) { + /* if booted without stand-by MPU */ + + writel(1, SG_ETPHYPSHUT); + writel(1, SG_ETPHYCNT); + + udelay(1); /* wait for regulator level 1.1V -> 2.5V */ + + writel(3, SG_ETPHYCNT); + writel(3, SG_ETPHYPSHUT); + writel(7, SG_ETPHYCNT); + } +} diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index f9646c0..6ad4c76 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) puts("PH1-LD6b (MN2WS0320)"); break; case 0x31: - puts("PH1-LD11 ()"); + puts("PH1-LD11 (SC1405AP1)"); break; case 0x32: puts("PH1-LD20 (SC1401AJ1)"); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 41aa53b..5b9d892 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o else diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c new file mode 100644 index 0000000..1be18a8 --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-ld11.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 Socionext Inc. + */ + +#include <common.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/processor.h> + +#include "../init.h" +#include "umc64-regs.h" + +#define CONFIG_DDR_FREQ 1866 + +#define DRAM_CH_NR 2 + +enum dram_freq { + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +/* umc */ +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; +static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; +static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D}; +static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200}; +static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808}; + +static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810}; +static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810}; +static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004}; +static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004}; +static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203}; +static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605}; + +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, + unsigned long size, int ch) +{ + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); + writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); + writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE); + writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF); + writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG); + + writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); + writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); + + writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); + writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); + + writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); + writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); + + writel(0x00000003, dc_base + UMC_ACSSETA); + writel(0x00000103, dc_base + UMC_FLOWCTLG); + writel(umc_acssetb[ch], dc_base + UMC_ACSSETB); + writel(0x02020200, dc_base + UMC_SPCSETB); + writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); + writel(0x00000002, dc_base + UMC_ACFETCHCTRL); + + return 0; +} + +static int umc_ch_init(void __iomem *umc_ch_base, + enum dram_freq freq, unsigned long size, int ch) +{ + void __iomem *dc_base = umc_ch_base; + + return umc_dc_init(dc_base, freq, size, ch); +} + +static void um_init(void __iomem *um_base) +{ + writel(0x00000001, um_base + UMC_SIORST); + writel(0x00000001, um_base + UMC_VO0RST); + writel(0x00000001, um_base + UMC_VPERST); + writel(0x00000001, um_base + UMC_RGLRST); + writel(0x00000001, um_base + UMC_A2DRST); + writel(0x00000001, um_base + UMC_DMDRST); +} + +int uniphier_ld11_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *um_base = (void __iomem *)0x5B800000; + void __iomem *umc_ch_base = (void __iomem *)0x5BC00000; + enum dram_freq freq; + int ch, ret; + + switch (bd->dram_freq) { + case 1600: + freq = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + return -EINVAL; + } + + for (ch = 0; ch < bd->dram_nr_ch; ch++) { + unsigned long size = bd->dram_ch[ch].size; + unsigned int width = bd->dram_ch[ch].width; + + ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + umc_ch_base += 0x00200000; + } + + um_init(um_base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c index 4614dac..186a398 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld20.c +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -15,7 +15,7 @@ #include "../init.h" #include "ddrphy-ld20-regs.h" -#include "umc-ld20-regs.h" +#include "umc64-regs.h" #define DRAM_CH_NR 3 @@ -200,9 +200,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, writel(umc_dataset[freq], dc_base + UMC_DATASET); writel(0x00400020, dc_base + UMC_DCCGCTL); - writel(0x00000003, dc_base + UMC_ACSCTLA); + writel(0x00000003, dc_base + UMC_ACSSETA); writel(0x00000103, dc_base + UMC_FLOWCTLG); - writel(0x00010200, dc_base + UMC_ACSSETA); + writel(0x00010200, dc_base + UMC_ACSSETB); writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA); writel(0x00004444, dc_base + UMC_FLOWCTLC); diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h index 46e513c..860d04e 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h +++ b/arch/arm/mach-uniphier/dram/umc64-regs.h @@ -18,13 +18,15 @@ #define UMC_INITSET 0x00000040 #define UMC_INITSTAT 0x00000044 #define UMC_CMDCTLE 0x00000050 +#define UMC_CMDCTLF 0x00000054 +#define UMC_CMDCTLG 0x00000058 #define UMC_SPCSETB 0x00000084 #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ #define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ #define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ -#define UMC_ACSCTLA 0x000000C0 -#define UMC_ACSSETA 0x000000C4 +#define UMC_ACSSETA 0x000000C0 +#define UMC_ACSSETB 0x000000C4 #define UMC_MEMCONF0A 0x00000200 #define UMC_MEMCONF0B 0x00000204 #define UMC_MEMCONFCH 0x00000240 @@ -32,6 +34,7 @@ #define UMC_FLOWCTLA 0x00000400 #define UMC_FLOWCTLB 0x00000404 #define UMC_FLOWCTLC 0x00000408 +#define UMC_ACFETCHCTRL 0x00000460 #define UMC_FLOWCTLG 0x00000508 #define UMC_RDATACTL_D0 0x00000600 #define UMC_WDATACTL_D0 0x00000604 @@ -42,6 +45,7 @@ #define UMC_ODTCTL_D1 0x0000061C #define UMC_RESPCTL 0x00000624 #define UMC_DIRECTBUSCTRLA 0x00000680 +#define UMC_DEBUGC 0x00000718 #define UMC_DCCGCTL 0x00000720 #define UMC_DICGCTLA 0x00000724 #define UMC_DICGCTLB 0x00000728 @@ -70,4 +74,12 @@ #define UMC_MBUS9 0x00002478 #define UMC_MBUS10 0x000024F8 +/* UMC1 register */ +#define UMC_SIORST 0x00000728 +#define UMC_VO0RST 0x0000073c +#define UMC_VPERST 0x00000744 +#define UMC_RGLRST 0x00000750 +#define UMC_A2DRST 0x00000764 +#define UMC_DMDRST 0x00000770 + #endif /* UMC_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 9242b41..755a361 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c new file mode 100644 index 0000000..c94d83c --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_PERI; + writel(tmp, SC_CLKCTRL4); + + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile index a103902..7177a8c 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -3,4 +3,5 @@ # obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index ab0a68d..cba0bc9 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); +int uniphier_ld11_init(const struct uniphier_board_data *bd); int uniphier_ld20_init(const struct uniphier_board_data *bd); #if defined(CONFIG_MICRO_SUPPORT_CARD) @@ -81,6 +82,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); +int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd); int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd); @@ -91,6 +93,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); int uniphier_ld20_umc_init(const struct uniphier_board_data *bd); +int uniphier_ld11_umc_init(const struct uniphier_board_data *bd); void uniphier_sld3_pin_init(void); void uniphier_ld4_pin_init(void); @@ -105,6 +108,7 @@ void uniphier_ld4_clk_init(void); void uniphier_pro4_clk_init(void); void uniphier_pro5_clk_init(void); void uniphier_pxs2_clk_init(void); +void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void); void cci500_init(int nr_slaves); diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index b58e6c8..dcaa445 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c new file mode 100644 index 0000000..de2dc62 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +#include "../init.h" +#include "../micro-support-card.h" + +int uniphier_ld11_init(const struct uniphier_board_data *bd) +{ + uniphier_sbc_init_savepin(bd); + uniphier_pxs2_sbc_init(bd); + uniphier_ld20_early_pin_init(bd); + + support_card_reset(); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + uniphier_ld11_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = uniphier_ld11_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + dcache_disable(); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index 660ad45..7f66053 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) led_puts("L5"); + dcache_disable(); + return 0; } diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index 15a53ce..77e5b99 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -55,6 +55,11 @@ void spl_board_init(void) uniphier_pxs2_init(param); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD11) + case SOC_UNIPHIER_LD11: + uniphier_ld11_init(param); + break; +#endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: uniphier_ld20_init(param); diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index b579cb0..7f4d9f7 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index 38da253..ec3c22c 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 1d71ce8..a179d61 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -59,6 +59,9 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) +#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) +#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) + /* Pin Control */ #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index d396a13..db3c579 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,41 +1,5 @@ if ARCH_ZYNQ -config ZYNQ_CUSTOM_INIT - bool "Use custom ps7_init provided by Xilinx tool" - help - U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants. - If you want to override them with customized ones - or ps7_init code for your board is missing, please say Y here - and add ones into board/xilinx/zynq/custom_hw_platform/ directory. - -choice - prompt "Xilinx Zynq board select" - default TARGET_ZYNQ_ZC702 - -config TARGET_ZYNQ_ZED - bool "Zynq ZedBoard" - -config TARGET_ZYNQ_MICROZED - bool "Zynq MicroZed" - -config TARGET_ZYNQ_PICOZED - bool "Zynq PicoZed" - -config TARGET_ZYNQ_ZC702 - bool "Zynq ZC702 Board" - -config TARGET_ZYNQ_ZC706 - bool "Zynq ZC706 Board" - -config TARGET_ZYNQ_ZC770 - bool "Zynq ZC770 Board" - select ZYNQ_CUSTOM_INIT - -config TARGET_ZYNQ_ZYBO - bool "Zynq Zybo Board" - -endchoice - config SYS_BOARD default "zynq" @@ -46,11 +10,11 @@ config SYS_SOC default "zynq" config SYS_CONFIG_NAME - default "zynq_zed" if TARGET_ZYNQ_ZED - default "zynq_microzed" if TARGET_ZYNQ_MICROZED - default "zynq_picozed" if TARGET_ZYNQ_PICOZED - default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 - default "zynq_zc770" if TARGET_ZYNQ_ZC770 - default "zynq_zybo" if TARGET_ZYNQ_ZYBO + string "Board configuration name" + default "zynq-common" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. endif diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 723019d..6c5415a 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -90,3 +90,28 @@ __weak void ps7_init(void) * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. */ } + +__weak int ps7_post_config(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. + */ + return 0; +} + +void spl_board_prepare_for_boot(void) +{ + ps7_post_config(); + debug("SPL bye\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index 8b047ec..7d48e9a 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -6,28 +6,8 @@ #ifndef __ASM_U_BOOT_H__ #define __ASM_U_BOOT_H__ 1 -#ifdef CONFIG_SYS_GENERIC_BOARD /* Use the generic board which requires a unified bd_info */ #include <asm-generic/u-boot.h> -#else - -typedef struct bd_info { - unsigned char bi_phy_id[4]; - unsigned long bi_board_number; - void *bi_boot_params; - struct { - unsigned long start; - unsigned long size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; - unsigned long bi_flashstart; - unsigned long bi_flashsize; - unsigned long bi_flashoffset; -} bd_t; - -#define bi_memstart bi_dram[0].start -#define bi_memsize bi_dram[0].size - -#endif /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_AVR32 diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 911c0d3..8203844 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -14,47 +14,8 @@ #ifndef __U_BOOT_H__ #define __U_BOOT_H__ -/* - * Board information passed to Linux kernel from U-Boot - * - * include/asm-ppc/u-boot.h - */ - -#ifdef CONFIG_SYS_GENERIC_BOARD /* Use the generic board which requires a unified bd_info */ #include <asm-generic/u-boot.h> -#else - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#ifdef CONFIG_PCI - unsigned long bi_pcifreq; /* pci Freq in MHz */ -#endif -#ifdef CONFIG_EXTRA_CLOCK - unsigned long bi_inpfreq; /* input Freq in MHz */ - unsigned long bi_vcofreq; /* vco Freq in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ -#endif -} bd_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* !CONFIG_SYS_GENERIC_BOARD */ - /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_M68K diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h index 11f3dd0..94f0562 100644 --- a/arch/microblaze/include/asm/asm.h +++ b/arch/microblaze/include/asm/asm.h @@ -50,7 +50,7 @@ #define NOP __asm__ __volatile__ ("nop"); /* use machine status registe USE_MSR_REG */ -#if XILINX_USE_MSR_INSTR == 1 +#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1 #define MSRSET(val) \ __asm__ __volatile__ ("msrset r0," #val ); diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h index 724f5bd..8f67ec7 100644 --- a/arch/microblaze/include/asm/string.h +++ b/arch/microblaze/include/asm/string.h @@ -17,13 +17,11 @@ #define __MICROBLAZE_STRING_H__ #if 0 -#define __HAVE_ARCH_BCOPY #define __HAVE_ARCH_MEMCPY #define __HAVE_ARCH_MEMSET #define __HAVE_ARCH_MEMMOVE extern void *memcpy (void *, const void *, __kernel_size_t); -extern void bcopy (const char *, char *, int); extern void *memset (void *, int, __kernel_size_t); extern void *memmove (void *, const void *, __kernel_size_t); #endif diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index dc34c18..5c30ae9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,12 +23,19 @@ config TARGET_QEMU_MIPS config TARGET_MALTA bool "Support malta" + select DM + select DM_SERIAL select DYNAMIC_IO_PORT_BASE + select OF_CONTROL + select OF_ISA_BUS select SUPPORTS_BIG_ENDIAN select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS32_R6 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_CPU_MIPS64_R6 select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6 @@ -221,6 +228,9 @@ config MIPS_TUNE_14KC config MIPS_TUNE_24KC bool +config MIPS_TUNE_34KC + bool + config MIPS_TUNE_74KC bool @@ -236,6 +246,40 @@ config SWAP_IO_SPACE config SYS_MIPS_CACHE_INIT_RAM_LOAD bool +config SYS_DCACHE_SIZE + int + default 0 + help + The total size of the L1 Dcache, if known at compile time. + +config SYS_DCACHE_LINE_SIZE + hex + default 0 + help + The size of L1 Dcache lines, if known at compile time. + +config SYS_ICACHE_SIZE + int + default 0 + help + The total size of the L1 ICache, if known at compile time. + +config SYS_ICACHE_LINE_SIZE + int + default 0 + help + The size of L1 Icache lines, if known at compile time. + +config SYS_CACHE_SIZE_AUTO + def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ + SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 + help + Select this (or let it be auto-selected by not defining any cache + sizes) in order to allow U-Boot to automatically detect the sizes + of caches at runtime. This has a small cost in code size & runtime + so if you know the cache configuration for your system at compile + time it would be beneficial to configure it. + config MIPS_L1_CACHE_SHIFT_4 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 655a493..efe7e44 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -4,6 +4,12 @@ head-y := arch/mips/cpu/start.o +ifeq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_SPL_START_S_PATH),) +head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o +endif +endif + libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ @@ -28,6 +34,7 @@ arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc +tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc # Include default header files diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 609a998..dcd3460 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -65,7 +65,7 @@ else PF_ABICALLS := -mabicalls PF_PIC := -fpic PF_PIE := -pie -PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding +PF_OBJCOPY := -j .got -j .rel.dyn -j .padding PF_OBJCOPY += -j .dtb.init.rodata endif @@ -74,4 +74,5 @@ PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections $(PF_PIE) -OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY) +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list +OBJCOPYFLAGS += $(PF_OBJCOPY) diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds new file mode 100644 index 0000000..07004ea --- /dev/null +++ b/arch/mips/cpu/u-boot-spl.lds @@ -0,0 +1,90 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : { + *(.text*) + } > .spl_mem + + . = ALIGN(4); + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } > .spl_mem + + . = ALIGN(4); + .data : { + *(SORT_BY_ALIGNMENT(.data*)) + *(SORT_BY_ALIGNMENT(.sdata*)) + } > .spl_mem + +#ifdef CONFIG_SPL_DM + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .spl_mem +#endif + + . = ALIGN(4); + __image_copy_end = .; + + .bss (NOLOAD) : { + __bss_start = .; + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } > .bss_mem + + .rel.dyn (NOLOAD) : { + *(.rel.dyn) + } + + .dynsym : { + *(.dynsym) + } + + .dynbss : { + *(.dynbss) + } + + .dynstr : { + *(.dynstr) + } + + .dynamic : { + *(.dynamic) + } + + .plt : { + *(.plt) + } + + .interp : { + *(.interp) + } + + .gnu : { + *(.gnu*) + } + + .MIPS.stubs : { + *(.MIPS.stubs) + } + + .hash : { + *(.hash) + } +} diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index a94b745..2f04d73 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb +dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts index e31f601..a934a58 100644 --- a/arch/mips/dts/ap121.dts +++ b/arch/mips/dts/ap121.dts @@ -41,3 +41,8 @@ reg = <0>; }; }; + +&gmac0 { + phy-mode = "rmii"; + status = "okay"; +}; diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi index 00896b2..971f13e 100644 --- a/arch/mips/dts/ar933x.dtsi +++ b/arch/mips/dts/ar933x.dtsi @@ -75,7 +75,7 @@ }; gmac0: eth@0x19000000 { - compatible = "qca,ag7240-mac"; + compatible = "qca,ag933x-mac"; reg = <0x19000000 0x200>; phy = <&phy0>; phy-mode = "rmii"; @@ -92,7 +92,7 @@ }; gmac1: eth@0x1a000000 { - compatible = "qca,ag7240-mac"; + compatible = "qca,ag933x-mac"; reg = <0x1a000000 0x200>; phy = <&phy0>; phy-mode = "rgmii"; diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts new file mode 100644 index 0000000..d339229 --- /dev/null +++ b/arch/mips/dts/mti,malta.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +/memreserve/ 0x00000000 0x00001000; /* Exception vectors */ +/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mti,malta"; + + chosen { + stdout-path = &uart0; + }; + + isa@0 { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0x1000>; + + uart0: serial@3f8 { + compatible = "ns16550a"; + + reg = <1 0x3f8 0x40>; + reg-shift = <0>; + + clock-frequency = <1843200>; + + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 806bd26..0cea581 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -12,4 +12,11 @@ #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) +/* + * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for + * DMA buffer alignment. Satisfy those drivers by providing it as a synonym + * of ARCH_DMA_MINALIGN for now. + */ +#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN + #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 3f230b0..37f8ed5 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -15,14 +15,6 @@ struct arch_global_data { #ifdef CONFIG_DYNAMIC_IO_PORT_BASE unsigned long io_port_base; #endif -#ifdef CONFIG_JZSOC - /* There are other clocks in the jz4740 */ - unsigned long per_clk; /* Peripheral bus clock */ - unsigned long dev_clk; /* Device clock */ - unsigned long sys_clk; - unsigned long tbl; - unsigned long lastinc; -#endif #ifdef CONFIG_ARCH_ATH79 unsigned long id; unsigned long soc; diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 723a60a..5b86386 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -92,11 +92,8 @@ static inline unsigned long virt_to_phys(volatile const void *address) #ifdef CONFIG_64BIT if (addr < CKSEG0) return XPHYSADDR(addr); - - return CPHYSADDR(addr); -#else - return addr - PAGE_OFFSET + PHYS_OFFSET; #endif + return CPHYSADDR(addr); } /* diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h deleted file mode 100644 index 7a7cfff..0000000 --- a/arch/mips/include/asm/jz4740.h +++ /dev/null @@ -1,1150 +0,0 @@ -/* - * head file for Ingenic Semiconductor's JZ4740 CPU. - */ -#ifndef __JZ4740_H__ -#define __JZ4740_H__ - -#include <asm/addrspace.h> -#include <asm/cacheops.h> - -/* Boot ROM Specification */ -/* NOR Boot config */ -#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */ -#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */ -#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */ -/* NAND Boot config */ -#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */ -#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */ -#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */ - -/* 1st-level interrupts */ -#define JZ4740_IRQ_I2C 1 -#define JZ4740_IRQ_UHC 3 -#define JZ4740_IRQ_UART0 9 -#define JZ4740_IRQ_SADC 12 -#define JZ4740_IRQ_MSC 14 -#define JZ4740_IRQ_RTC 15 -#define JZ4740_IRQ_SSI 16 -#define JZ4740_IRQ_CIM 17 -#define JZ4740_IRQ_AIC 18 -#define JZ4740_IRQ_ETH 19 -#define JZ4740_IRQ_DMAC 20 -#define JZ4740_IRQ_TCU2 21 -#define JZ4740_IRQ_TCU1 22 -#define JZ4740_IRQ_TCU0 23 -#define JZ4740_IRQ_UDC 24 -#define JZ4740_IRQ_GPIO3 25 -#define JZ4740_IRQ_GPIO2 26 -#define JZ4740_IRQ_GPIO1 27 -#define JZ4740_IRQ_GPIO0 28 -#define JZ4740_IRQ_IPU 29 -#define JZ4740_IRQ_LCD 30 -/* 2nd-level interrupts */ -#define JZ4740_IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */ -#define JZ4740_IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */ - -/* Register Definitions */ -#define JZ4740_CPM_BASE 0x10000000 -#define JZ4740_INTC_BASE 0x10001000 -#define JZ4740_TCU_BASE 0x10002000 -#define JZ4740_WDT_BASE 0x10002000 -#define JZ4740_RTC_BASE 0x10003000 -#define JZ4740_GPIO_BASE 0x10010000 -#define JZ4740_AIC_BASE 0x10020000 -#define JZ4740_ICDC_BASE 0x10020000 -#define JZ4740_MSC_BASE 0x10021000 -#define JZ4740_UART0_BASE 0x10030000 -#define JZ4740_I2C_BASE 0x10042000 -#define JZ4740_SSI_BASE 0x10043000 -#define JZ4740_SADC_BASE 0x10070000 -#define JZ4740_EMC_BASE 0x13010000 -#define JZ4740_DMAC_BASE 0x13020000 -#define JZ4740_UHC_BASE 0x13030000 -#define JZ4740_UDC_BASE 0x13040000 -#define JZ4740_LCD_BASE 0x13050000 -#define JZ4740_SLCD_BASE 0x13050000 -#define JZ4740_CIM_BASE 0x13060000 -#define JZ4740_ETH_BASE 0x13100000 - -/* 8bit Mode Register of SDRAM bank 0 */ -#define JZ4740_EMC_SDMR0 (JZ4740_EMC_BASE + 0xa000) - -/* GPIO (General-Purpose I/O Ports) */ -/* = 0,1,2,3 */ -#define GPIO_PXPIN(n) \ - (JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ -#define GPIO_PXDAT(n) \ - (JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ -#define GPIO_PXDATS(n) \ - (JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ -#define GPIO_PXDATC(n) \ - (JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ -#define GPIO_PXIM(n) \ - (JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ -#define GPIO_PXIMS(n) \ - (JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ -#define GPIO_PXIMC(n) \ - (JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ -#define GPIO_PXPE(n) \ - (JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ -#define GPIO_PXPES(n) \ - (JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ -#define GPIO_PXPEC(n) \ - (JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ -#define GPIO_PXFUN(n) \ - (JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ -#define GPIO_PXFUNS(n) \ - (JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ -#define GPIO_PXFUNC(n) \ - (JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ -#define GPIO_PXSEL(n) \ - (JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ -#define GPIO_PXSELS(n) \ - (JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ -#define GPIO_PXSELC(n) \ - (JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ -#define GPIO_PXDIR(n) \ - (JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ -#define GPIO_PXDIRS(n) \ - (JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ -#define GPIO_PXDIRC(n) \ - (JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ -#define GPIO_PXTRG(n) \ - (JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */ -#define GPIO_PXTRGS(n) \ - (JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */ -#define GPIO_PXTRGC(n) \ - (JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */ - -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) - -/* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ -#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ -#define EMC_NFECR_HAMMING (0 << 2) /* Use HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ - -/* NAND Flash ECC Data Register */ -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -/* NAND Flash Interrupt Status Register */ -#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ -#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ - -/* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ - -/* NAND Flash RS Error Report Register */ -#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ -#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) -#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ -#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) - -/* DRAM Control Register */ -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - -/* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -/* SDRAM Bank Address Configuration Register */ -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -/* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ -#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 /* Burst Type */ -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ - #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ -#define EMC_SDMR_BL_BIT 0 /* Burst Length */ -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - -/* RTC Control Register */ -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */ -#define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF (1 << 4) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ - -/* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ -#define RTC_RGR_ADJC_BIT 16 -#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) -#define RTC_RGR_NC1HZ_BIT 0 -#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) - -/* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ - -/* Hibernate Wakeup Filter Counter Register */ -#define RTC_HWFCR_BIT 5 -#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) - -/* Hibernate Reset Counter Register */ -#define RTC_HRCR_BIT 5 -#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) - -/* Hibernate Wakeup Control Register */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ - -/* Hibernate Wakeup Status Register */ -#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ -#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ - -/* Clock Control Register */ -#define CPM_CPCCR_I2CS (1 << 31) -#define CPM_CPCCR_CLKOEN (1 << 30) -#define CPM_CPCCR_UCS (1 << 29) -#define CPM_CPCCR_UDIV_BIT 23 -#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) -#define CPM_CPCCR_CE (1 << 22) -#define CPM_CPCCR_PCS (1 << 21) -#define CPM_CPCCR_LDIV_BIT 16 -#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) -#define CPM_CPCCR_MDIV_BIT 12 -#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) -#define CPM_CPCCR_PDIV_BIT 8 -#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) -#define CPM_CPCCR_HDIV_BIT 4 -#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) -#define CPM_CPCCR_CDIV_BIT 0 -#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) - -/* I2S Clock Divider Register */ -#define CPM_I2SCDR_I2SDIV_BIT 0 -#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) - -/* LCD Pixel Clock Divider Register */ -#define CPM_LPCDR_PIXDIV_BIT 0 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) - -/* MSC Clock Divider Register */ -#define CPM_MSCCDR_MSCDIV_BIT 0 -#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) - -/* PLL Control Register */ -#define CPM_CPPCR_PLLM_BIT 23 -#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) -#define CPM_CPPCR_PLLN_BIT 18 -#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) -#define CPM_CPPCR_PLLOD_BIT 16 -#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) -#define CPM_CPPCR_PLLS (1 << 10) -#define CPM_CPPCR_PLLBP (1 << 9) -#define CPM_CPPCR_PLLEN (1 << 8) -#define CPM_CPPCR_PLLST_BIT 0 -#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) - -/* Low Power Control Register */ -#define CPM_LCR_DOZE_DUTY_BIT 3 -#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) -#define CPM_LCR_DOZE_ON (1 << 2) -#define CPM_LCR_LPM_BIT 0 -#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) - #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) - -/* Clock Gate Register */ -#define CPM_CLKGR_UART1 (1 << 15) -#define CPM_CLKGR_UHC (1 << 14) -#define CPM_CLKGR_IPU (1 << 13) -#define CPM_CLKGR_DMAC (1 << 12) -#define CPM_CLKGR_UDC (1 << 11) -#define CPM_CLKGR_LCD (1 << 10) -#define CPM_CLKGR_CIM (1 << 9) -#define CPM_CLKGR_SADC (1 << 8) -#define CPM_CLKGR_MSC (1 << 7) -#define CPM_CLKGR_AIC1 (1 << 6) -#define CPM_CLKGR_AIC2 (1 << 5) -#define CPM_CLKGR_SSI (1 << 4) -#define CPM_CLKGR_I2C (1 << 3) -#define CPM_CLKGR_RTC (1 << 2) -#define CPM_CLKGR_TCU (1 << 1) -#define CPM_CLKGR_UART0 (1 << 0) - -/* Sleep Control Register */ -#define CPM_SCR_O1ST_BIT 8 -#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) -#define CPM_SCR_UDCPHY_ENABLE (1 << 6) -#define CPM_SCR_USBPHY_DISABLE (1 << 7) -#define CPM_SCR_OSC_ENABLE (1 << 4) - -/* Hibernate Control Register */ -#define CPM_HCR_PD (1 << 0) - -/* Wakeup Filter Counter Register in Hibernate Mode */ -#define CPM_HWFCR_TIME_BIT 0 -#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) - -/* Reset Counter Register in Hibernate Mode */ -#define CPM_HRCR_TIME_BIT 0 -#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) - -/* Wakeup Control Register in Hibernate Mode */ -#define CPM_HWCR_WLE_LOW (0 << 2) -#define CPM_HWCR_WLE_HIGH (1 << 2) -#define CPM_HWCR_PIN_WAKEUP (1 << 1) -#define CPM_HWCR_RTC_WAKEUP (1 << 0) - -/* Wakeup Status Register in Hibernate Mode */ -#define CPM_HWSR_WSR_PIN (1 << 1) -#define CPM_HWSR_WSR_RTC (1 << 0) - -/* Reset Status Register */ -#define CPM_RSR_HR (1 << 2) -#define CPM_RSR_WR (1 << 1) -#define CPM_RSR_PR (1 << 0) - -/* Register definitions */ -#define TCU_TCSR_PWM_SD (1 << 9) -#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) -#define TCU_TCSR_PWM_EN (1 << 7) -#define TCU_TCSR_PRESCALE_BIT 3 -#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) -#define TCU_TCSR_EXT_EN (1 << 2) -#define TCU_TCSR_RTC_EN (1 << 1) -#define TCU_TCSR_PCK_EN (1 << 0) - -#define TCU_TER_TCEN5 (1 << 5) -#define TCU_TER_TCEN4 (1 << 4) -#define TCU_TER_TCEN3 (1 << 3) -#define TCU_TER_TCEN2 (1 << 2) -#define TCU_TER_TCEN1 (1 << 1) -#define TCU_TER_TCEN0 (1 << 0) - -#define TCU_TESR_TCST5 (1 << 5) -#define TCU_TESR_TCST4 (1 << 4) -#define TCU_TESR_TCST3 (1 << 3) -#define TCU_TESR_TCST2 (1 << 2) -#define TCU_TESR_TCST1 (1 << 1) -#define TCU_TESR_TCST0 (1 << 0) - -#define TCU_TECR_TCCL5 (1 << 5) -#define TCU_TECR_TCCL4 (1 << 4) -#define TCU_TECR_TCCL3 (1 << 3) -#define TCU_TECR_TCCL2 (1 << 2) -#define TCU_TECR_TCCL1 (1 << 1) -#define TCU_TECR_TCCL0 (1 << 0) - -#define TCU_TFR_HFLAG5 (1 << 21) -#define TCU_TFR_HFLAG4 (1 << 20) -#define TCU_TFR_HFLAG3 (1 << 19) -#define TCU_TFR_HFLAG2 (1 << 18) -#define TCU_TFR_HFLAG1 (1 << 17) -#define TCU_TFR_HFLAG0 (1 << 16) -#define TCU_TFR_FFLAG5 (1 << 5) -#define TCU_TFR_FFLAG4 (1 << 4) -#define TCU_TFR_FFLAG3 (1 << 3) -#define TCU_TFR_FFLAG2 (1 << 2) -#define TCU_TFR_FFLAG1 (1 << 1) -#define TCU_TFR_FFLAG0 (1 << 0) - -#define TCU_TFSR_HFLAG5 (1 << 21) -#define TCU_TFSR_HFLAG4 (1 << 20) -#define TCU_TFSR_HFLAG3 (1 << 19) -#define TCU_TFSR_HFLAG2 (1 << 18) -#define TCU_TFSR_HFLAG1 (1 << 17) -#define TCU_TFSR_HFLAG0 (1 << 16) -#define TCU_TFSR_FFLAG5 (1 << 5) -#define TCU_TFSR_FFLAG4 (1 << 4) -#define TCU_TFSR_FFLAG3 (1 << 3) -#define TCU_TFSR_FFLAG2 (1 << 2) -#define TCU_TFSR_FFLAG1 (1 << 1) -#define TCU_TFSR_FFLAG0 (1 << 0) - -#define TCU_TFCR_HFLAG5 (1 << 21) -#define TCU_TFCR_HFLAG4 (1 << 20) -#define TCU_TFCR_HFLAG3 (1 << 19) -#define TCU_TFCR_HFLAG2 (1 << 18) -#define TCU_TFCR_HFLAG1 (1 << 17) -#define TCU_TFCR_HFLAG0 (1 << 16) -#define TCU_TFCR_FFLAG5 (1 << 5) -#define TCU_TFCR_FFLAG4 (1 << 4) -#define TCU_TFCR_FFLAG3 (1 << 3) -#define TCU_TFCR_FFLAG2 (1 << 2) -#define TCU_TFCR_FFLAG1 (1 << 1) -#define TCU_TFCR_FFLAG0 (1 << 0) - -#define TCU_TMR_HMASK5 (1 << 21) -#define TCU_TMR_HMASK4 (1 << 20) -#define TCU_TMR_HMASK3 (1 << 19) -#define TCU_TMR_HMASK2 (1 << 18) -#define TCU_TMR_HMASK1 (1 << 17) -#define TCU_TMR_HMASK0 (1 << 16) -#define TCU_TMR_FMASK5 (1 << 5) -#define TCU_TMR_FMASK4 (1 << 4) -#define TCU_TMR_FMASK3 (1 << 3) -#define TCU_TMR_FMASK2 (1 << 2) -#define TCU_TMR_FMASK1 (1 << 1) -#define TCU_TMR_FMASK0 (1 << 0) - -#define TCU_TMSR_HMST5 (1 << 21) -#define TCU_TMSR_HMST4 (1 << 20) -#define TCU_TMSR_HMST3 (1 << 19) -#define TCU_TMSR_HMST2 (1 << 18) -#define TCU_TMSR_HMST1 (1 << 17) -#define TCU_TMSR_HMST0 (1 << 16) -#define TCU_TMSR_FMST5 (1 << 5) -#define TCU_TMSR_FMST4 (1 << 4) -#define TCU_TMSR_FMST3 (1 << 3) -#define TCU_TMSR_FMST2 (1 << 2) -#define TCU_TMSR_FMST1 (1 << 1) -#define TCU_TMSR_FMST0 (1 << 0) - -#define TCU_TMCR_HMCL5 (1 << 21) -#define TCU_TMCR_HMCL4 (1 << 20) -#define TCU_TMCR_HMCL3 (1 << 19) -#define TCU_TMCR_HMCL2 (1 << 18) -#define TCU_TMCR_HMCL1 (1 << 17) -#define TCU_TMCR_HMCL0 (1 << 16) -#define TCU_TMCR_FMCL5 (1 << 5) -#define TCU_TMCR_FMCL4 (1 << 4) -#define TCU_TMCR_FMCL3 (1 << 3) -#define TCU_TMCR_FMCL2 (1 << 2) -#define TCU_TMCR_FMCL1 (1 << 1) -#define TCU_TMCR_FMCL0 (1 << 0) - -#define TCU_TSR_WDTS (1 << 16) -#define TCU_TSR_STOP5 (1 << 5) -#define TCU_TSR_STOP4 (1 << 4) -#define TCU_TSR_STOP3 (1 << 3) -#define TCU_TSR_STOP2 (1 << 2) -#define TCU_TSR_STOP1 (1 << 1) -#define TCU_TSR_STOP0 (1 << 0) - -#define TCU_TSSR_WDTSS (1 << 16) -#define TCU_TSSR_STPS5 (1 << 5) -#define TCU_TSSR_STPS4 (1 << 4) -#define TCU_TSSR_STPS3 (1 << 3) -#define TCU_TSSR_STPS2 (1 << 2) -#define TCU_TSSR_STPS1 (1 << 1) -#define TCU_TSSR_STPS0 (1 << 0) - -#define TCU_TSSR_WDTSC (1 << 16) -#define TCU_TSSR_STPC5 (1 << 5) -#define TCU_TSSR_STPC4 (1 << 4) -#define TCU_TSSR_STPC3 (1 << 3) -#define TCU_TSSR_STPC2 (1 << 2) -#define TCU_TSSR_STPC1 (1 << 1) -#define TCU_TSSR_STPC0 (1 << 0) - -/* Register definition */ -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) -#define WDT_TCER_TCEN (1 << 0) - -/* - * Define macros for UART_IER - * UART Interrupt Enable Register - */ -#define UART_IER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ -#define UART_IER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ -#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UART_ISR - * UART Interrupt Status Register - */ -#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UART_ISR_IID (7 << 1) /* Source of Interrupt */ -#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -/* FIFO mode select, set when UART_FCR.FE is set to 1 */ -#define UART_ISR_FFMS (3 << 6) -#define UART_ISR_FFMS_NO_FIFO (0 << 6) -#define UART_ISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UART_FCR - * UART FIFO Control Register - */ -#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UART_FCR_UUE (1 << 4) /* 0: disable UART */ -#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UART_FCR_RTRG_1 (0 << 6) -#define UART_FCR_RTRG_4 (1 << 6) -#define UART_FCR_RTRG_8 (2 << 6) -#define UART_FCR_RTRG_15 (3 << 6) - -/* - * Define macros for UART_LCR - * UART Line Control Register - */ -#define UART_LCR_WLEN (3 << 0) /* word length */ -#define UART_LCR_WLEN_5 (0 << 0) -#define UART_LCR_WLEN_6 (1 << 0) -#define UART_LCR_WLEN_7 (2 << 0) -#define UART_LCR_WLEN_8 (3 << 0) -#define UART_LCR_STOP (1 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_1 (0 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UART_LCR_STOP_2 (1 << 2) - /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ - -#define UART_LCR_PE (1 << 3) /* 0: parity disable */ -#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ -#define UART_LCR_DLAB (1 << 7) - -/* - * Define macros for UART_LSR - * UART Line Status Register - */ -/* 0: receive FIFO is empty 1: receive data is ready */ -#define UART_LSR_DR (1 << 0) -/* 0: no overrun error */ -#define UART_LSR_ORER (1 << 1) -/* 0: no parity error */ -#define UART_LSR_PER (1 << 2) -/* 0; no framing error */ -#define UART_LSR_FER (1 << 3) -/* 0: no break detected 1: receive a break signal */ -#define UART_LSR_BRK (1 << 4) -/* 1: transmit FIFO half "empty" */ -#define UART_LSR_TDRQ (1 << 5) -/* 1: transmit FIFO and shift registers empty */ -#define UART_LSR_TEMT (1 << 6) -/* 0: no receive error 1: receive error in FIFO mode */ -#define UART_LSR_RFER (1 << 7) - -/* - * Define macros for UART_MCR - * UART Modem Control Register - */ -#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */ -#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */ -/* 0: UART_MSR.RI is set to 0 and RI_ input high */ -#define UART_MCR_OUT1 (1 << 2) -/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ -#define UART_MCR_OUT2 (1 << 3) -#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UART_MSR - * UART Modem Status Register - */ -#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ since last read */ -#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ since last read */ -#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ since last read */ -#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ since last read */ -#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */ -#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */ -#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */ -#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - -/* MSC Clock and Control Register (MSC_STRPCL) */ -#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) -#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) -#define MSC_STRPCL_START_READWAIT (1 << 5) -#define MSC_STRPCL_STOP_READWAIT (1 << 4) -#define MSC_STRPCL_RESET (1 << 3) -#define MSC_STRPCL_START_OP (1 << 2) -#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 -#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) -#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) -#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) - -/* MSC Status Register (MSC_STAT) */ -#define MSC_STAT_IS_RESETTING (1 << 15) -#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) -#define MSC_STAT_PRG_DONE (1 << 13) -#define MSC_STAT_DATA_TRAN_DONE (1 << 12) -#define MSC_STAT_END_CMD_RES (1 << 11) -#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) -#define MSC_STAT_IS_READWAIT (1 << 9) -#define MSC_STAT_CLK_EN (1 << 8) -#define MSC_STAT_DATA_FIFO_FULL (1 << 7) -#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) -#define MSC_STAT_CRC_RES_ERR (1 << 5) -#define MSC_STAT_CRC_READ_ERROR (1 << 4) -#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 -#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* No error on transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* Card observed erroneous transmission of data */ - #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) -/* No CRC status is sent back */ - #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) -#define MSC_STAT_TIME_OUT_RES (1 << 1) -#define MSC_STAT_TIME_OUT_READ (1 << 0) - -/* MSC Bus Clock Control Register (MSC_CLKRT) */ -#define MSC_CLKRT_CLK_RATE_BIT 0 -#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) - #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) - -/* MSC Command Sequence Control Register (MSC_CMDAT) */ -#define MSC_CMDAT_IO_ABORT (1 << 11) -#define MSC_CMDAT_BUS_WIDTH_BIT 9 -#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) -#define MSC_CMDAT_DMA_EN (1 << 8) -#define MSC_CMDAT_INIT (1 << 7) -#define MSC_CMDAT_BUSY (1 << 6) -#define MSC_CMDAT_STREAM_BLOCK (1 << 5) -#define MSC_CMDAT_WRITE (1 << 4) -#define MSC_CMDAT_READ (0 << 4) -#define MSC_CMDAT_DATA_EN (1 << 3) -#define MSC_CMDAT_RESPONSE_BIT 0 -#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) -#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) - -/* MSC Interrupts Mask Register (MSC_IMASK) */ -#define MSC_IMASK_SDIO (1 << 7) -#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) -#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) -#define MSC_IMASK_END_CMD_RES (1 << 2) -#define MSC_IMASK_PRG_DONE (1 << 1) -#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) - -#ifndef __ASSEMBLY__ -/* INTC (Interrupt Controller) */ -struct jz4740_intc { - uint32_t isr; /* interrupt source register */ - uint32_t imr; /* interrupt mask register */ - uint32_t imsr; /* interrupt mask set register */ - uint32_t imcr; /* interrupt mask clear register */ - uint32_t ipr; /* interrupt pending register */ -}; - -/* RTC */ -struct jz4740_rtc { - uint32_t rcr; /* rtc control register */ - uint32_t rsr; /* rtc second register */ - uint32_t rsar; /* rtc second alarm register */ - uint32_t rgr; /* rtc regulator register */ - uint32_t hcr; /* hibernate control register */ - uint32_t hwfcr; /* hibernate wakeup filter counter reg */ - uint32_t hrcr; /* hibernate reset counter reg */ - uint32_t hwcr; /* hibernate wakeup control register */ - uint32_t hwrsr; /* hibernate wakeup status reg */ - uint32_t hspr; /* scratch pattern register */ -}; - -/* CPM (Clock reset and Power control Management) */ -struct jz4740_cpm { - uint32_t cpccr; /* 0x00 clock control reg */ - uint32_t lcr; /* 0x04 low power control reg */ - uint32_t rsr; /* 0x08 reset status reg */ - uint32_t pad00; - uint32_t cppcr; /* 0x10 pll control reg */ - uint32_t pad01[3]; - uint32_t clkgr; /* 0x20 clock gate reg */ - uint32_t scr; /* 0x24 sleep control reg */ - uint32_t pad02[14]; - uint32_t i2scd; /* 0x60 I2S device clock divider reg */ - uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */ - uint32_t msccdr; /* 0x68 MSC device clock divider reg */ - uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */ - uint32_t uhcts; /* 0x70 UHC PHY test point reg */ - uint32_t ssicd; /* 0x74 SSI clock divider reg */ -}; - -/* TCU (Timer Counter Unit) */ -struct jz4740_tcu { - uint32_t pad00[4]; - uint32_t ter; /* 0x10 Timer Counter Enable Register */ - uint32_t tesr; /* 0x14 Timer Counter Enable Set Register */ - uint32_t tecr; /* 0x18 Timer Counter Enable Clear Register */ - uint32_t tsr; /* 0x1C Timer Stop Register */ - uint32_t tfr; /* 0x20 Timer Flag Register */ - uint32_t tfsr; /* 0x24 Timer Flag Set Register */ - uint32_t tfcr; /* 0x28 Timer Flag Clear Register */ - uint32_t tssr; /* 0x2C Timer Stop Set Register */ - uint32_t tmr; /* 0x30 Timer Mask Register */ - uint32_t tmsr; /* 0x34 Timer Mask Set Register */ - uint32_t tmcr; /* 0x38 Timer Mask Clear Register */ - uint32_t tscr; /* 0x3C Timer Stop Clear Register */ - uint32_t tdfr0; /* 0x40 Timer Data Full Register */ - uint32_t tdhr0; /* 0x44 Timer Data Half Register */ - uint32_t tcnt0; /* 0x48 Timer Counter Register */ - uint32_t tcsr0; /* 0x4C Timer Control Register */ - uint32_t tdfr1; /* 0x50 */ - uint32_t tdhr1; /* 0x54 */ - uint32_t tcnt1; /* 0x58 */ - uint32_t tcsr1; /* 0x5C */ - uint32_t tdfr2; /* 0x60 */ - uint32_t tdhr2; /* 0x64 */ - uint32_t tcnt2; /* 0x68 */ - uint32_t tcsr2; /* 0x6C */ - uint32_t tdfr3; /* 0x70 */ - uint32_t tdhr3; /* 0x74 */ - uint32_t tcnt3; /* 0x78 */ - uint32_t tcsr3; /* 0x7C */ - uint32_t tdfr4; /* 0x80 */ - uint32_t tdhr4; /* 0x84 */ - uint32_t tcnt4; /* 0x88 */ - uint32_t tcsr4; /* 0x8C */ - uint32_t tdfr5; /* 0x90 */ - uint32_t tdhr5; /* 0x94 */ - uint32_t tcnt5; /* 0x98 */ - uint32_t tcsr5; /* 0x9C */ -}; - -/* WDT (WatchDog Timer) */ -struct jz4740_wdt { - uint16_t tdr; /* 0x00 watchdog timer data reg*/ - uint16_t pad00; - uint8_t tcer; /* 0x04 watchdog counter enable reg*/ - uint8_t pad01[3]; - uint16_t tcnt; /* 0x08 watchdog timer counter*/ - uint16_t pad02; - uint16_t tcsr; /* 0x0C watchdog timer control reg*/ - uint16_t pad03; -}; - -struct jz4740_uart { - uint8_t rbr_thr_dllr; - /* 0x00 R 8b receive buffer reg */ - /* 0x00 W 8b transmit hold reg */ - /* 0x00 RW 8b divisor latch low reg */ - uint8_t pad00[3]; - uint8_t dlhr_ier; - /* 0x04 RW 8b divisor latch high reg */ - /* 0x04 RW 8b interrupt enable reg */ - uint8_t pad01[3]; - uint8_t iir_fcr; - /* 0x08 R 8b interrupt identification reg */ - /* 0x08 W 8b FIFO control reg */ - uint8_t pad02[3]; - uint8_t lcr; /* 0x0C RW 8b Line control reg */ - uint8_t pad03[3]; - uint8_t mcr; /* 0x10 RW 8b modem control reg */ - uint8_t pad04[3]; - uint8_t lsr; /* 0x14 R 8b line status reg */ - uint8_t pad05[3]; - uint8_t msr; /* 0x18 R 8b modem status reg */ - uint8_t pad06[3]; - uint8_t spr; /* 0x1C RW 8b scratch pad reg */ - uint8_t pad07[3]; - uint8_t isr; /* 0x20 RW 8b infrared selection reg */ - uint8_t pad08[3]; - uint8_t umr; /* 0x24 RW 8b */ -}; - -/* MSC */ -struct jz4740_msc { - uint16_t strpcl;/* 0x00 */ - uint32_t stat; /* 0x04 */ - uint16_t clkrt; /* 0x08 */ - uint32_t cmdat; /* 0x0C */ - uint16_t resto; /* 0x10 */ - uint16_t rdto; /* 0x14 */ - uint16_t blklen;/* 0x18 */ - uint16_t nob; /* 0x1C */ - uint16_t snob; /* 0x20 */ - uint16_t imask; /* 0x24 */ - uint16_t ireg; /* 0x28 */ - uint8_t cmd; /* 0x2C */ - uint32_t arg; /* 0x30 */ - uint16_t res; /* 0x34 */ - uint32_t rxfifo;/* 0x38 */ - uint32_t txfifo;/* 0x3C */ -}; - -/* External Memory Controller */ -struct jz4740_emc { - uint32_t bcr; /* 0x00 BCR */ - uint32_t pad00[3]; - uint32_t smcr[5]; - /* x10 Static Memory Control Register 0 */ - /* x14 Static Memory Control Register 1 */ - /* x18 Static Memory Control Register 2 */ - /* x1c Static Memory Control Register 3 */ - /* x20 Static Memory Control Register 4 */ - uint32_t pad01[3]; - uint32_t sacr[5]; - /* x30 Static Memory Bank 0 Addr Config Reg */ - /* x34 Static Memory Bank 1 Addr Config Reg */ - /* x38 Static Memory Bank 2 Addr Config Reg */ - /* x3c Static Memory Bank 3 Addr Config Reg */ - /* x40 Static Memory Bank 4 Addr Config Reg */ - uint32_t pad02[3]; - uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */ - - uint32_t pad03[11]; - uint32_t dmcr; /* x80 DRAM Control Register */ - uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */ - uint16_t pad04; - uint16_t rtcnt; /* x88 Refresh Timer Counter */ - uint16_t pad05; - uint16_t rtcor; /* x8c Refresh Time Constant Register */ - uint16_t pad06; - uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */ - uint32_t pad07[27]; - uint32_t nfecr; /* x100 NAND Flash ECC Control Register */ - uint32_t nfecc; /* x104 NAND Flash ECC Data Register */ - uint8_t nfpar[12]; - /* x108 NAND Flash RS Parity 0 Register */ - /* x10c NAND Flash RS Parity 1 Register */ - /* x110 NAND Flash RS Parity 2 Register */ - uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */ - uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */ - uint32_t nferr[4]; - /* x11c NAND Flash RS Error Report 0 Register */ - /* x120 NAND Flash RS Error Report 1 Register */ - /* x124 NAND Flash RS Error Report 2 Register */ - /* x128 NAND Flash RS Error Report 3 Register */ -}; - -#define __gpio_as_nand() \ -do { \ - writel(0x02018000, GPIO_PXFUNS(1)); \ - writel(0x02018000, GPIO_PXSELC(1)); \ - writel(0x02018000, GPIO_PXPES(1)); \ - writel(0x30000000, GPIO_PXFUNS(2)); \ - writel(0x30000000, GPIO_PXSELC(2)); \ - writel(0x30000000, GPIO_PXPES(2)); \ - writel(0x40000000, GPIO_PXFUNC(2)); \ - writel(0x40000000, GPIO_PXSELC(2)); \ - writel(0x40000000, GPIO_PXDIRC(2)); \ - writel(0x40000000, GPIO_PXPES(2)); \ - writel(0x00400000, GPIO_PXFUNS(1)); \ - writel(0x00400000, GPIO_PXSELC(1)); \ -} while (0) - -#define __gpio_as_sdram_16bit_4720() \ -do { \ - writel(0x5442bfaa, GPIO_PXFUNS(0)); \ - writel(0x5442bfaa, GPIO_PXSELC(0)); \ - writel(0x5442bfaa, GPIO_PXPES(0)); \ - writel(0x81f9ffff, GPIO_PXFUNS(1)); \ - writel(0x81f9ffff, GPIO_PXSELC(1)); \ - writel(0x81f9ffff, GPIO_PXPES(1)); \ - writel(0x01000000, GPIO_PXFUNS(2)); \ - writel(0x01000000, GPIO_PXSELC(2)); \ - writel(0x01000000, GPIO_PXPES(2)); \ -} while (0) - -#define __gpio_as_lcd_18bit() \ -do { \ - writel(0x003fffff, GPIO_PXFUNS(2)); \ - writel(0x003fffff, GPIO_PXSELC(2)); \ - writel(0x003fffff, GPIO_PXPES(2)); \ -} while (0) - -/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */ -#define __gpio_as_msc() \ -do { \ - writel(0x00003f00, GPIO_PXFUNS(3)); \ - writel(0x00003f00, GPIO_PXSELC(3)); \ - writel(0x00003f00, GPIO_PXPES(3)); \ -} while (0) - -#define __gpio_get_port(p) (readl(GPIO_PXPIN(p))) - -#define __gpio_disable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXPES(p)); \ -} while (0) - -#define __gpio_enable_pull(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel(1 << (o), GPIO_PXPEC(p)); \ -} while (0) - -#define __gpio_port_as_output(p, o) \ -do { \ - writel(1 << (o), GPIO_PXFUNC(p)); \ - writel(1 << (o), GPIO_PXSELC(p)); \ - writel(1 << (o), GPIO_PXDIRS(p)); \ -} while (0) - -#define __gpio_port_as_input(p, o) \ -do { \ - writel(1 << (o), GPIO_PXFUNC(p)); \ - writel(1 << (o), GPIO_PXSELC(p)); \ - writel(1 << (o), GPIO_PXDIRC(p)); \ -} while (0) - -#define __gpio_as_output(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_output(p, o); \ -} while (0) - -#define __gpio_as_input(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - __gpio_port_as_input(p, o); \ -} while (0) - -#define __gpio_set_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXDATS(p)); \ -} while (0) - -#define __gpio_clear_pin(n) \ -do { \ - unsigned int p, o; \ - p = (n) / 32; \ - o = (n) % 32; \ - writel((1 << o), GPIO_PXDATC(p)); \ -} while (0) - -#define __gpio_get_pin(n) \ -({ \ - unsigned int p, o, v; \ - p = (n) / 32; \ - o = (n) % 32; \ - if (__gpio_get_port(p) & (1 << o)) \ - v = 1; \ - else \ - v = 0; \ - v; \ -}) - -#define __gpio_as_uart0() \ -do { \ - writel(0x06000000, GPIO_PXFUNS(3)); \ - writel(0x06000000, GPIO_PXSELS(3)); \ - writel(0x06000000, GPIO_PXPES(3)); \ -} while (0) - -#define __gpio_jtag_to_uart0() \ -do { \ - writel(0x80000000, GPIO_PXSELS(2)); \ -} while (0) - -/* Clock Control Register */ -#define __cpm_get_pllm() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK) \ - >> CPM_CPPCR_PLLM_BIT) -#define __cpm_get_plln() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK) \ - >> CPM_CPPCR_PLLN_BIT) -#define __cpm_get_pllod() \ - ((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK) \ - >> CPM_CPPCR_PLLOD_BIT) -#define __cpm_get_hdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK) \ - >> CPM_CPCCR_HDIV_BIT) -#define __cpm_get_pdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK) \ - >> CPM_CPCCR_PDIV_BIT) -#define __cpm_get_cdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK) \ - >> CPM_CPCCR_CDIV_BIT) -#define __cpm_get_mdiv() \ - ((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK) \ - >> CPM_CPCCR_MDIV_BIT) - -static inline unsigned int __cpm_get_pllout(void) -{ - uint32_t m, n, no, pllout; - uint32_t od[4] = {1, 2, 2, 4}; - - struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - uint32_t cppcr = readl(&cpm->cppcr); - - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) { - m = __cpm_get_pllm() + 2; - n = __cpm_get_plln() + 2; - no = od[__cpm_get_pllod()]; - pllout = (CONFIG_SYS_EXTAL / (n * no)) * m; - } else - pllout = CONFIG_SYS_EXTAL; - - return pllout; -} - -extern void pll_init(void); -extern void sdram_init(void); -extern void calc_clocks(void); -extern void rtc_init(void); - -#endif /* !__ASSEMBLY__ */ -#endif /* __JZ4740_H__ */ diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index a5b2fc0..1f527bb 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -1,23 +1,8 @@ /* * SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de */ -static inline unsigned long bss_start(void) -{ - extern char __bss_start[]; - return (unsigned long) &__bss_start; -} +#ifndef _U_BOOT_MIPS_H_ +#define _U_BOOT_MIPS_H_ -static inline unsigned long bss_end(void) -{ - extern ulong __bss_end; - return (unsigned long) &__bss_end; -} - -static inline unsigned long image_copy_end(void) -{ - extern char __image_copy_end[]; - return (unsigned long) &__image_copy_end; -} +#endif /* _U_BOOT_MIPS_H_ */ diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 4909a2a..af03e8d 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -15,25 +15,9 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 -#ifdef CONFIG_SYS_GENERIC_BOARD - /* Use the generic board which requires a unified bd_info */ #include <asm-generic/u-boot.h> -#else /* !CONFIG_SYS_GENERIC_BOARD */ - -typedef struct bd_info { - unsigned long bi_arch_number; /* unique id for this board */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ -} bd_t; - -#endif /* !CONFIG_SYS_GENERIC_BOARD */ - /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_MIPS diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 7482005..5f520c0 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -9,23 +9,13 @@ #include <asm/cacheops.h> #include <asm/mipsregs.h> -#ifdef CONFIG_SYS_CACHELINE_SIZE - static inline unsigned long icache_line_size(void) { - return CONFIG_SYS_CACHELINE_SIZE; -} - -static inline unsigned long dcache_line_size(void) -{ - return CONFIG_SYS_CACHELINE_SIZE; -} + unsigned long conf1, il; -#else /* !CONFIG_SYS_CACHELINE_SIZE */ + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_ICACHE_LINE_SIZE; -static inline unsigned long icache_line_size(void) -{ - unsigned long conf1, il; conf1 = read_c0_config1(); il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; if (!il) @@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void) static inline unsigned long dcache_line_size(void) { unsigned long conf1, dl; + + if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) + return CONFIG_SYS_DCACHE_LINE_SIZE; + conf1 = read_c0_config1(); dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; if (!dl) @@ -43,84 +37,59 @@ static inline unsigned long dcache_line_size(void) return 2 << dl; } -#endif /* !CONFIG_SYS_CACHELINE_SIZE */ +#define cache_loop(start, end, lsize, ops...) do { \ + const void *addr = (const void *)(start & ~(lsize - 1)); \ + const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \ + const unsigned int cache_ops[] = { ops }; \ + unsigned int i; \ + \ + for (; addr <= aend; addr += lsize) { \ + for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \ + mips_cache(cache_ops[i], addr); \ + } \ +} while (0) void flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); unsigned long dlsize = dcache_line_size(); - const void *addr, *aend; /* aend will be miscalculated when size is zero, so we return here */ if (size == 0) return; - addr = (const void *)(start_addr & ~(dlsize - 1)); - aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1)); - if (ilsize == dlsize) { /* flush I-cache & D-cache simultaneously */ - while (1) { - mips_cache(HIT_WRITEBACK_INV_D, addr); - mips_cache(HIT_INVALIDATE_I, addr); - if (addr == aend) - break; - addr += dlsize; - } + cache_loop(start_addr, start_addr + size, ilsize, + HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); return; } /* flush D-cache */ - while (1) { - mips_cache(HIT_WRITEBACK_INV_D, addr); - if (addr == aend) - break; - addr += dlsize; - } + cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); /* flush I-cache */ - addr = (const void *)(start_addr & ~(ilsize - 1)); - aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1)); - while (1) { - mips_cache(HIT_INVALIDATE_I, addr); - if (addr == aend) - break; - addr += ilsize; - } + cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); } void flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); - const void *addr = (const void *)(start_addr & ~(lsize - 1)); - const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; - while (1) { - mips_cache(HIT_WRITEBACK_INV_D, addr); - if (addr == aend) - break; - addr += lsize; - } + cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); } void invalidate_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); - const void *addr = (const void *)(start_addr & ~(lsize - 1)); - const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; - while (1) { - mips_cache(HIT_INVALIDATE_D, addr); - if (addr == aend) - break; - addr += lsize; - } + cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I); } diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 08b7c3a..bc8ab27 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -99,16 +99,16 @@ * */ LEAF(mips_cache_reset) -#ifdef CONFIG_SYS_ICACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t2, CONFIG_SYS_ICACHE_SIZE - li t8, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_ICACHE_LINE_SIZE #else l1_info t2, t8, MIPS_CONF1_IA_SHF #endif -#ifdef CONFIG_SYS_DCACHE_SIZE +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO li t3, CONFIG_SYS_DCACHE_SIZE - li t9, CONFIG_SYS_CACHELINE_SIZE + li t9, CONFIG_SYS_DCACHE_LINE_SIZE #else l1_info t3, t9, MIPS_CONF1_DA_SHF #endif @@ -116,7 +116,7 @@ LEAF(mips_cache_reset) #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Determine the largest L1 cache size */ -#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#ifndef CONFIG_SYS_CACHE_SIZE_AUTO #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE li v0, CONFIG_SYS_ICACHE_SIZE #else diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c index 9fcd496..6d98efc 100644 --- a/arch/mips/mach-ath79/ar933x/clk.c +++ b/arch/mips/mach-ath79/ar933x/clk.c @@ -9,7 +9,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -17,7 +17,7 @@ static u32 ar933x_get_xtal(void) { u32 val; - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & AR933X_BOOTSTRAP_REF_CLK_40) return 40000000; else diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 91452bc..2a25e23 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -10,7 +10,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +114,7 @@ void ddr_init(void) writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & AR933X_BOOTSTRAP_DDR2) { /* AHB maximum timeout */ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX); @@ -268,6 +268,8 @@ void ddr_tap_tuning(void) dir = 1; tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); val = tap; + upper = tap; + lower = tap; while (!done) { err = 0; diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c index 9c65184..9b41d3d 100644 --- a/arch/mips/mach-ath79/ar934x/clk.c +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -9,7 +9,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> #include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; @@ -119,7 +119,7 @@ void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */ /* Test for 40MHz XTAL */ - reg = get_bootstrap(); + reg = ath79_get_bootstrap(); if (reg & AR934X_BOOTSTRAP_REF_CLK_40) { xtal_40 = 1; cpu_srif = 0x41c00000; @@ -214,7 +214,7 @@ static u32 ar934x_get_xtal(void) { u32 val; - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & AR934X_BOOTSTRAP_REF_CLK_40) return 40000000; else diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c index 4621d58..2ba1efa 100644 --- a/arch/mips/mach-ath79/ar934x/ddr.c +++ b/arch/mips/mach-ath79/ar934x/ddr.c @@ -11,7 +11,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,7 +45,7 @@ void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, MAP_NOCACHE); - reg = get_bootstrap(); + reg = ath79_get_bootstrap(); if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */ if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */ memtype = AR934X_DDR1; diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index a8e51cb..7b48524 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -331,6 +331,7 @@ #define AR933X_PLL_CPU_CONFIG_REG 0x00 #define AR933X_PLL_CLK_CTRL_REG 0x08 #define AR933X_PLL_DITHER_FRAC_REG 0x10 +#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f @@ -660,6 +661,7 @@ #define AR933X_RESET_GE1_MDIO BIT(23) #define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14) #define AR933X_RESET_GE1_MAC BIT(13) #define AR933X_RESET_WMAC BIT(11) #define AR933X_RESET_GE0_MAC BIT(9) diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 17af082..582c028 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); } +u32 ath79_get_bootstrap(void); int ath79_eth_reset(void); int ath79_usb_reset(void); diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h deleted file mode 100644 index c383bfe..0000000 --- a/arch/mips/mach-ath79/include/mach/reset.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_MACH_RESET_H -#define __ASM_MACH_RESET_H - -#include <linux/types.h> - -u32 get_bootstrap(void); - -#endif /* __ASM_MACH_RESET_H */ diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c index ef0a28e..533356c 100644 --- a/arch/mips/mach-ath79/qca953x/clk.c +++ b/arch/mips/mach-ath79/qca953x/clk.c @@ -9,7 +9,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -17,7 +17,7 @@ static u32 qca953x_get_xtal(void) { u32 val; - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & QCA953X_BOOTSTRAP_REF_CLK_40) return 40000000; else diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c index ac0130c..c6049d8 100644 --- a/arch/mips/mach-ath79/qca953x/ddr.c +++ b/arch/mips/mach-ath79/qca953x/ddr.c @@ -10,7 +10,7 @@ #include <asm/addrspace.h> #include <asm/types.h> #include <mach/ar71xx_regs.h> -#include <mach/reset.h> +#include <mach/ath79.h> DECLARE_GLOBAL_DATA_PTR; @@ -226,7 +226,7 @@ void ddr_init(void) regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, MAP_NOCACHE); - val = get_bootstrap(); + val = ath79_get_bootstrap(); if (val & QCA953X_BOOTSTRAP_DDR1) { writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); udelay(10); diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 188eccb..073a179 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -45,7 +45,7 @@ void _machine_restart(void) /* NOP */; } -u32 get_bootstrap(void) +u32 ath79_get_bootstrap(void) { void __iomem *base; u32 reg = 0; @@ -81,14 +81,15 @@ static int eth_init_ar933x(void) MAP_NOCACHE); const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO | - AR933X_RESET_ETH_SWITCH; + AR933X_RESET_ETH_SWITCH | + AR933X_RESET_ETH_SWITCH_ANALOG; /* Clear MDIO slave EN bit. */ clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17)); mdelay(10); /* Get Atheros S26 PHY out of reset. */ - clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG, + clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG, 0x1f, 0x10); mdelay(10); @@ -135,6 +136,23 @@ static int eth_init_ar934x(void) return 0; } +static int eth_init_qca953x(void) +{ + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO | + QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO | + QCA953X_RESET_ETH_SWITCH_ANALOG | + QCA953X_RESET_ETH_SWITCH; + + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + + return 0; +} + int ath79_eth_reset(void) { /* @@ -145,6 +163,8 @@ int ath79_eth_reset(void) return eth_init_ar933x(); if (soc_is_ar934x()) return eth_init_ar934x(); + if (soc_is_qca953x()) + return eth_init_qca953x(); return -EINVAL; } @@ -184,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs) return 0; } +static int usb_reset_qca953x(void __iomem *reset_regs) +{ + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG, + 0xf00, 0x200); + mdelay(10); + + /* Ungate the USB block */ + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, + QCA953X_RESET_USBSUS_OVERRIDE); + mdelay(1); + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, + QCA953X_RESET_USB_PHY); + mdelay(1); + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, + QCA953X_RESET_USB_PHY_ANALOG); + mdelay(1); + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, + QCA953X_RESET_USB_HOST); + mdelay(1); + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, + QCA953X_RESET_USB_PHY_PLL_PWD_EXT); + mdelay(1); + + return 0; +} + int ath79_usb_reset(void) { void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE, @@ -203,6 +252,8 @@ int ath79_usb_reset(void) return usb_reset_ar933x(reset_regs); if (soc_is_ar934x()) return usb_reset_ar934x(reset_regs); + if (soc_is_qca953x()) + return usb_reset_qca953x(reset_regs); return -EINVAL; } diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c index 79f72aa..a44f51a 100644 --- a/arch/nios2/cpu/fdt.c +++ b/arch/nios2/cpu/fdt.c @@ -12,7 +12,7 @@ #include <common.h> -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP #include <libfdt.h> #include <fdt_support.h> @@ -35,4 +35,4 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ fdt_fixup_ethernet(blob); } -#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index dfa72d9..3a2f6ec 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -5,6 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += timer.o diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c deleted file mode 100644 index b7fbd2f..0000000 --- a/arch/openrisc/lib/board.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2011 - * Julius Baxter, julius@opencores.org - * - * (C) Copyright 2003, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt@psyent.com> - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> -#include <stdio_dev.h> -#include <watchdog.h> -#include <malloc.h> -#include <mmc.h> -#include <net.h> -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#ifdef CONFIG_CMD_NAND -#include <nand.h> /* cannot even include nand.h if it isnt configured */ -#endif - -#include <timestamp.h> -#include <version.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - -extern int cache_init(void); - -/* - * Initialization sequence - */ -static int (* const init_sequence[])(void) = { - cache_init, - timer_init, /* initialize timer */ - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, -}; - - -/***********************************************************************/ -void board_init(void) -{ - bd_t *bd; - int i; - - gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR; - - memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#endif -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - WATCHDOG_RESET(); - if (init_sequence[i]()) - hang(); - } - - WATCHDOG_RESET(); - - /* The Malloc area is immediately below the monitor copy in RAM */ - mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - -#ifndef CONFIG_SYS_NO_FLASH - WATCHDOG_RESET(); - bd->bi_flashsize = flash_init(); -#endif - -#ifdef CONFIG_CMD_NAND - puts("NAND: "); - nand_init(); -#endif - -#ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(bd); -#endif - - WATCHDOG_RESET(); - env_relocate(); - - WATCHDOG_RESET(); - stdio_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET(); - interrupt_init(); - -#if defined(CONFIG_BOARD_LATE_INIT) - board_late_init(); -#endif - -#if defined(CONFIG_CMD_NET) - puts("NET: "); - eth_initialize(); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET(); - main_loop(); - } -} diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c index 6451ea9..68c5f8a 100644 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c @@ -70,7 +70,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, mddrc_config = &default_mddrc_config; if (dram_init_seq == NULL) { dram_init_seq = default_init_seq; - seq_sz = sizeof(default_init_seq)/sizeof(u32); + seq_sz = ARRAY_SIZE(default_init_seq); } /* Initialize IO Control */ diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c index 7a463b5..84fabbd 100644 --- a/arch/powerpc/cpu/mpc5xxx/cpu.c +++ b/arch/powerpc/cpu/mpc5xxx/cpu.c @@ -96,7 +96,7 @@ unsigned long get_tbclk (void) /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP void ft_cpu_setup(void *blob, bd_t *bd) { int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; @@ -117,7 +117,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0); do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0); #endif -#if defined(CONFIG_OF_IDE_FIXUP) +#ifdef CONFIG_OF_IDE_FIXUP if (!ide_device_present(0)) { /* NO CF card detected -> delete ata node in DTS */ int nodeoffset = 0; @@ -132,10 +132,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) } } -#endif +#endif /* CONFIG_OF_IDE_FIXUP */ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */ #ifdef CONFIG_MPC5xxx_FEC /* Default initializations for FEC controllers. To override, diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 54793f0..b4c5543 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -83,8 +83,7 @@ _start: * This function is called when the platform is build with SPL * support from the main (full-blown) U-Boot. And the GD needs * to get cleared (again) so that the following generic - * board support code, defined via CONFIG_SYS_GENERIC_BOARD, - * initializes all variables correctly. + * board support code initializes all variables correctly. */ mr r3, r2 /* parameter 1: GD pointer */ li r4,0 /* parameter 2: value to fill */ diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c index 6eed6f5..9f2be3c 100644 --- a/arch/powerpc/cpu/mpc8260/cpu.c +++ b/arch/powerpc/cpu/mpc8260/cpu.c @@ -284,7 +284,7 @@ void watchdog_reset (void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP void ft_cpu_setup (void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -303,7 +303,7 @@ void ft_cpu_setup (void *blob, bd_t *bd) "clock-frequency", bd->bi_intfreq, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } -#endif /* CONFIG_OF_LIBFDT */ +#endif /* CONFIG_OF_BOARD_SETUP */ /* * Initializes on-chip ethernet controllers. diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c index a9bb5ad..55130f7 100644 --- a/arch/powerpc/cpu/mpc8260/cpu_init.c +++ b/arch/powerpc/cpu/mpc8260/cpu_init.c @@ -253,7 +253,7 @@ int prt_8260_rsr (void) RSR_ESRS, "External Soft"}, { RSR_EHRS, "External Hard"} }; - static int n = sizeof bits / sizeof bits[0]; + static int n = ARRAY_SIZE(bits); ulong rsr = gd->arch.reset_status; int i; char *sep; diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index 9bb395e..a11ad1e 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -362,7 +362,7 @@ int fec_initialize(bd_t *bis) struct eth_device* dev; int i; - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); @@ -432,7 +432,7 @@ static elbt_prdesc rxeacc_descs[] = { { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" }, { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" }, }; -static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]); +static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs); typedef struct { @@ -449,7 +449,7 @@ static elbt_prdesc txeacc_descs[] = { { offsetof(elbt_txeacc, un), "Underrun" }, { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" }, }; -static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]); +static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs); typedef struct { @@ -500,7 +500,7 @@ static elbt_prdesc epram_descs[] = { { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" }, { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"}, }; -static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]); +static int epram_ndesc = ARRAY_SIZE(epram_descs); /* * given an elbt_prdesc array and an array of base addresses, print diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 0791043..f911275 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -484,7 +484,7 @@ int prt_83xx_rsr(void) RSR_SRS, "External/Internal Soft"}, { RSR_HRS, "External/Internal Hard"} }; - static int n = sizeof bits / sizeof bits[0]; + static int n = ARRAY_SIZE(bits); ulong rsr = gd->arch.reset_status; int i; char *sep; diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 2e91f51..5498c19 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -412,7 +412,7 @@ int get_clocks(void) #endif corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); - if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { + if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) { /* corecnf_tab_index is too high, possibly wrong value */ return -11; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f168375..61f5639 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -958,6 +958,15 @@ int cpu_init_r(void) #ifdef CONFIG_FSL_CAAM sec_init(); + +#if defined(CONFIG_PPC_C29X) + if ((SVR_SOC_VER(svr) == SVR_C292) || + (SVR_SOC_VER(svr) == SVR_C293)) + sec_init_idx(1); + + if (SVR_SOC_VER(svr) == SVR_C293) + sec_init_idx(2); +#endif #endif #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c index 14358ae..51f1bee 100644 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -424,7 +424,7 @@ int fec_initialize(bd_t *bis) struct eth_device* dev; int i; - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 82a151a..4c51225 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -720,16 +720,39 @@ enable_l2_cluster_l2: ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync stw r4, 0(r3) /* invalidate L2 */ + /* Poll till the bits are cleared */ 1: sync lwz r0, 0(r3) twi 0, r0, 0 isync and. r1, r0, r4 bne 1b + + /* L2PE must be set before L2 cache is enabled */ + lis r4, (L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2PE)@l + sync + stw r4, 0(r3) /* enable L2 parity/ECC error checking */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + delete_ccsr_l2_tlb: delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index ea4ab3a..f1ae358 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -137,7 +137,7 @@ int fec_initialize(bd_t *bis) struct ether_fcc_info_s *efis; int i; - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { dev = malloc(sizeof(*dev)); if (dev == NULL) @@ -879,7 +879,7 @@ void mii_init (void) /* Setup the pin configuration of the FEC(s) */ - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) fec_pin_init(ether_fcc_info[i].ether_index); } diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 5f5c720..4013a0c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -449,13 +449,6 @@ cpu_init_f (void) mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ - -#ifndef CONFIG_SYS_GENERIC_BOARD - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset((void *)gd, 0, sizeof(gd_t)); -#endif } /* diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index eef9c5a..c73509b 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -11,7 +11,7 @@ #include <asm/cache.h> #include <asm/ppc4xx.h> -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP #include <libfdt.h> #include <fdt_support.h> #include <asm/4xx_pcie.h> @@ -160,4 +160,4 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ fdt_pcie_setup(blob); } -#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c index 339d38a..a42327e 100644 --- a/arch/powerpc/cpu/ppc4xx/reginfo.c +++ b/arch/powerpc/cpu/ppc4xx/reginfo.c @@ -321,7 +321,7 @@ void ppc4xx_reginfo(void) PRINT_DCR(OPB2PLB40_BCTRL); PRINT_DCR(P4P3BO0_CFG); #endif - n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]); + n = ARRAY_SIZE(ppc4xx_reg); for (i = 0; i < n; i++) { value = 0; type = ppc4xx_reg[i].type; diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c index d4ef36d..cd63456 100644 --- a/arch/powerpc/cpu/ppc4xx/sdram.c +++ b/arch/powerpc/cpu/ppc4xx/sdram.c @@ -33,7 +33,7 @@ sdram_conf_t mb0cf[] = { sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #endif -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) +#define N_MB0CF (ARRAY_SIZE(mb0cf)) #ifdef CONFIG_SYS_SDRAM_CASL static ulong ns2clks(ulong ns) @@ -266,7 +266,7 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */ #endif -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) +#define N_MB0CF (ARRAY_SIZE(mb0cf)) #define NUM_TRIES 64 #define NUM_READS 10 diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 137afce..b432b18 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -760,7 +760,6 @@ _start: #endif bl cpu_init_f /* run low-level CPU init code (from Flash) */ -#ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 bl board_init_f_alloc_reserve mr r1, r3 @@ -768,7 +767,6 @@ _start: li r0,0 stwu r0, -4(r1) stwu r0, -4(r1) -#endif li r3, 0 bl board_init_f /* NOTREACHED - board_init_f() does not return */ @@ -1037,14 +1035,12 @@ _start: GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ -#ifdef CONFIG_SYS_GENERIC_BOARD mr r3, r1 bl board_init_f_alloc_reserve mr r1, r3 bl board_init_f_init_reserve stwu r0, -4(r1) stwu r0, -4(r1) -#endif li r3, 0 bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */ diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index da7352a..41b6677 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -14,6 +14,8 @@ #ifndef __ASM_ARCH_MX85XX_GPIO_H #define __ASM_ARCH_MX85XX_GPIO_H +#ifndef CONFIG_MPC85XX_GPIO #include <asm/mpc85xx_gpio.h> +#endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index eccc146..505d355 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 +#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 #elif defined(CONFIG_QEMU_E500) #define CONFIG_MAX_CPUS 1 @@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif +#if !defined(CONFIG_PPC_C29X) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 07d2adf..c045a24 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -265,6 +265,7 @@ typedef struct ccsr_pcix { #define PIWAR_WRITE_SNOOP 0x00005000 #define PIWAR_MEM_2G 0x0000001e +#ifndef CONFIG_MPC85XX_GPIO typedef struct ccsr_gpio { u32 gpdir; u32 gpodr; @@ -273,6 +274,7 @@ typedef struct ccsr_gpio { u32 gpimr; u32 gpicr; } ccsr_gpio_t; +#endif /* L2 Cache Registers */ typedef struct ccsr_l2cache { diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index a61e998..74b6202 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -14,112 +14,8 @@ #ifndef __U_BOOT_H__ #define __U_BOOT_H__ -/* - * Board information passed to Linux kernel from U-Boot - * - * include/asm-ppc/u-boot.h - */ - -#ifdef CONFIG_SYS_GENERIC_BOARD /* Use the generic board which requires a unified bd_info */ #include <asm-generic/u-boot.h> -#else - -#ifndef __ASSEMBLY__ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) - unsigned long bi_immr_base; /* base of IMMR register */ -#endif -#if defined(CONFIG_MPC5xxx) - unsigned long bi_mbar_base; /* base of internal registers */ -#endif -#if defined(CONFIG_MPC83xx) - unsigned long bi_immrbar; -#endif - unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#if defined(CONFIG_CPM2) - unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ - unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ - unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ - unsigned long bi_vco; /* VCO Out from PLL, in MHz */ -#endif -#if defined(CONFIG_MPC512X) - unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ - unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ -#endif -#if defined(CONFIG_405) || \ - defined(CONFIG_405GP) || \ - defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || \ - defined(CONFIG_440) - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ - unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ -#endif - -#ifdef CONFIG_HAS_ETH1 - unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH2 - unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH3 - unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH4 - unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH5 - unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - unsigned int bi_opbfreq; /* OPB clock in Hz */ - int bi_iic_fast[2]; /* Use fast i2c mode */ -#endif -#if defined(CONFIG_4xx) -#if defined(CONFIG_440GX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - int bi_phynum[4]; /* Determines phy mapping */ - int bi_phymode[4]; /* Determines phy mode */ -#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440) - int bi_phynum[2]; /* Determines phy mapping */ - int bi_phymode[2]; /* Determines phy mode */ -#else - int bi_phynum[1]; /* Determines phy mapping */ - int bi_phymode[1]; /* Determines phy mode */ -#endif -#endif /* defined(CONFIG_4xx) */ -} bd_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* !CONFIG_SYS_GENERIC_BOARD */ /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_PPC diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 05b22bb..3c97476 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -29,11 +29,6 @@ obj-y += ticks.o obj-y += reloc.o obj-$(CONFIG_BAT_RW) += bat_rw.o -ifndef CONFIG_SPL_BUILD -ifndef CONFIG_SYS_GENERIC_BOARD -obj-y += board.o -endif -endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index b96dbc6..66cf02d 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -65,6 +65,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ +#endif blr /* @@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbi's to get to ram */ +#endif blr diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S index 8152ac9..56bb3b8 100644 --- a/arch/powerpc/lib/ppcstring.S +++ b/arch/powerpc/lib/ppcstring.S @@ -92,13 +92,6 @@ memset: bdnz 8b blr - .globl bcopy -bcopy: - mr r6,r3 - mr r3,r4 - mr r4,r6 - b memcpy - .globl memmove memmove: cmplw 0,r3,r4 diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index d2a7dc9..2b4dbd3 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -360,8 +360,8 @@ int state_init(void) assert(state->ram_buf); /* No reset yet, so mark it as such. Always allow power reset */ - state->last_reset = RESET_COUNT; - state->reset_allowed[RESET_POWER] = true; + state->last_sysreset = SYSRESET_COUNT; + state->sysreset_allowed[SYSRESET_POWER] = true; /* * Example of how to use GPIOs: diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8930009..686c215 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -216,6 +216,17 @@ }; }; + mbox: mbox { + compatible = "sandbox,mbox"; + #mbox-cells = <1>; + }; + + mbox-test { + compatible = "sandbox,mbox-test"; + mboxes = <&mbox 100>, <&mbox 1>; + mbox-names = "other", "test"; + }; + mmc { compatible = "sandbox,mmc"; }; diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index 8317db1..427af2c 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -41,6 +41,26 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); /** + * Set or reset the simulated open drain mode of a GPIO (used only in sandbox + * test code) + * + * @param gp GPIO number + * @param value value to set (0 for enabled open drain mode, non-zero for + * disabled) + * @return -1 on error, 0 if ok + */ +int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value); + +/** + * Return the state of the simulated open drain mode of a GPIO (used only in + * sandbox test code) + * + * @param gp GPIO number + * @return -1 on error, 0 if GPIO is input, >0 if output + */ +int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset); + +/** * Return the simulated direction of a GPIO (used only in sandbox test code) * * @param gp GPIO number diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h new file mode 100644 index 0000000..2d7b7d0 --- /dev/null +++ b/arch/sandbox/include/asm/mbox.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SANDBOX_MBOX_H +#define __SANDBOX_MBOX_H + +#include <common.h> + +#define SANDBOX_MBOX_PING_XOR 0x12345678 + +struct udevice; + +int sandbox_mbox_test_get(struct udevice *dev); +int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg); +int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg); +int sandbox_mbox_test_free(struct udevice *dev); + +#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 11856c2..149f28d 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -7,7 +7,7 @@ #define __SANDBOX_STATE_H #include <config.h> -#include <reset.h> +#include <sysreset.h> #include <stdbool.h> #include <linux/stringify.h> @@ -60,8 +60,8 @@ struct sandbox_state { bool write_state; /* Write sandbox state on exit */ bool ignore_missing_state_on_read; /* No error if state missing */ bool show_lcd; /* Show LCD on start-up */ - enum reset_t last_reset; /* Last reset type */ - bool reset_allowed[RESET_COUNT]; /* Allowed reset types */ + enum sysreset_t last_sysreset; /* Last system reset type */ + bool sysreset_allowed[SYSRESET_COUNT]; /* Allowed system reset types */ enum state_terminal_raw term_raw; /* Terminal raw/cooked */ bool skip_delays; /* Ignore any time delays (for test) */ bool show_test_output; /* Don't suppress stdout in tests */ diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c index a2f856f..9a93cf5 100644 --- a/arch/sh/cpu/sh2/cpu.c +++ b/arch/sh/cpu/sh2/cpu.c @@ -83,3 +83,9 @@ int dcache_status(void) { return 0; } + +void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) +{ + /* TODO(sh maintainer): Implement this */ + while (1); +} diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S index ebf731a..6171edc 100644 --- a/arch/sh/cpu/sh2/start.S +++ b/arch/sh/cpu/sh2/start.S @@ -46,8 +46,9 @@ _init: mov.l ._gd_init, r13 /* global data */ mov.l ._stack_init, r15 /* stack */ - mov.l ._sh_generic_init, r0 - jsr @r0 + #TODO(sh maintainer): Fix this up to call the correct code + #mov.l ._sh_generic_init, r0 + #jsr @r0 nop loop: @@ -62,4 +63,4 @@ loop: ._bss_end: .long bss_end ._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) ._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -._sh_generic_init: .long sh_generic_init +#._sh_generic_init: .long sh_generic_init diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c index ea0006a..494f908 100644 --- a/arch/sh/cpu/sh3/cpu.c +++ b/arch/sh/cpu/sh3/cpu.c @@ -66,3 +66,9 @@ int dcache_status(void) { return 0; } + +void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) +{ + /* TODO(sh maintainer): Implement this */ + while (1); +} diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S index 7a934e2..9ed7198 100644 --- a/arch/sh/cpu/sh3/start.S +++ b/arch/sh/cpu/sh3/start.S @@ -45,8 +45,9 @@ _sh_start: mov.l ._gd_init, r13 /* global data */ mov.l ._stack_init, r15 /* stack */ - mov.l ._sh_generic_init, r0 - jsr @r0 + #TODO(sh maintainer): Fix this up to call the correct code + #mov.l ._sh_generic_init, r0 + #jsr @r0 nop loop: @@ -61,4 +62,4 @@ loop: ._bss_end: .long bss_end ._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) ._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -._sh_generic_init: .long sh_generic_init +#._sh_generic_init: .long sh_generic_init diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index e8ee0a4..de90ca7 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -75,3 +75,9 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } + +void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) +{ + /* TODO(sh maintainer): Implement this */ + while (1); +} diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S index 21644b5..77fc221 100644 --- a/arch/sh/cpu/sh4/start.S +++ b/arch/sh/cpu/sh4/start.S @@ -42,8 +42,9 @@ _sh_start: mov.l ._gd_init, r13 /* global data */ mov.l ._stack_init, r15 /* stack */ - mov.l ._sh_generic_init, r0 - jsr @r0 + #TODO(sh maintainer): Fix this up to call the correct code + #mov.l ._sh_generic_init, r0 + #jsr @r0 nop loop: @@ -58,4 +59,4 @@ loop: ._bss_end: .long bss_end ._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) ._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -._sh_generic_init: .long sh_generic_init +#._sh_generic_init: .long sh_generic_init diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 30c7a9d..78611c2 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -67,6 +67,7 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } + PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index ea37c24..716d8e9 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -12,16 +12,8 @@ #ifndef __ASM_SH_U_BOOT_H_ #define __ASM_SH_U_BOOT_H_ -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_boot_params; /* where this board expects params */ -} bd_t; +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_SH diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index f7ae4f8..c5cf89f 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -6,7 +6,6 @@ # -obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o ifeq ($(CONFIG_CPU_SH2),y) obj-y += time_sh2.o diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c deleted file mode 100644 index 69cdca3..0000000 --- a/arch/sh/lib/board.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (C) 2007, 2008, 2010 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <console.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <version.h> -#include <watchdog.h> -#include <net.h> -#include <mmc.h> -#include <environment.h> - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern int cpu_init(void); -extern int board_init(void); -extern int dram_init(void); -extern int timer_init(void); - -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; - -#ifndef CONFIG_SYS_NO_FLASH -static int sh_flash_init(void) -{ - gd->bd->bi_flashsize = flash_init(); - - if (gd->bd->bi_flashsize >= (1024 * 1024)) - printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024)); - else - printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024); - - return 0; -} -#endif /* CONFIG_SYS_NO_FLASH */ - -#if defined(CONFIG_CMD_NAND) -# include <nand.h> -# define INIT_FUNC_NAND_INIT nand_init, -#else -# define INIT_FUNC_NAND_INIT -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_WATCHDOG) -extern int watchdog_init(void); -extern int watchdog_disable(void); -# undef INIT_FUNC_WATCHDOG_INIT -# define INIT_FUNC_WATCHDOG_INIT watchdog_init, -# define WATCHDOG_DISABLE watchdog_disable -#else -# define INIT_FUNC_WATCHDOG_INIT -# define WATCHDOG_DISABLE -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_CMD_IDE) -# include <ide.h> -# define INIT_FUNC_IDE_INIT ide_init, -#else -# define INIT_FUNC_IDE_INIT -#endif /* CONFIG_CMD_IDE */ - -#if defined(CONFIG_PCI) -#include <pci.h> -static int sh_pci_init(void) -{ - pci_init(); - return 0; -} -# define INIT_FUNC_PCI_INIT sh_pci_init, -#else -# define INIT_FUNC_PCI_INIT -#endif /* CONFIG_PCI */ - -static int sh_mem_env_init(void) -{ - mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE - - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16); - env_relocate(); - jumptable_init(); - return 0; -} - -#if defined(CONFIG_CMD_MMC) -static int sh_mmc_init(void) -{ - puts("MMC: "); - mmc_initialize(gd->bd); - return 0; -} -#endif - -typedef int (init_fnc_t) (void); - -init_fnc_t *init_sequence[] = -{ - cpu_init, /* basic cpu dependent setup */ - board_init, /* basic board dependent setup */ - interrupt_init, /* set up exceptions */ - env_init, /* event init */ - serial_init, /* SCIF init */ - INIT_FUNC_WATCHDOG_INIT /* watchdog init */ - console_init_f, - display_options, - checkcpu, - checkboard, /* Check support board */ - dram_init, /* SDRAM init */ - timer_init, /* SuperH Timer (TCNT0 only) init */ - sh_mem_env_init, -#ifndef CONFIG_SYS_NO_FLASH - sh_flash_init, /* Flash memory init*/ -#endif - INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */ - INIT_FUNC_PCI_INIT /* PCI init */ - stdio_init, - console_init_r, - interrupt_init, -#ifdef CONFIG_BOARD_LATE_INIT - board_late_init, -#endif -#if defined(CONFIG_CMD_MMC) - sh_mmc_init, -#endif - NULL /* Terminate this list */ -}; - -void sh_generic_init(void) -{ - bd_t *bd; - init_fnc_t **init_fnc_ptr; - - memset(gd, 0, GENERATED_GBL_DATA_SIZE); - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - gd->bd = (bd_t *)(gd + 1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; -#endif -#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -#endif - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET(); - if ((*init_fnc_ptr) () != 0) - hang(); - } - -#ifdef CONFIG_WATCHDOG - /* disable watchdog if environment is set */ - { - char *s = getenv("watchdog"); - if (s != NULL) - if (strncmp(s, "off", 3) == 0) - WATCHDOG_DISABLE(); - } -#endif /* CONFIG_WATCHDOG*/ - - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(); -#endif /* CONFIG_CMD_NET */ - - while (1) { - WATCHDOG_RESET(); - main_loop(); - } -} diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 396023e..29d2307 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -274,6 +274,13 @@ config ENABLE_MRC_CACHE to be used for speeding up boot time on future reboots and/or power cycles. + For platforms that use Intel FSP for the memory initialization, + please check FSP output HOB via U-Boot command 'fsp hob' to see + if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). + If such GUID does not exist, MRC cache is not avaiable on such + platform (eg: Intel Queensbay), which means selecting this option + here does not make any difference. + config HAVE_MRC bool "Add a System Agent binary" depends on !HAVE_FSP @@ -439,21 +446,13 @@ config GENERATE_MP_TABLE config GENERATE_ACPI_TABLE bool "Generate an ACPI (Advanced Configuration and Power Interface) table" default n + select QFW if QEMU help The Advanced Configuration and Power Interface (ACPI) specification provides an open standard for device configuration and management by the operating system. It defines platform-independent interfaces for configuration and power management monitoring. -config QEMU_ACPI_TABLE - bool "Load ACPI table from QEMU fw_cfg interface" - depends on GENERATE_ACPI_TABLE && QEMU - default y - help - By default, U-Boot generates its own ACPI tables. This option, if - enabled, disables U-Boot's version and loads ACPI tables generated - by QEMU. - config GENERATE_SMBIOS_TABLE bool "Generate an SMBIOS (System Management BIOS) table" default y @@ -465,6 +464,22 @@ config GENERATE_SMBIOS_TABLE Check http://www.dmtf.org/standards/smbios for details. +config SMBIOS_MANUFACTURER + string "SMBIOS Manufacturer" + depends on GENERATE_SMBIOS_TABLE + default SYS_VENDOR + help + The board manufacturer to store in SMBIOS structures. + Change this to override the default one (CONFIG_SYS_VENDOR). + +config SMBIOS_PRODUCT_NAME + string "SMBIOS Product Name" + depends on GENERATE_SMBIOS_TABLE + default SYS_BOARD + help + The product name to store in SMBIOS structures. + Change this to override the default one (CONFIG_SYS_BOARD). + endmenu config MAX_PIRQ_LINKS @@ -539,6 +554,20 @@ config SEABIOS Check http://www.seabios.org/SeaBIOS for details. +config HIGH_TABLE_SIZE + hex "Size of configuration tables which reside in high memory" + default 0x10000 + depends on SEABIOS + help + SeaBIOS itself resides in E seg and F seg, where U-Boot puts all + configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot + puts a copy of configuration tables in high memory region which + is reserved on the stack before relocation. The region size is + determined by this option. + + Increse it if the default size does not fit the board's needs. + This is most likely due to a large ACPI DSDT table is used. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index 5be5491..a0216f3 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -8,3 +8,4 @@ obj-y += cpu.o obj-y += early_uart.o obj-y += fsp_configs.o obj-y += valleyview.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c new file mode 100644 index 0000000..5ee4868 --- /dev/null +++ b/arch/x86/cpu/baytrail/acpi.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/acpi_table.h> +#include <asm/ioapic.h> +#include <asm/mpspec.h> +#include <asm/tables.h> +#include <asm/arch/iomap.h> + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_reg.addrh = 0; + fadt->reset_value = SYS_RST | RST_CPU; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = table_compute_checksum(fadt, header->length); +} + +static int acpi_create_madt_irq_overrides(u32 current) +{ + struct acpi_madt_irqoverride *irqovr; + u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; + int length = 0; + + irqovr = (void *)current; + length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + irqovr = (void *)(current + length); + length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); + + return length; +} + +u32 acpi_fill_madt(u32 current) +{ + current += acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, + io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irq_overrides(current); + + return current; +} diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 25382f9..b31f24e 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -53,14 +53,6 @@ int arch_misc_init(void) return 0; } -int reserve_arch(void) -{ -#ifdef CONFIG_ENABLE_MRC_CACHE - return mrccache_reserve(); -#else - return 0; -#endif -} #endif void reset_cpu(ulong addr) diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index f0798a7..317f57d 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -109,7 +109,8 @@ static void pch_enable_ioapic(void) { u32 reg32; - io_apic_set_id(0x02); + /* Make sure this is a unique ID within system */ + io_apic_set_id(0x04); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(0x01); diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 4bf5d15..e7befde 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data) return 0; } -int reserve_arch(void) -{ - return mrccache_reserve(); -} - int dram_init(void) { struct pei_data _pei_data __aligned(8); diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 845f86a..1b04203 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -39,15 +39,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -int last_stage_init(void) -{ - if (gd->flags & GD_FLG_COLD_BOOT) - timestamp_add_to_bootstage(); - - return 0; -} - -void board_final_cleanup(void) +static void board_final_cleanup(void) { /* * Un-cache the ROM so the kernel has one @@ -79,6 +71,16 @@ void board_final_cleanup(void) } } +int last_stage_init(void) +{ + if (gd->flags & GD_FLG_COLD_BOOT) + timestamp_add_to_bootstage(); + + board_final_cleanup(); + + return 0; +} + int misc_init_r(void) { return 0; diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 233a6c8..e522ff3 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,10 +25,12 @@ #include <errno.h> #include <malloc.h> #include <asm/control_regs.h> +#include <asm/coreboot_tables.h> #include <asm/cpu.h> #include <asm/lapic.h> #include <asm/microcode.h> #include <asm/mp.h> +#include <asm/mrccache.h> #include <asm/msr.h> #include <asm/mtrr.h> #include <asm/post.h> @@ -661,10 +663,20 @@ void show_boot_progress(int val) } #ifndef CONFIG_SYS_COREBOOT +/* + * Implement a weak default function for boards that optionally + * need to clean up the system before jumping to the kernel. + */ +__weak void board_final_cleanup(void) +{ +} + int last_stage_init(void) { write_tables(); + board_final_cleanup(); + return 0; } #endif @@ -741,3 +753,18 @@ int cpu_init_r(void) return 0; } + +#ifndef CONFIG_EFI_STUB +int reserve_arch(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + mrccache_reserve(); +#endif + +#ifdef CONFIG_SEABIOS + high_table_reserve(); +#endif + + return 0; +} +#endif diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 10dc4d4..dd2819a 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -15,14 +15,14 @@ #include <dm.h> #include <asm/cache.h> #include <asm/control_regs.h> +#include <asm/i8259.h> #include <asm/interrupt.h> #include <asm/io.h> -#include <asm/processor-flags.h> -#include <linux/compiler.h> +#include <asm/lapic.h> #include <asm/msr.h> +#include <asm/processor-flags.h> #include <asm/processor.h> #include <asm/u-boot-x86.h> -#include <asm/i8259.h> DECLARE_GLOBAL_DATA_PTR; @@ -266,6 +266,8 @@ int interrupt_init(void) i8259_init(); #endif + lapic_setup(); + /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 2950783..df3cd0a 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -13,6 +13,7 @@ #include <asm/irq.h> #include <asm/pci.h> #include <asm/pirq_routing.h> +#include <asm/tables.h> DECLARE_GLOBAL_DATA_PTR; @@ -121,6 +122,11 @@ static int create_pirq_routing_table(struct udevice *dev) priv->irq_mask = fdtdec_get_int(blob, node, "intel,pirq-mask", PIRQ_BITMAP); + if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) { + /* Reserve IRQ9 for SCI */ + priv->irq_mask &= ~(1 << 9); + } + if (priv->config == PIRQ_VIA_IBASE) { int ibase_off; @@ -142,6 +148,9 @@ static int create_pirq_routing_table(struct udevice *dev) priv->ibase &= ~0xf; } + priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit"); + priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0); + cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); if (!cell || len % sizeof(struct pirq_routing)) return -EINVAL; @@ -206,11 +215,30 @@ static int create_pirq_routing_table(struct udevice *dev) rt->size = irq_entries * sizeof(struct irq_info) + 32; + /* Fix up the table checksum */ + rt->checksum = table_compute_checksum(rt, rt->size); + pirq_routing_table = rt; return 0; } +static void irq_enable_sci(struct udevice *dev) +{ + struct irq_router *priv = dev_get_priv(dev); + + if (priv->actl_8bit) { + /* Bit7 must be turned on to enable ACPI */ + dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80); + } else { + /* Write 0 to enable SCI on IRQ9 */ + if (priv->config == PIRQ_VIA_PCI) + dm_pci_write_config32(dev->parent, priv->actl_addr, 0); + else + writel(0, priv->ibase + priv->actl_addr); + } +} + int irq_router_common_init(struct udevice *dev) { int ret; @@ -224,6 +252,9 @@ int irq_router_common_init(struct udevice *dev) pirq_route_irqs(dev, pirq_routing_table->slots, get_irq_slot_count(pirq_routing_table)); + if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) + irq_enable_sci(dev); + return 0; } diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 88ab797..ff1faa5 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -12,7 +12,6 @@ #include <fdtdec.h> #include <rtc.h> #include <pci.h> -#include <asm/acpi.h> #include <asm/intel_regs.h> #include <asm/interrupt.h> #include <asm/io.h> diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index cef4256..38e244b 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -12,10 +12,8 @@ #include <dm.h> #include <fdtdec.h> #include <malloc.h> -#include <asm/acpi.h> #include <asm/cpu.h> #include <asm/cpu_x86.h> -#include <asm/lapic.h> #include <asm/msr.h> #include <asm/msr-index.h> #include <asm/mtrr.h> @@ -419,7 +417,6 @@ static int model_206ax_init(struct udevice *dev) /* Enable the local cpu apics */ enable_lapic_tpr(); - lapic_setup(); /* Enable virtualization if enabled in CMOS */ enable_vmx(); diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index f7e0bc3..491f289 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -10,7 +10,6 @@ #include <common.h> #include <dm.h> #include <asm/msr.h> -#include <asm/acpi.h> #include <asm/cpu.h> #include <asm/intel_regs.h> #include <asm/io.h> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index e35e543..9d9f63d 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -201,11 +201,6 @@ static int recovery_mode_enabled(void) return false; } -int reserve_arch(void) -{ - return mrccache_reserve(); -} - static int copy_spd(struct udevice *dev, struct pei_data *peid) { const void *data; diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index 30d2313..fbea2d1 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v) void enable_lapic(void) { - msr_t msr; - - msr = msr_read(MSR_IA32_APICBASE); - msr.hi &= 0xffffff00; - msr.lo |= MSR_IA32_APICBASE_ENABLE; - msr.lo &= ~MSR_IA32_APICBASE_BASE; - msr.lo |= LAPIC_DEFAULT_BASE; - msr_write(MSR_IA32_APICBASE, msr); + if (!IS_ENABLED(CONFIG_INTEL_QUARK)) { + msr_t msr; + + msr = msr_read(MSR_IA32_APICBASE); + msr.hi &= 0xffffff00; + msr.lo |= MSR_IA32_APICBASE_ENABLE; + msr.lo &= ~MSR_IA32_APICBASE_BASE; + msr.lo |= LAPIC_DEFAULT_BASE; + msr_write(MSR_IA32_APICBASE, msr); + } } void disable_lapic(void) { - msr_t msr; + if (!IS_ENABLED(CONFIG_INTEL_QUARK)) { + msr_t msr; - msr = msr_read(MSR_IA32_APICBASE); - msr.lo &= ~MSR_IA32_APICBASE_ENABLE; - msr_write(MSR_IA32_APICBASE, msr); + msr = msr_read(MSR_IA32_APICBASE); + msr.lo &= ~MSR_IA32_APICBASE_ENABLE; + msr_write(MSR_IA32_APICBASE, msr); + } } unsigned long lapicid(void) @@ -120,7 +124,6 @@ int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) void lapic_setup(void) { -#ifdef CONFIG_SMP /* Only Pentium Pro and later have those MSR stuff */ debug("Setting up local apic: "); @@ -150,11 +153,7 @@ void lapic_setup(void) LAPIC_DELIVERY_MODE_NMI)); debug("apic_id: 0x%02lx, ", lapicid()); -#else /* !CONFIG_SMP */ - /* Only Pentium Pro and later have those MSR stuff */ - debug("Disabling local apic: "); - disable_lapic(); -#endif /* CONFIG_SMP */ + debug("done.\n"); post_code(POST_LAPIC); } diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 2604a68..2b6b3bd 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -11,6 +11,7 @@ #include <dm.h> #include <errno.h> #include <malloc.h> +#include <qfw.h> #include <asm/atomic.h> #include <asm/cpu.h> #include <asm/interrupt.h> @@ -21,7 +22,6 @@ #include <asm/mtrr.h> #include <asm/processor.h> #include <asm/sipi.h> -#include <asm/fw_cfg.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include <dm/lists.h> @@ -408,8 +408,6 @@ static int init_bsp(struct udevice **devp) cpu_get_name(processor_name); debug("CPU: %s\n", processor_name); - lapic_setup(); - apic_id = lapicid(); ret = find_cpu_by_apic_id(apic_id, devp); if (ret) { @@ -420,7 +418,7 @@ static int init_bsp(struct udevice **devp) return 0; } -#ifdef CONFIG_QEMU +#ifdef CONFIG_QFW static int qemu_cpu_fixup(void) { int ret; @@ -496,7 +494,7 @@ int mp_init(struct mp_params *p) if (ret) return ret; -#ifdef CONFIG_QEMU +#ifdef CONFIG_QFW ret = qemu_cpu_fixup(); if (ret) return ret; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 6eeddf1..a080c5e 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -7,4 +7,5 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif -obj-y += cpu.o fw_cfg.o qemu.o +obj-y += qemu.o +obj-$(CONFIG_QFW) += cpu.o e820.o diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index a1b70c6..b1a965e 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -8,8 +8,8 @@ #include <cpu.h> #include <dm.h> #include <errno.h> +#include <qfw.h> #include <asm/cpu.h> -#include <asm/fw_cfg.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c new file mode 100644 index 0000000..63853e4 --- /dev/null +++ b/arch/x86/cpu/qemu/e820.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/e820.h> + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + entries[0].addr = 0; + entries[0].size = ISA_START_ADDRESS; + entries[0].type = E820_RAM; + + entries[1].addr = ISA_START_ADDRESS; + entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[1].type = E820_RESERVED; + + /* + * since we use memalign(malloc) to allocate high memory for + * storing ACPI tables, we need to reserve them in e820 tables, + * otherwise kernel will reclaim them and data will be corrupted + */ + entries[2].addr = ISA_END_ADDRESS; + entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; + entries[2].type = E820_RAM; + + /* for simplicity, reserve entire malloc space */ + entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; + entries[3].size = TOTAL_MALLOC_LEN; + entries[3].type = E820_RESERVED; + + entries[4].addr = gd->relocaddr; + entries[4].size = gd->ram_size - gd->relocaddr; + entries[4].type = E820_RESERVED; + + entries[5].addr = CONFIG_PCIE_ECAM_BASE; + entries[5].size = CONFIG_PCIE_ECAM_SIZE; + entries[5].type = E820_RESERVED; + + return 6; +} diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c deleted file mode 100644 index 2e2794e..0000000 --- a/arch/x86/cpu/qemu/fw_cfg.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/fw_cfg.h> -#include <asm/tables.h> -#include <asm/e820.h> -#include <linux/list.h> -#include <memalign.h> - -static bool fwcfg_present; -static bool fwcfg_dma_present; - -static LIST_HEAD(fw_list); - -/* Read configuration item using fw_cfg PIO interface */ -static void qemu_fwcfg_read_entry_pio(uint16_t entry, - uint32_t size, void *address) -{ - uint32_t i = 0; - uint8_t *data = address; - - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - outw(entry, FW_CONTROL_PORT); - while (size--) - data[i++] = inb(FW_DATA_PORT); -} - -/* Read configuration item using fw_cfg DMA interface */ -static void qemu_fwcfg_read_entry_dma(uint16_t entry, - uint32_t size, void *address) -{ - struct fw_cfg_dma_access dma; - - dma.length = cpu_to_be32(size); - dma.address = cpu_to_be64((uintptr_t)address); - dma.control = cpu_to_be32(FW_CFG_DMA_READ); - - /* - * writting FW_CFG_INVALID will cause read operation to resume at - * last offset, otherwise read will start at offset 0 - */ - if (entry != FW_CFG_INVALID) - dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16)); - - barrier(); - - debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n", - address, size, be32_to_cpu(dma.control)); - - outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH); - - while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR) - __asm__ __volatile__ ("pause"); -} - -static bool qemu_fwcfg_present(void) -{ - uint32_t qemu; - - qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu); - return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE; -} - -static bool qemu_fwcfg_dma_present(void) -{ - uint8_t dma_enabled; - - qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled); - if (dma_enabled & FW_CFG_DMA_ENABLED) - return true; - - return false; -} - -static void qemu_fwcfg_read_entry(uint16_t entry, - uint32_t length, void *address) -{ - if (fwcfg_dma_present) - qemu_fwcfg_read_entry_dma(entry, length, address); - else - qemu_fwcfg_read_entry_pio(entry, length, address); -} - -int qemu_fwcfg_online_cpus(void) -{ - uint16_t nb_cpus; - - if (!fwcfg_present) - return -ENODEV; - - qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus); - - return le16_to_cpu(nb_cpus); -} - -/* - * This function prepares kernel for zboot. It loads kernel data - * to 'load_addr', initrd to 'initrd_addr' and kernel command - * line using qemu fw_cfg interface. - */ -static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) -{ - char *data_addr; - uint32_t setup_size, kernel_size, cmdline_size, initrd_size; - - qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size); - qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size); - - if (setup_size == 0 || kernel_size == 0) { - printf("warning: no kernel available\n"); - return -1; - } - - data_addr = load_addr; - qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA, - le32_to_cpu(setup_size), data_addr); - data_addr += le32_to_cpu(setup_size); - - qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA, - le32_to_cpu(kernel_size), data_addr); - data_addr += le32_to_cpu(kernel_size); - - data_addr = initrd_addr; - qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size); - if (initrd_size == 0) { - printf("warning: no initrd available\n"); - } else { - qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA, - le32_to_cpu(initrd_size), data_addr); - data_addr += le32_to_cpu(initrd_size); - } - - qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size); - if (cmdline_size) { - qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA, - le32_to_cpu(cmdline_size), data_addr); - /* - * if kernel cmdline only contains '\0', (e.g. no -append - * when invoking qemu), do not update bootargs - */ - if (*data_addr != '\0') { - if (setenv("bootargs", data_addr) < 0) - printf("warning: unable to change bootargs\n"); - } - } - - printf("loading kernel to address %p size %x", load_addr, - le32_to_cpu(kernel_size)); - if (initrd_size) - printf(" initrd %p size %x\n", - initrd_addr, - le32_to_cpu(initrd_size)); - else - printf("\n"); - - return 0; -} - -static int qemu_fwcfg_read_firmware_list(void) -{ - int i; - uint32_t count; - struct fw_file *file; - struct list_head *entry; - - /* don't read it twice */ - if (!list_empty(&fw_list)) - return 0; - - qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); - if (!count) - return 0; - - count = be32_to_cpu(count); - for (i = 0; i < count; i++) { - file = malloc(sizeof(*file)); - if (!file) { - printf("error: allocating resource\n"); - goto err; - } - qemu_fwcfg_read_entry(FW_CFG_INVALID, - sizeof(struct fw_cfg_file), &file->cfg); - file->addr = 0; - list_add_tail(&file->list, &fw_list); - } - - return 0; - -err: - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - free(file); - } - - return -ENOMEM; -} - -#ifdef CONFIG_QEMU_ACPI_TABLE -static struct fw_file *qemu_fwcfg_find_file(const char *name) -{ - struct list_head *entry; - struct fw_file *file; - - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - if (!strcmp(file->cfg.name, name)) - return file; - } - - return NULL; -} - -/* - * This function allocates memory for ACPI tables - * - * @entry : BIOS linker command entry which tells where to allocate memory - * (either high memory or low memory) - * @addr : The address that should be used for low memory allcation. If the - * memory allocation request is 'ZONE_HIGH' then this parameter will - * be ignored. - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) -{ - uint32_t size, align; - struct fw_file *file; - unsigned long aligned_addr; - - align = le32_to_cpu(entry->alloc.align); - /* align must be power of 2 */ - if (align & (align - 1)) { - printf("error: wrong alignment %u\n", align); - return -EINVAL; - } - - file = qemu_fwcfg_find_file(entry->alloc.file); - if (!file) { - printf("error: can't find file %s\n", entry->alloc.file); - return -ENOENT; - } - - size = be32_to_cpu(file->cfg.size); - - /* - * ZONE_HIGH means we need to allocate from high memory, since - * malloc space is already at the end of RAM, so we directly use it. - * If allocation zone is ZONE_FSEG, then we use the 'addr' passed - * in which is low memory - */ - if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) { - aligned_addr = (unsigned long)memalign(align, size); - if (!aligned_addr) { - printf("error: allocating resource\n"); - return -ENOMEM; - } - } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { - aligned_addr = ALIGN(*addr, align); - } else { - printf("error: invalid allocation zone\n"); - return -EINVAL; - } - - debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n", - file->cfg.name, size, entry->alloc.zone, align, aligned_addr); - - qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), - size, (void *)aligned_addr); - file->addr = aligned_addr; - - /* adjust address for low memory allocation */ - if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) - *addr = (aligned_addr + size); - - return 0; -} - -/* - * This function patches ACPI tables previously loaded - * by bios_linker_allocate() - * - * @entry : BIOS linker command entry which tells how to patch - * ACPI tables - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_add_pointer(struct bios_linker_entry *entry) -{ - struct fw_file *dest, *src; - uint32_t offset = le32_to_cpu(entry->pointer.offset); - uint64_t pointer = 0; - - dest = qemu_fwcfg_find_file(entry->pointer.dest_file); - if (!dest || !dest->addr) - return -ENOENT; - src = qemu_fwcfg_find_file(entry->pointer.src_file); - if (!src || !src->addr) - return -ENOENT; - - debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n", - dest->addr, src->addr, offset, entry->pointer.size, pointer); - - memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size); - pointer = le64_to_cpu(pointer); - pointer += (unsigned long)src->addr; - pointer = cpu_to_le64(pointer); - memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size); - - return 0; -} - -/* - * This function updates checksum fields of ACPI tables previously loaded - * by bios_linker_allocate() - * - * @entry : BIOS linker command entry which tells where to update ACPI table - * checksums - * @return: 0 on success, or negative value on failure - */ -static int bios_linker_add_checksum(struct bios_linker_entry *entry) -{ - struct fw_file *file; - uint8_t *data, cksum = 0; - uint8_t *cksum_start; - - file = qemu_fwcfg_find_file(entry->cksum.file); - if (!file || !file->addr) - return -ENOENT; - - data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset)); - cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start)); - cksum = table_compute_checksum(cksum_start, - le32_to_cpu(entry->cksum.length)); - *data = cksum; - - return 0; -} - -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) -{ - entries[0].addr = 0; - entries[0].size = ISA_START_ADDRESS; - entries[0].type = E820_RAM; - - entries[1].addr = ISA_START_ADDRESS; - entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; - entries[1].type = E820_RESERVED; - - /* - * since we use memalign(malloc) to allocate high memory for - * storing ACPI tables, we need to reserve them in e820 tables, - * otherwise kernel will reclaim them and data will be corrupted - */ - entries[2].addr = ISA_END_ADDRESS; - entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; - entries[2].type = E820_RAM; - - /* for simplicity, reserve entire malloc space */ - entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; - entries[3].size = TOTAL_MALLOC_LEN; - entries[3].type = E820_RESERVED; - - entries[4].addr = gd->relocaddr; - entries[4].size = gd->ram_size - gd->relocaddr; - entries[4].type = E820_RESERVED; - - entries[5].addr = CONFIG_PCIE_ECAM_BASE; - entries[5].size = CONFIG_PCIE_ECAM_SIZE; - entries[5].type = E820_RESERVED; - - return 6; -} - -/* This function loads and patches ACPI tables provided by QEMU */ -u32 write_acpi_tables(u32 addr) -{ - int i, ret = 0; - struct fw_file *file; - struct bios_linker_entry *table_loader; - struct bios_linker_entry *entry; - uint32_t size; - struct list_head *list; - - /* make sure fw_list is loaded */ - ret = qemu_fwcfg_read_firmware_list(); - if (ret) { - printf("error: can't read firmware file list\n"); - return addr; - } - - file = qemu_fwcfg_find_file("etc/table-loader"); - if (!file) { - printf("error: can't find etc/table-loader\n"); - return addr; - } - - size = be32_to_cpu(file->cfg.size); - if ((size % sizeof(*entry)) != 0) { - printf("error: table-loader maybe corrupted\n"); - return addr; - } - - table_loader = malloc(size); - if (!table_loader) { - printf("error: no memory for table-loader\n"); - return addr; - } - - qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), - size, table_loader); - - for (i = 0; i < (size / sizeof(*entry)); i++) { - entry = table_loader + i; - switch (le32_to_cpu(entry->command)) { - case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: - ret = bios_linker_allocate(entry, &addr); - if (ret) - goto out; - break; - case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: - ret = bios_linker_add_pointer(entry); - if (ret) - goto out; - break; - case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM: - ret = bios_linker_add_checksum(entry); - if (ret) - goto out; - break; - default: - break; - } - } - -out: - if (ret) { - list_for_each(list, &fw_list) { - file = list_entry(list, struct fw_file, list); - if (file->addr) - free((void *)file->addr); - } - } - - free(table_loader); - return addr; -} -#endif - -static int qemu_fwcfg_list_firmware(void) -{ - int ret; - struct list_head *entry; - struct fw_file *file; - - /* make sure fw_list is loaded */ - ret = qemu_fwcfg_read_firmware_list(); - if (ret) - return ret; - - list_for_each(entry, &fw_list) { - file = list_entry(entry, struct fw_file, list); - printf("%-56s\n", file->cfg.name); - } - - return 0; -} - -void qemu_fwcfg_init(void) -{ - fwcfg_present = qemu_fwcfg_present(); - if (fwcfg_present) - fwcfg_dma_present = qemu_fwcfg_dma_present(); -} - -static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (qemu_fwcfg_list_firmware() < 0) - return CMD_RET_FAILURE; - - return 0; -} - -static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - int ret = qemu_fwcfg_online_cpus(); - if (ret < 0) { - printf("QEMU fw_cfg interface not found\n"); - return CMD_RET_FAILURE; - } - - printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus()); - - return 0; -} - -static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - char *env; - void *load_addr; - void *initrd_addr; - - env = getenv("loadaddr"); - load_addr = env ? - (void *)simple_strtoul(env, NULL, 16) : - (void *)CONFIG_LOADADDR; - - env = getenv("ramdiskaddr"); - initrd_addr = env ? - (void *)simple_strtoul(env, NULL, 16) : - (void *)CONFIG_RAMDISK_ADDR; - - if (argc == 2) { - load_addr = (void *)simple_strtoul(argv[0], NULL, 16); - initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16); - } else if (argc == 1) { - load_addr = (void *)simple_strtoul(argv[0], NULL, 16); - } - - return qemu_fwcfg_setup_kernel(load_addr, initrd_addr); -} - -static cmd_tbl_t fwcfg_commands[] = { - U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""), - U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""), - U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""), -}; - -static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int ret; - cmd_tbl_t *fwcfg_cmd; - - if (!fwcfg_present) { - printf("QEMU fw_cfg interface not found\n"); - return CMD_RET_USAGE; - } - - fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands, - ARRAY_SIZE(fwcfg_commands)); - argc -= 2; - argv += 2; - if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs) - return CMD_RET_USAGE; - - ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv); - - return cmd_process_error(fwcfg_cmd, ret); -} - -U_BOOT_CMD( - qfw, 4, 1, do_qemu_fw, - "QEMU firmware interface", - "<command>\n" - " - list : print firmware(s) currently loaded\n" - " - cpus : print online cpu number\n" - " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n" -) diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 7ad0ee4..680e558 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,15 +6,59 @@ #include <common.h> #include <pci.h> +#include <qfw.h> #include <asm/irq.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> -#include <asm/fw_cfg.h> static bool i440fx; +#ifdef CONFIG_QFW + +/* on x86, the qfw registers are all IO ports */ +#define FW_CONTROL_PORT 0x510 +#define FW_DATA_PORT 0x511 +#define FW_DMA_PORT_LOW 0x514 +#define FW_DMA_PORT_HIGH 0x518 + +static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry, + uint32_t size, void *address) +{ + uint32_t i = 0; + uint8_t *data = address; + + /* + * writting FW_CFG_INVALID will cause read operation to resume at + * last offset, otherwise read will start at offset 0 + * + * Note: on platform where the control register is IO port, the + * endianness is little endian. + */ + if (entry != FW_CFG_INVALID) + outw(cpu_to_le16(entry), FW_CONTROL_PORT); + + /* the endianness of data register is string-preserving */ + while (size--) + data[i++] = inb(FW_DATA_PORT); +} + +static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma) +{ + /* the DMA address register is big endian */ + outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH); + + while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) + __asm__ __volatile__ ("pause"); +} + +static struct fw_cfg_arch_ops fwcfg_x86_ops = { + .arch_read_pio = qemu_x86_fwcfg_read_entry_pio, + .arch_read_dma = qemu_x86_fwcfg_read_entry_dma +}; +#endif + static void enable_pm_piix(void) { u8 en; @@ -88,7 +132,9 @@ static void qemu_chipset_init(void) enable_pm_ich9(); } - qemu_fwcfg_init(); +#ifdef CONFIG_QFW + qemu_fwcfg_init(&fwcfg_x86_ops); +#endif } int arch_cpu_init(void) diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile index 6d670d7..93ce412 100644 --- a/arch/x86/cpu/quark/Makefile +++ b/arch/x86/cpu/quark/Makefile @@ -6,3 +6,4 @@ obj-y += car.o dram.o irq.o msg_port.o quark.o obj-y += mrc.o mrc_util.o hte.o smc.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c new file mode 100644 index 0000000..8f69829 --- /dev/null +++ b/arch/x86/cpu/quark/acpi.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/acpi_table.h> +#include <asm/ioapic.h> +#include <asm/mpspec.h> +#include <asm/tables.h> +#include <asm/arch/iomap.h> + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &(fadt->header); + u16 pmbase = ACPI_PM1_BASE_ADDRESS; + + memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS; + fadt->gpe1_blk = 0; + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0x00; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_reg.addrh = 0; + fadt->reset_value = SYS_RST | RST_CPU; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = table_compute_checksum(fadt, header->length); +} + +static int acpi_create_madt_irq_overrides(u32 current) +{ + struct acpi_madt_irqoverride *irqovr; + u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; + int length = 0; + + irqovr = (void *)current; + length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + irqovr = (void *)(current + length); + length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); + + return length; +} + +u32 acpi_fill_madt(u32 current) +{ + current += acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, + io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irq_overrides(current); + + return current; +} diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index afb3463..bdd360a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -7,6 +7,7 @@ #include <common.h> #include <mmc.h> #include <asm/io.h> +#include <asm/ioapic.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -338,6 +339,9 @@ int arch_misc_init(void) mrccache_save(); #endif + /* Assign a unique I/O APIC ID */ + io_apic_set_id(1); + return 0; } @@ -360,12 +364,3 @@ void board_final_cleanup(void) return; } - -int reserve_arch(void) -{ -#ifdef CONFIG_ENABLE_MRC_CACHE - return mrccache_reserve(); -#else - return 0; -#endif -} diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 4ea9262..4a50d86 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -84,6 +84,7 @@ compatible = "intel,irq-router"; intel,pirq-config = "ibase"; intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; intel,pirq-link = <8 8>; intel,pirq-mask = <0xdee0>; intel,pirq-routing = < @@ -249,10 +250,10 @@ #include "microcode/m0230671117.dtsi" }; update@1 { -#include "microcode/m0130673322.dtsi" +#include "microcode/m0130673325.dtsi" }; update@2 { -#include "microcode/m0130679901.dtsi" +#include "microcode/m0130679907.dtsi" }; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 478dece..1a4ecaa 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -88,6 +88,7 @@ compatible = "intel,irq-router"; intel,pirq-config = "ibase"; intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; intel,pirq-link = <8 8>; intel,pirq-mask = <0xdee0>; intel,pirq-routing = < @@ -269,10 +270,10 @@ microcode { update@0 { -#include "microcode/m0130673322.dtsi" +#include "microcode/m0130673325.dtsi" }; update@1 { -#include "microcode/m0130679901.dtsi" +#include "microcode/m0130679907.dtsi" }; }; }; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 337513b..78a1ef4 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -154,6 +154,7 @@ irq-router { compatible = "intel,queensbay-irq-router"; intel,pirq-config = "pci"; + intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; intel,pirq-mask = <0xcee0>; intel,pirq-routing = < diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 21c3641..da3cbff 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -29,6 +29,18 @@ stdout-path = &pciuart0; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + }; + tsc-timer { clock-frequency = <400000000>; }; @@ -88,6 +100,7 @@ irq-router { compatible = "intel,quark-irq-router"; intel,pirq-config = "pci"; + intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; intel,pirq-mask = <0xdef8>; intel,pirq-routing = < diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi deleted file mode 100644 index 90bf2fb..0000000 --- a/arch/x86/dts/microcode/m0130673322.dtsi +++ /dev/null @@ -1,3284 +0,0 @@ -/* - * --- - * This is a device tree fragment. Use #include to add these properties to a - * node. - * - * Date: - */ - -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x322>; -intel,date-code = <0x4012014>; -intel,processor-signature = <0x30673>; -intel,checksum = <0x17b0d914>; -intel,loader-revision = <1>; -intel,processor-flags = <0x1>; - -/* The first 48-bytes are the public header which repeats the above data */ -data = < - 0x01000000 0x22030000 0x14200104 0x73060300 - 0x14d9b017 0x01000000 0x01000000 0xd0cb0000 - 0x00cc0000 0x00000000 0x00000000 0x00000000 - 0x00000000 0xa1000000 0x01000200 0x22030000 - 0x00000000 0x00000000 0x31031420 0x11320000 - 0x01000000 0x73060300 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0xf4320000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x0ae10178 0x7c98f9d1 0x41962d85 0x19391270 - 0xcf3c0336 0xc1f13d6f 0xe46abaf6 0x3b65ca6b - 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 - 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26 - 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Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x325>; +intel,date-code = <0x11192014>; +intel,processor-signature = <0x30673>; +intel,checksum = <0x5edcd570>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x25030000 0x14201911 0x73060300 + 0x70d5dc5e 0x01000000 0x01000000 0xd0cb0000 + 0x00cc0000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x25030000 + 0x00000000 0x00000000 0x19111420 0x11320000 + 0x01000000 0x73060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xf4320000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0xfff634fa 0x937ca2ab 0xb28d19b6 0xdefc54a7 + 0xd8df0b32 0x13e9a2a8 0x7b7cb24d 0xd588d3a7 + 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 + 0x198e2c7d 0x7c665bbf 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Use #include to add these properties to a - * node. - * - * Date: - */ - -compatible = "intel,microcode"; -intel,header-version = <1>; -intel,update-revision = <0x901>; -intel,date-code = <0x4212014>; -intel,processor-signature = <0x30679>; -intel,checksum = <0x69c4e6f1>; -intel,loader-revision = <1>; -intel,processor-flags = <0x1>; - -/* The first 48-bytes are the public header which repeats the above data */ -data = < - 0x01000000 0x01090000 0x14202104 0x79060300 - 0xf1e6c469 0x01000000 0x01000000 0xd0cb0000 - 0x00cc0000 0x00000000 0x00000000 0x00000000 - 0x00000000 0xa1000000 0x01000200 0x01090000 - 0x00000000 0x00000000 0x18041420 0x01320000 - 0x01000000 0x79060300 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00000000 0xf4320000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 - 0x3b6ec6fe 0xc0fda75e 0xb4ea6a9f 0x8fd6ed15 - 0xd537f374 0x669bf3bb 0xebedec72 0xb4cbc889 - 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 - 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26 - 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Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x907>; +intel,date-code = <0x11142015>; +intel,processor-signature = <0x30679>; +intel,checksum = <0x1bb67b21>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x07090000 0x15201411 0x79060300 + 0x217bb61b 0x01000000 0x01000000 0xd0cb0000 + 0x00cc0000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x07090000 + 0x00000000 0x00000000 0x13111520 0x01320000 + 0x01000000 0x79060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xf4320000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x9703f29f 0x1c68d65c 0x1f15f858 0x114237f4 + 0xfef8d172 0x363b5a9d 0x4c3d9e71 0x13ff68a0 + 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 + 0x198e2c7d 0x7c665bbf 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0x8243c025 0xfe05b066 0xc1b0c590 + 0xd8c107ba 0x235b8c6a 0xac4fe894 0xa012810b + 0x5470e6de 0x6f1217ae 0xcb099ad1 0x2b03655e + 0x91f0b417 0xc21a1af4 0xb4a8c50e 0xa5988ed2 + 0x7f03fa1e 0xa0658a65 0x5532c4b3 0x1fdcfcec + 0x17f41c26 0xd6b29efb 0x3411f331 0x1b774029 + 0x2ee2d094 0x9f5edaab 0xc644a9f3 0xdc4cf7b1 + 0xb6304748 0xb064cfca 0x89e4dbee 0xb1563a5e + 0xd370bca8 0xe6cb17d8 0xbfcacc87 0x76940250 + 0xf2456a18 0x3c1873e4 0x0a3d7d0e 0xeb145eb9 + 0xe88a48fb 0x9413f290 0x626e4e00 0xb234a13b + 0xcbf49379 0xcf600cee 0xc78891b8 0x799f8e80 + 0xdbf4e604 0x89860862 0x04fb77db 0x0fb1bf13 + 0x3b1aa906 0xadaf9a45 0x48526bf7 0x09d8ffb3 + 0xce751581 0x00e35b8d 0x0549e629 0x6d3cc316 + 0x3d8f300a 0xdcd790b5 0xde1ca316 0x737d5f31 + 0x171b2646 0x4798a85d 0xea36f650 0xcf889098 + 0xe4ec65b8 0x944637d3 0x019c8103 0x5fbdc21c + 0xa61ebe77 0x74ea95a5 0x258eb8d1 0xf8c8c4d6 + 0x9a1edc66 0x9118b309 0x639ae9b5 0xd0c40735 + 0xc6ddec32 0x36d26a75 0x86018c99 0xe8bf66df + 0xf345dba0 0x780670a3 0xe34e60fd 0x733ad4ba + 0x2ef04d54 0xb1b9c41f 0x84cca1c2 0xaa09279b + 0x34797d41 0xb93d4c70 0x919ce970 0xd0d6ec5e + 0xdc70cc95 0xd89f4680 0x458cfd33 0xc257784b + 0x29ec9364 0x8e717417 0x6d9732df 0xa3658440 + 0x8574b5c6 0xa58ebb8c 0x81bc4dea 0x1f396663 + 0x361dfd98 0x20b35a46 0x886a7e4c 0x69f0a1c5 + 0xd0b7de5f 0xbbc08761 0xa1cef991 0x084a8ea2 + 0x4df68c5b 0xb84b4b2e 0xd4bf1770 0x94b4f7c7 + 0x9906a752 0x878c7f1f 0x385b5a5e 0x99147c87 + 0x97c54a35 0xbacb57d4 0xf85f9733 0xb5d2c83f + 0x4405f9f5 0x020260b5 0x5c0a8556 0xb623ad79 + 0x8d42a6a3 0x35ae5806 0x2c28a60d 0xa0200ee8 + 0xed9e0ece 0xb7e0442a 0x1ddf0e2b 0x26ceec5d + 0xda397b2c 0xb073d9a2 0x9d856bbd 0x06e35ca8 + 0x6296193e 0x292dee18 0xf5a9bd7a 0xb62fe73f + 0x95a8775f 0x1efc0fd0 0xf3338af4 0x06ccbe78 + 0xafb3f669 0xd9f7fe16 0x09beed63 0xa2f0bb3e + 0x02f5c52f 0x24aee650 0xf715039b 0x3f566d89 + 0xd575429b 0x9d40207d 0xa89c7de9 0xde5157f0 + 0xd79025ae 0x4259c4b6 0x61e86217 0x6d2e3273 + 0x57b5c99d 0xa18edb02 0xf5f314be 0xfa58bf5f + 0x581e95bb 0x04967c03 0x9187d903 0xdaf34bc3 + 0xa18e49f0 0xb7973963 0x2984967f 0x7332f94f + 0x57e5a8b5 0xe6e0a6f8 0xbc08c39f 0xc9e73ad8 + 0x0ea113d8 0xa9cfdb06 0xfda1ebbb 0x1a30e9f9 + 0x69a9029a 0x44b43320 0x04182d93 0x00220972 + 0xa7f984c5 0xb4eeae8a 0x11718517 0x06e70840 + 0xb3091fe5 0x099ccb1a 0xac3df88c 0xa8bd0ca3 + 0xa202bbc0 0x19979cf1 0x8656c385 0x139abf7b + 0xae298ea4 0xab9481ae 0xe08e2c38 0x27967dab + 0x1108054c 0x1ba0d3c5 0x8a0fb923 0x9c54f682 + 0x5f363a46 0xec564b34 0x8d53c918 0x47f39642 + 0x3fd68743 0x197f16cc 0x2b03d11c 0xcc574d53 + 0x8b2d1aa3 0xd403c5b0 0xce21d3a6 0x57c88abe + 0x56d6b12b 0x204f9ac8 0xfd44c338 0x18417de6 + 0x5582f0bf 0x7ea9d04f 0x7bdee65d 0x9fe3f5b5 + 0xa14edd82 0x8301f6ba 0x24bc737a 0x5c6e71a8 + 0xdb0d7fc2 0x243b6e99 0x3941f113 0xcaaa3674 + 0x1b25b686 0xfb219a33 0x1b122757 0x27298223 + 0x44cbb8ad 0xed4e6ef9 0xae338c2d 0xa8d231ee + 0x9bc2d8f3 0xcecd4d27 0xe8ba9908 0x9a106344 + 0xbdf27147 0x0c547009 0x46b16833 0xd89b0690 + 0x4b742f40 0x733d4cd5 0x1abb6f77 0x803f40df + 0xf8d909bb 0x8fa6a921 0x08966531 0xdf093174 + 0xc7ee92c8 0x4272612d 0x149f8242 0xf8c07ec3 + 0x99259781 0x8bf3f9c0 0x09d6b679 0x19a1968f + 0x735b197e 0xa98c913f 0x3e208a56 0x59b2b40b + 0x0ed212ed 0xfc92d02a 0xe9b1b441 0x1429fc3c + 0x8a6fb38c 0x6235d73e 0x82f5aca8 0x9ebb490a + 0x718fed05 0xee355cdc 0xf34bbc8e 0xcfde74ac + 0x5c267a70 0x30b66c7f 0x9a655781 0x1d354268 + 0xd0debf01 0x71798948 0x4542b707 0x66c02ecf + 0x49763e11 0xa02f170b 0xbcf30ee9 0xba9bbfec + 0x6d915d18 0xcadd484f 0x8eadbd10 0x91463818 + 0xe8add34f 0x55620c30 0x14d47fa5 0x63c2a25f + 0x7213f2f4 0x6d96a516 0xf10f4ed1 0x9825aeac + 0xe9ca9b8a 0x4bb0e2aa 0x957f8851 0x1a41de29 + 0xa0039e6c 0x3ec63393 0x66b6ac8a 0x2992d983 + 0x2d73caa4 0xb0ae06c2 0xa4008915 0x2ba7050d + 0x6d9e01e6 0x908f316f 0x3f17dabb 0x8c86b0e3 + 0x89fcebf8 0xbada4307 0x0f6e9f6f 0x07f36992 + 0x1a82520e 0x728f11a9 0x418aa9b7 0xc57f51d7 + 0xcffa1cd0 0xf9f6d902 0xdf22329a 0x4ac48293 + 0x37326e23 0xbb39c187 0xc9086dfe 0x1347e4f8 + 0x7ae88ecb 0xc280a07f 0x7f0a6b0a 0x57cff37d + 0x2dfd629d 0x5a8a444d 0x934bcafb 0x593b6a3a + 0x9c62c1ca 0x0ecdb2dc 0xb4c2fd82 0x2c19c0ab + 0x26acf079 0x71aa1041 0x8aeb2595 0xed90f704 + 0x7d68f5c5 0x624429d5 0xefd0d147 0xc8682f79 + 0xfe7e9cc0 0xaee6c970 0x33e9231e 0x4720df4d + 0x6a3f6428 0x463b676f 0x71960ee6 0xc684d974 + 0x9f01a6d2 0x728cbec7 0x2e20d715 0x172a4a11 + 0x4153ad1e 0xb1f36e53 0xc277f818 0x94ac6d39 + 0x502f91d8 0x3028b1ee 0x48390347 0x45a8b5af + 0x2cb8095f 0x063cbe4a 0x07a53b3b 0xcfd08c80 + 0x81679803 0x9fa4726a 0xa682f4c8 0x4d90e8bf + >; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 60bd05a..936455b 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -117,6 +117,7 @@ compatible = "intel,irq-router"; intel,pirq-config = "ibase"; intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; intel,pirq-link = <8 8>; intel,pirq-mask = <0xdee0>; intel,pirq-routing = < @@ -297,10 +298,10 @@ microcode { update@0 { -#include "microcode/m0130673322.dtsi" +#include "microcode/m0130673325.dtsi" }; update@1 { -#include "microcode/m0130679901.dtsi" +#include "microcode/m0130679907.dtsi" }; }; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 5d601b3..0d462a9 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -69,6 +69,8 @@ irq-router { compatible = "intel,irq-router"; intel,pirq-config = "pci"; + intel,actl-8bit; + intel,actl-addr = <0x44>; intel,pirq-link = <0x60 8>; intel,pirq-mask = <0x0e40>; intel,pirq-routing = < diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h deleted file mode 100644 index 4872b92..0000000 --- a/arch/x86/include/asm/acpi.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * From coreboot - * - * Copyright (C) 2004 SUSE LINUX AG - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2008-2009 coresystems GmbH - * (Written by Stefan Reinauer <stepan@coresystems.de>) - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef __ASM_ACPI_H -#define __ASM_ACPI_H - -#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ -#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */ -#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */ -#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */ - -/* 0 = S0, 1 = S1 ...*/ -int acpi_get_slp_type(void); -void apci_set_slp_type(int type); - -#endif diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl new file mode 100644 index 0000000..8e7b603 --- /dev/null +++ b/arch/x86/include/asm/acpi/debug.asl @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/debug.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* POST register region */ +OperationRegion(X80, SystemIO, 0x80, 1) +Field(X80, ByteAcc, NoLock, Preserve) +{ + P80, 8 +} + +/* Legacy serial port register region */ +OperationRegion(CREG, SystemIO, 0x3F8, 8) +Field(CREG, ByteAcc, NoLock, Preserve) +{ + CDAT, 8, + CDLM, 8, + , 8, + CLCR, 8, + CMCR, 8, + CLSR, 8 +} + +/* DINI - Initialize the serial port to 115200 8-N-1 */ +Method(DINI) +{ + Store(0x83, CLCR) + Store(0x01, CDAT) /* 115200 baud (low) */ + Store(0x00, CDLM) /* 115200 baud (high) */ + Store(0x03, CLCR) /* word=8 stop=1 parity=none */ + Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */ + Store(0x00, CDLM) /* turn off interrupts */ +} + +/* THRE - Wait for serial port transmitter holding register to go empty */ +Method(THRE) +{ + And(CLSR, 0x20, Local0) + While (LEqual(Local0, Zero)) { + And(CLSR, 0x20, Local0) + } +} + +/* OUTX - Send a single raw character */ +Method(OUTX, 1) +{ + THRE() + Store(Arg0, CDAT) +} + +/* OUTC - Send a single character, expanding LF into CR/LF */ +Method(OUTC, 1) +{ + If (LEqual(Arg0, 0x0a)) { + OUTX(0x0d) + } + OUTX(Arg0) +} + +/* DBGN - Send a single hex nibble */ +Method(DBGN, 1) +{ + And(Arg0, 0x0f, Local0) + If (LLess(Local0, 10)) { + Add(Local0, 0x30, Local0) + } Else { + Add(Local0, 0x37, Local0) + } + OUTC(Local0) +} + +/* DBGB - Send a hex byte */ +Method(DBGB, 1) +{ + ShiftRight(Arg0, 4, Local0) + DBGN(Local0) + DBGN(Arg0) +} + +/* DBGW - Send a hex word */ +Method(DBGW, 1) +{ + ShiftRight(Arg0, 8, Local0) + DBGB(Local0) + DBGB(Arg0) +} + +/* DBGD - Send a hex dword */ +Method(DBGD, 1) +{ + ShiftRight(Arg0, 16, Local0) + DBGW(Local0) + DBGW(Arg0) +} + +/* Get a char from a string */ +Method(GETC, 2) +{ + CreateByteField(Arg0, Arg1, DBGC) + Return (DBGC) +} + +/* DBGO - Send either a string or an integer */ +Method(DBGO, 1, Serialized) +{ + If (LEqual(ObjectType(Arg0), 1)) { + If (LGreater(Arg0, 0xffff)) { + DBGD(Arg0) + } Else { + If (LGreater(Arg0, 0xff)) { + DBGW(Arg0) + } Else { + DBGB(Arg0) + } + } + } Else { + Name(BDBG, Buffer(80) {}) + Store(Arg0, BDBG) + Store(0, Local1) + While (One) { + Store(GETC(BDBG, Local1), Local0) + If (LEqual(Local0, 0)) { + Return (Zero) + } + OUTC(Local0) + Increment(Local1) + } + } + + Return (Zero) +} diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl new file mode 100644 index 0000000..46381b6 --- /dev/null +++ b/arch/x86/include/asm/acpi/globutil.asl @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/globutil.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Method(MIN, 2) +{ + If (LLess(Arg0, Arg1)) { + Return (Arg0) + } Else { + Return (Arg1) + } +} + +Method(SLEN, 1) +{ + Store(Arg0, Local0) + Return (Sizeof(Local0)) +} + +Method(S2BF, 1, Serialized) +{ + Add(SLEN(Arg0), One, Local0) + Name(BUFF, Buffer(Local0) {}) + Store(Arg0, BUFF) + Return (BUFF) +} + +/* + * SCMP - Strong string compare + * + * Checks both length and content + */ +Method(SCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + Store(Zero, Local4) + Store(SLEN(Arg0), Local5) + Store(SLEN(Arg1), Local6) + Store(MIN(Local5, Local6), Local7) + + While (LLess(Local4, Local7)) { + Store(Derefof(Index(Local0, Local4)), Local2) + Store(Derefof(Index(Local1, Local4)), Local3) + If (LGreater(Local2, Local3)) { + Return (One) + } Else { + If (LLess(Local2, Local3)) { + Return (Ones) + } + } + Increment(Local4) + } + + If (LLess(Local4, Local5)) { + Return (One) + } Else { + If (LLess(Local4, Local6)) { + Return (Ones) + } Else { + Return (Zero) + } + } +} + +/* + * WCMP - Weak string compare + * + * Checks to find Arg1 at beginning of Arg0. + * Fails if length(Arg0) < length(Arg1). + * Returns 0 on fail, 1 on pass. + */ +Method(WCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + If (LLess(SLEN(Arg0), SLEN(Arg1))) { + Return (Zero) + } + Store(Zero, Local2) + Store(SLEN(Arg1), Local3) + + While (LLess(Local2, Local3)) { + If (LNotEqual(Derefof(Index(Local0, Local2)), + Derefof(Index(Local1, Local2)))) { + Return (Zero) + } + Increment(Local2) + } + + Return (One) +} + +/* + * I2BM - Returns Bit Map + * + * Arg0 = IRQ Number (0-15) + */ +Method(I2BM, 1) +{ + Store(0, Local0) + If (LNotEqual(Arg0, 0)) { + Store(1, Local1) + ShiftLeft(Local1, Arg0, Local0) + } + + Return (Local0) +} diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h new file mode 100644 index 0000000..f0b3a6b --- /dev/null +++ b/arch/x86/include/asm/acpi/irq_helper.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronics Engineering, LLC. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file intentionally gets included multiple times, to set pic and apic + * modes, so should not have guard statements added. + */ + +/* + * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ + * routing for the platform being compiled. + * + * This method uses #defines in irqroute.h along with the macros contained + * in this file to generate an IRQ routing for each PCI device in the system. + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef PCI_DEV_PIRQ_ROUTE +#undef ACPI_DEV_IRQ +#undef PCIE_BRIDGE_DEV +#undef RP_IRQ_ROUTES +#undef ROOTPORT_METHODS +#undef ROOTPORT_IRQ_ROUTES +#undef RP_METHOD + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## P, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +/* define as blank so ROOTPORT_METHODS only gets inserted once */ +#define ROOTPORT_METHODS(prefix_, dev_) + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## A, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +#define ROOTPORT_METHODS(prefix_, dev_) \ + RP_METHOD(prefix_, dev_, 0) \ + RP_METHOD(prefix_, dev_, 1) \ + RP_METHOD(prefix_, dev_, 2) \ + RP_METHOD(prefix_, dev_, 3) \ + RP_METHOD(prefix_, dev_, 4) \ + RP_METHOD(prefix_, dev_, 5) \ + RP_METHOD(prefix_, dev_, 6) \ + RP_METHOD(prefix_, dev_, 7) + +#endif /* defined(PIC_MODE) */ + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) + +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ + ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + ROOTPORT_METHODS(prefix_, dev_) + +#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ + RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) + +#define RP_METHOD(prefix_, dev_, func_)\ +Device (prefix_ ## 0 ## func_) \ +{ \ + Name(_ADR, dev_ ## 000 ## func_) \ + Name(_PRW, Package() { 0, 0 }) \ + Method(_PRT) { \ + If (PICM) { \ + Return (prefix_ ## func_ ## A) \ + } Else { \ + Return (prefix_ ## func_ ## P) \ + } \ + } \ +} + +/* SoC specific PIRQ route configuration */ +#include <asm/arch/acpi/irqroute.h> diff --git a/arch/x86/include/asm/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl new file mode 100644 index 0000000..84c1e53 --- /dev/null +++ b/arch/x86/include/asm/acpi/irqlinks.asl @@ -0,0 +1,486 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Intel chipset PIRQ routing control ASL description + * + * The programming interface is common to most Intel chipsets. But the PRTx + * registers may be mapped to different blocks. Some chipsets map them to LPC + * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while + * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy + * Block (ILB) memory space. + * + * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines + * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be + * defined somewhere else in the platform's ASL files. + */ + +Device (LNKA) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTA) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTA */ + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTA, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKB) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTB) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTB */ + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTB, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKC) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTC) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTC */ + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTC, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKD) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTD) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTD */ + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTD, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKE) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTE) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTE */ + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTE, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKF) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTF) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTF */ + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTF, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKG) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTG) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTG */ + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTG, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKH) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTH) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTH */ + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTH, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl new file mode 100644 index 0000000..64d3820 --- /dev/null +++ b/arch/x86/include/asm/acpi/irqroute.asl @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(\PICM, 0) + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local APIC/IOAPIC configuration. + */ +Method(\_PIC, 1) +{ + /* Remember the OS' IRQ routing choice */ + Store(Arg0, PICM) +} + +/* PCI interrupt routing */ +Method(_PRT) { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } + +} + +/* PCIe downstream ports interrupt routing */ +PCIE_BRIDGE_IRQ_ROUTES +#undef PIC_MODE +#include "irq_helper.h" +PCIE_BRIDGE_IRQ_ROUTES diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl new file mode 100644 index 0000000..e8cff10 --- /dev/null +++ b/arch/x86/include/asm/acpi/statdef.asl @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/arch/x86/acpi/statdef.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Status and notification definitions */ + +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0b +#define STA_UNAVAILABLE 0x0d +#define STA_VISIBLE 0x0f + +/* SMBus status codes */ +#define SMB_OK 0x00 +#define SMB_UNKNOWN_FAIL 0x07 +#define SMB_DEV_ADDR_NAK 0x10 +#define SMB_DEVICE_ERROR 0x11 +#define SMB_DEV_CMD_DENIED 0x12 +#define SMB_UNKNOWN_ERR 0x13 +#define SMB_DEV_ACC_DENIED 0x17 +#define SMB_TIMEOUT 0x18 +#define SMB_HST_UNSUPP_PROTOCOL 0x19 +#define SMB_BUSY 0x1a +#define SMB_PKT_CHK_ERROR 0x1f + +/* Device Object Notification Values */ +#define NOTIFY_BUS_CHECK 0x00 +#define NOTIFY_DEVICE_CHECK 0x01 +#define NOTIFY_DEVICE_WAKE 0x02 +#define NOTIFY_EJECT_REQUEST 0x03 +#define NOTIFY_DEVICE_CHECK_JR 0x04 +#define NOTIFY_FREQUENCY_ERROR 0x05 +#define NOTIFY_BUS_MODE 0x06 +#define NOTIFY_POWER_FAULT 0x07 +#define NOTIFY_CAPABILITIES 0x08 +#define NOTIFY_PLD_CHECK 0x09 +#define NOTIFY_SLIT_UPDATE 0x0b +#define NOTIFY_SRA_UPDATE 0x0d + +/* Battery Device Notification Values */ +#define NOTIFY_BAT_STATUSCHG 0x80 +#define NOTIFY_BAT_INFOCHG 0x81 +#define NOTIFY_BAT_MAINTDATA 0x82 + +/* Power Source Object Notification Values */ +#define NOTIFY_PWR_STATUSCHG 0x80 +#define NOTIFY_PWR_INFOCHG 0x81 + +/* Thermal Zone Object Notification Values */ +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_DEVLISTCHG 0x82 +#define NOTIFY_TZ_RELTBLCHG 0x83 + +/* Power Button Notification Values */ +#define NOTIFY_POWER_BUTTON 0x80 + +/* Sleep Button Notification Values */ +#define NOTIFY_SLEEP_BUTTON 0x80 + +/* Lid Notification Values */ +#define NOTIFY_LID_STATUSCHG 0x80 + +/* Processor Device Notification Values */ +#define NOTIFY_CPU_PPCCHG 0x80 +#define NOTIFY_CPU_CSTATECHG 0x81 +#define NOTIFY_CPU_THROTLCHG 0x82 + +/* User Presence Device Notification Values */ +#define NOTIFY_USR_PRESNCECHG 0x80 + +/* Ambient Light Sensor Notification Values */ +#define NOTIFY_ALS_ILLUMCHG 0x80 +#define NOTIFY_ALS_COLORTMPCHG 0x81 +#define NOTIFY_ALS_RESPCHG 0x82 diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 9856fa6..56aa282 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -2,83 +2,19 @@ * Based on acpi.c from coreboot * * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com> + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> -#include <malloc.h> -#include <asm/post.h> -#include <linux/string.h> - -#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ -#define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */ -#define OEM_ID "UBOOT " /* Must be 6 bytes long! */ -#define ASLC "INTL" /* Must be 4 bytes long! */ - -#define OEM_REVISION 42 -#define ASL_COMPILER_REVISION 42 - -/* IO ports to generate SMIs */ -#define APM_CNT 0xb2 -#define APM_CNT_CST_CONTROL 0x85 -#define APM_CNT_PST_CONTROL 0x80 -#define APM_CNT_ACPI_DISABLE 0x1e -#define APM_CNT_ACPI_ENABLE 0xe1 -#define APM_CNT_MBI_UPDATE 0xeb -#define APM_CNT_GNVS_UPDATE 0xea -#define APM_CNT_FINALIZE 0xcb -#define APM_CNT_LEGACY 0xcc -#define APM_ST 0xb3 - -/* Multiple Processor Interrupts */ -#define MP_IRQ_POLARITY_DEFAULT 0x0 -#define MP_IRQ_POLARITY_HIGH 0x1 -#define MP_IRQ_POLARITY_LOW 0x3 -#define MP_IRQ_POLARITY_MASK 0x3 -#define MP_IRQ_TRIGGER_DEFAULT 0x0 -#define MP_IRQ_TRIGGER_EDGE 0x4 -#define MP_IRQ_TRIGGER_LEVEL 0xc -#define MP_IRQ_TRIGGER_MASK 0xc - -/* - * Interrupt assigned for SCI in order to - * create the ACPI MADT IRQ override entry - */ -#define ACTL 0x00 -#define SCIS_MASK 0x07 -#define SCIS_IRQ9 0x00 -#define SCIS_IRQ10 0x01 -#define SCIS_IRQ11 0x02 -#define SCIS_IRQ20 0x04 -#define SCIS_IRQ21 0x05 -#define SCIS_IRQ22 0x06 -#define SCIS_IRQ23 0x07 - -#define ACPI_REV_ACPI_1_0 1 -#define ACPI_REV_ACPI_2_0 1 -#define ACPI_REV_ACPI_3_0 2 -#define ACPI_REV_ACPI_4_0 3 -#define ACPI_REV_ACPI_5_0 5 +#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ +#define OEM_ID "U-BOOT" /* U-Boot */ +#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ +#define ASLC_ID "INTL" /* Intel ASL Compiler */ #define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2 -typedef struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - union { - /* Reserved in ACPI 2.0 - 2.0b */ - u8 resv; - /* Access size in ACPI 2.0c/3.0/4.0/5.0 */ - u8 access_size; - }; - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -} acpi_addr_t; - - /* * RSDP (Root System Description Pointer) * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum @@ -87,7 +23,7 @@ struct acpi_rsdp { char signature[8]; /* RSDP signature */ u8 checksum; /* Checksum of the first 20 bytes */ char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */ + u8 revision; /* 0 for ACPI 1.0, others 2 */ u32 rsdt_address; /* Physical address of RSDT (32 bits) */ u32 length; /* Total RSDP length (incl. extended part) */ u64 xsdt_address; /* Physical address of XSDT (64 bits) */ @@ -95,35 +31,8 @@ struct acpi_rsdp { u8 reserved[3]; }; -enum acpi_address_space_type { - ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ - ACPI_ADDRESS_SPACE_IO, /* System I/O */ - ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ - ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ - ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ - ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ - ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ -}; - -/* functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ - -/* Access size definitions for Generic address structure */ -enum acpi_address_space_size { - ACPI_ACCESS_SIZE_UNDEFINED = 0, /* Undefined (legacy reasons) */ - ACPI_ACCESS_SIZE_BYTE_ACCESS = 1, - ACPI_ACCESS_SIZE_WORD_ACCESS = 2, - ACPI_ACCESS_SIZE_DWORD_ACCESS = 3, - ACPI_ACCESS_SIZE_QWORD_ACCESS = 4 -}; - /* Generic ACPI header, provided by (almost) all tables */ -typedef struct acpi_table_header { +struct acpi_table_header { char signature[4]; /* ACPI signature (4 ASCII characters) */ u32 length; /* Table length in bytes (incl. header) */ u8 revision; /* Table version (not ACPI version!) */ @@ -131,12 +40,12 @@ typedef struct acpi_table_header { char oem_id[6]; /* OEM identification */ char oem_table_id[8]; /* OEM table identification */ u32 oem_revision; /* OEM revision number */ - char asl_compiler_id[4]; /* ASL compiler vendor ID */ - u32 asl_compiler_revision; /* ASL compiler revision number */ -} acpi_header_t; + char aslc_id[4]; /* ASL compiler vendor ID */ + u32 aslc_revision; /* ASL compiler revision number */ +}; /* A maximum number of 32 ACPI tables ought to be enough for now */ -#define MAX_ACPI_TABLES 32 +#define MAX_ACPI_TABLES 32 /* RSDT (Root System Description Table) */ struct acpi_rsdt { @@ -150,103 +59,80 @@ struct acpi_xsdt { u64 entry[MAX_ACPI_TABLES]; }; -/* MCFG (PCI Express MMIO config space BAR description table) */ -struct acpi_mcfg { - struct acpi_table_header header; - u8 reserved[8]; -}; - -struct acpi_mcfg_mmconfig { - u32 base_address; - u32 base_reserved; - u16 pci_segment_group_number; - u8 start_bus_number; - u8 end_bus_number; - u8 reserved[4]; -}; - -/* MADT (Multiple APIC Description Table) */ -struct acpi_madt { - struct acpi_table_header header; - u32 lapic_addr; /* Local APIC address */ - u32 flags; /* Multiple APIC flags */ -} acpi_madt_t; - -enum dev_scope_type { - SCOPE_PCI_ENDPOINT = 1, - SCOPE_PCI_SUB = 2, - SCOPE_IOAPIC = 3, - SCOPE_MSI_HPET = 4 +/* FADT Preferred Power Management Profile */ +enum acpi_pm_profile { + ACPI_PM_UNSPECIFIED = 0, + ACPI_PM_DESKTOP, + ACPI_PM_MOBILE, + ACPI_PM_WORKSTATION, + ACPI_PM_ENTERPRISE_SERVER, + ACPI_PM_SOHO_SERVER, + ACPI_PM_APPLIANCE_PC, + ACPI_PM_PERFORMANCE_SERVER, + ACPI_PM_TABLET }; -typedef struct dev_scope { - u8 type; - u8 length; - u8 reserved[2]; - u8 enumeration; - u8 start_bus; - struct { - u8 dev; - u8 fn; - } path[0]; -} __packed dev_scope_t; - -/* MADT: APIC Structure Type*/ -enum acpi_apic_types { - LOCALAPIC = 0, /* Processor local APIC */ - IOAPIC, /* I/O APIC */ - IRQSOURCEOVERRIDE, /* Interrupt source override */ - NMITYPE, /* NMI source */ - LOCALNMITYPE, /* Local APIC NMI */ - LAPICADDRESSOVERRIDE, /* Local APIC address override */ - IOSAPIC, /* I/O SAPIC */ - LOCALSAPIC, /* Local SAPIC */ - PLATFORMIRQSOURCES, /* Platform interrupt sources */ - LOCALX2SAPIC, /* Processor local x2APIC */ - LOCALX2APICNMI, /* Local x2APIC NMI */ -}; +/* FADT flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 -/* MADT: Processor Local APIC Structure */ -struct acpi_madt_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (8) */ - u8 processor_id; /* ACPI processor ID */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Local APIC flags */ -}; +/* FADT Boot Architecture Flags */ +#define ACPI_FADT_LEGACY_FREE 0x00 +#define ACPI_FADT_LEGACY_DEVICES (1 << 0) +#define ACPI_FADT_8042 (1 << 1) +#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) +#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) +#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) -#define LOCAL_APIC_FLAG_ENABLED (1 << 0) -/* bits 1-31: reserved */ -#define PCAT_COMPAT (1 << 0) -/* bits 1-31: reserved */ +/* FADT Feature Flags */ +#define ACPI_FADT_WBINVD (1 << 0) +#define ACPI_FADT_WBINVD_FLUSH (1 << 1) +#define ACPI_FADT_C1_SUPPORTED (1 << 2) +#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) +#define ACPI_FADT_POWER_BUTTON (1 << 4) +#define ACPI_FADT_SLEEP_BUTTON (1 << 5) +#define ACPI_FADT_FIXED_RTC (1 << 6) +#define ACPI_FADT_S4_RTC_WAKE (1 << 7) +#define ACPI_FADT_32BIT_TIMER (1 << 8) +#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) +#define ACPI_FADT_RESET_REGISTER (1 << 10) +#define ACPI_FADT_SEALED_CASE (1 << 11) +#define ACPI_FADT_HEADLESS (1 << 12) +#define ACPI_FADT_SLEEP_TYPE (1 << 13) +#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) +#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) +#define ACPI_FADT_S4_RTC_VALID (1 << 16) +#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) +#define ACPI_FADT_APIC_CLUSTER (1 << 18) +#define ACPI_FADT_APIC_PHYSICAL (1 << 19) +#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) -/* MADT: Local APIC NMI Structure */ -struct acpi_madt_lapic_nmi { - u8 type; /* Type (4) */ - u8 length; /* Length in bytes (6) */ - u8 processor_id; /* ACPI processor ID */ - u16 flags; /* MPS INTI flags */ - u8 lint; /* Local APIC LINT# */ +enum acpi_address_space_type { + ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ + ACPI_ADDRESS_SPACE_IO, /* System I/O */ + ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ + ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ + ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ + ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ + ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ }; -/* MADT: I/O APIC Structure */ -struct acpi_madt_ioapic { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (12) */ - u8 ioapic_id; /* I/O APIC ID */ - u8 reserved; - u32 ioapic_addr; /* I/O APIC address */ - u32 gsi_base; /* Global system interrupt base */ +enum acpi_address_space_size { + ACPI_ACCESS_SIZE_UNDEFINED = 0, + ACPI_ACCESS_SIZE_BYTE_ACCESS, + ACPI_ACCESS_SIZE_WORD_ACCESS, + ACPI_ACCESS_SIZE_DWORD_ACCESS, + ACPI_ACCESS_SIZE_QWORD_ACCESS }; -/* MADT: Interrupt Source Override Structure */ -struct acpi_madt_irqoverride { - u8 type; /* Type (2) */ - u8 length; /* Length in bytes (10) */ - u8 bus; /* ISA (0) */ - u8 source; /* Bus-relative int. source (IRQ) */ - u32 gsirq; /* Global system interrupt */ - u16 flags; /* MPS INTI flags */ +struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ }; /* FADT (Fixed ACPI Description Table) */ @@ -254,7 +140,7 @@ struct __packed acpi_fadt { struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; + u8 res1; u8 preferred_pm_profile; u16 sci_int; u32 smi_cmd; @@ -309,85 +195,121 @@ struct __packed acpi_fadt { struct acpi_gen_regaddr x_gpe1_blk; }; -/* Flags for p_lvl2_lat and p_lvl3_lat */ -#define ACPI_FADT_C2_NOT_SUPPORTED 101 -#define ACPI_FADT_C3_NOT_SUPPORTED 1001 +/* FACS flags */ +#define ACPI_FACS_S4BIOS_F (1 << 0) +#define ACPI_FACS_64BIT_WAKE_F (1 << 1) -/* FADT Feature Flags */ -#define ACPI_FADT_WBINVD (1 << 0) -#define ACPI_FADT_WBINVD_FLUSH (1 << 1) -#define ACPI_FADT_C1_SUPPORTED (1 << 2) -#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) -#define ACPI_FADT_POWER_BUTTON (1 << 4) -#define ACPI_FADT_SLEEP_BUTTON (1 << 5) -#define ACPI_FADT_FIXED_RTC (1 << 6) -#define ACPI_FADT_S4_RTC_WAKE (1 << 7) -#define ACPI_FADT_32BIT_TIMER (1 << 8) -#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) -#define ACPI_FADT_RESET_REGISTER (1 << 10) -#define ACPI_FADT_SEALED_CASE (1 << 11) -#define ACPI_FADT_HEADLESS (1 << 12) -#define ACPI_FADT_SLEEP_TYPE (1 << 13) -#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) -#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) -#define ACPI_FADT_S4_RTC_VALID (1 << 16) -#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) -#define ACPI_FADT_APIC_CLUSTER (1 << 18) -#define ACPI_FADT_APIC_PHYSICAL (1 << 19) -/* Bits 20-31: reserved ACPI 3.0 & 4.0 */ -#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) -#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) -/* bits 22-31: reserved ACPI 5.0 */ +/* FACS (Firmware ACPI Control Structure) */ +struct acpi_facs { + char signature[4]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* Version 2 */ + u8 res1[3]; + u32 ospm_flags; /* OSPM enabled flags */ + u8 res2[24]; +}; -/* FADT Boot Architecture Flags */ -#define ACPI_FADT_LEGACY_DEVICES (1 << 0) -#define ACPI_FADT_8042 (1 << 1) -#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) -#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) -#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) -/* No legacy devices (including 8042) */ -#define ACPI_FADT_LEGACY_FREE 0x00 +/* MADT flags */ +#define ACPI_MADT_PCAT_COMPAT (1 << 0) -/* FADT Preferred Power Management Profile */ -#define PM_UNSPECIFIED 0 -#define PM_DESKTOP 1 -#define PM_MOBILE 2 -#define PM_WORKSTATION 3 -#define PM_ENTERPRISE_SERVER 4 -#define PM_SOHO_SERVER 5 -#define PM_APPLIANCE_PC 6 -#define PM_PERFORMANCE_SERVER 7 -#define PM_TABLET 8 /* ACPI 5.0 */ +/* MADT (Multiple APIC Description Table) */ +struct acpi_madt { + struct acpi_table_header header; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ +}; -/* FACS (Firmware ACPI Control Structure) */ -struct acpi_facs { - char signature[4]; /* "FACS" */ - u32 length; /* Length in bytes (>= 64) */ - u32 hardware_signature; /* Hardware signature */ - u32 firmware_waking_vector; /* Firmware waking vector */ - u32 global_lock; /* Global lock */ - u32 flags; /* FACS flags */ - u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ - u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* ACPI 4.0: 2 */ - u8 resv[31]; /* FIXME: 4.0: ospm_flags */ +/* MADT: APIC Structure Type*/ +enum acpi_apic_types { + ACPI_APIC_LAPIC = 0, /* Processor local APIC */ + ACPI_APIC_IOAPIC, /* I/O APIC */ + ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ + ACPI_APIC_NMI_SRC, /* NMI source */ + ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ + ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ + ACPI_APIC_IOSAPIC, /* I/O SAPIC */ + ACPI_APIC_LSAPIC, /* Local SAPIC */ + ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ + ACPI_APIC_LX2APIC, /* Processor local x2APIC */ + ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ }; -/* FACS flags */ -#define ACPI_FACS_S4BIOS_F (1 << 0) -#define ACPI_FACS_64BIT_WAKE_F (1 << 1) -/* Bits 31..2: reserved */ +/* MADT: Processor Local APIC Structure */ + +#define LOCAL_APIC_FLAG_ENABLED (1 << 0) + +struct acpi_madt_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ +}; + +/* MADT: I/O APIC Structure */ +struct acpi_madt_ioapic { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ + u8 reserved; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ +}; + +/* MADT: Interrupt Source Override Structure */ +struct __packed acpi_madt_irqoverride { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ +}; + +/* MADT: Local APIC NMI Structure */ +struct __packed acpi_madt_lapic_nmi { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ +}; + +/* MCFG (PCI Express MMIO config space BAR description table) */ +struct acpi_mcfg { + struct acpi_table_header header; + u8 reserved[8]; +}; + +struct acpi_mcfg_mmconfig { + u32 base_address_l; + u32 base_address_h; + u16 pci_segment_group_number; + u8 start_bus_number; + u8 end_bus_number; + u8 reserved[4]; +}; + +/* PM1_CNT bit defines */ +#define PM1_CNT_SCI_EN (1 << 0) /* These can be used by the target port */ -unsigned long acpi_create_madt_lapics(unsigned long current); -int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, - u32 gsi_base); -int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); -unsigned long acpi_fill_madt(unsigned long current); +void acpi_fill_header(struct acpi_table_header *header, char *signature); void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt); -int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + void *dsdt); +int acpi_create_madt_lapics(u32 current); +int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, + u32 addr, u32 gsi_base); +int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, + u8 bus, u8 source, u32 gsirq, u16 flags); +int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, + u8 cpu, u16 flags, u8 lint); +u32 acpi_fill_madt(u32 current); u32 write_acpi_tables(u32 start); diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl new file mode 100644 index 0000000..ef340f3 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* SouthCluster GPIO */ +Device (GPSC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 1) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* NorthCluster GPIO */ +Device (GPNC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_NC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* SUS GPIO */ +Device (GPSS) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 3) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SUS_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h new file mode 100644 index 0000000..d746314 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/device.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl new file mode 100644 index 0000000..22f0d68 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Scope (\) +{ + /* Intel Legacy Block */ + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field(ILBS, AnyAcc, NoLock, Preserve) { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + Offset (0x88), + , 3, + UI3E, 1, + UI4E, 1 + } +} + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field(LPC0, AnyAcc, NoLock, Preserve) { + Offset(0x08), + SRID, 8, + Offset(0x80), + C1EN, 1, + Offset(0x84) + } + + #include <asm/acpi/irqlinks.asl> + + /* Firmware Hub */ + Device (FWH) + { + Name(_HID, EISAID("INT0800")) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + /* 8259 Interrupt Controller */ + Device (PIC) + { + Name(_HID, EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x20, 0x20, 0x01, 0x02) + IO(Decode16, 0x24, 0x24, 0x01, 0x02) + IO(Decode16, 0x28, 0x28, 0x01, 0x02) + IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO(Decode16, 0x30, 0x30, 0x01, 0x02) + IO(Decode16, 0x34, 0x34, 0x01, 0x02) + IO(Decode16, 0x38, 0x38, 0x01, 0x02) + IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO(Decode16, 0xac, 0xac, 0x01, 0x02) + IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + /* 8254 timer */ + Device (TIMR) + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x40, 0x40, 0x01, 0x04) + IO(Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() { 0 } + }) + } + + /* HPET */ + Device (HPET) + { + Name(_HID, EISAID("PNP0103")) + Name(_CID, 0x010CD041) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) + }) + + Method(_STA) + { + Return (STA_VISIBLE) + } + } + + /* Internal UART */ + Device (IURT) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + Method(_STA, 0, Serialized) + { + /* + * TODO: + * + * Need to hide the internal UART depending on whether + * internal UART is enabled or not so that external + * SuperIO UART can be exposed to system. + */ + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + + } + + Method(_DIS, 0, Serialized) + { + Store(0, UI3E) + Store(0, UI4E) + Store(0, C1EN) + } + + Method(_CRS, 0, Serialized) + { + Name(BUF0, ResourceTemplate() + { + IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) + IRQNoFlags() { 3 } + }) + + Name(BUF1, ResourceTemplate() + { + IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) + IRQNoFlags() { 4 } + }) + + If (LLessEqual(SRID, 0x04)) { + Return (BUF0) + } Else { + Return (BUF1) + } + } + } + + /* Real Time Clock */ + Device (RTC) + { + Name(_HID, EISAID("PNP0B00")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 1, 8) + /* + * Disable as Windows doesn't like it, and systems + * don't seem to use it + */ + /* IRQNoFlags() { 8 } */ + }) + } + + /* LPC device: Resource consumption */ + Device (LDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ + }) + + Method(_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl new file mode 100644 index 0000000..6bc82ec --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/statdef.asl> +#include <asm/arch/iomap.h> +#include <asm/arch/irq.h> + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0. + */ +Method(_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ +Method(_WAK, 1) +{ + Return (Package() {0, 0}) +} + +/* TODO: add CPU ASL support */ + +Scope (\_SB) +{ + #include "southcluster.asl" + + /* ACPI devices */ + #include "gpio.asl" +} + +/* Chipset specific sleep states */ +#include "sleepstates.asl" diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl new file mode 100644 index 0000000..eb5ae76 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) +Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) +Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl new file mode 100644 index 0000000..e89ff26 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Device (PCI0) +{ + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + + Name(_ADR, 0) + Name(_BBN, 0) + + Name(MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) + + /* IO Region 0 */ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) + + /* PCI Config Space */ + IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000, , , ASEG) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000, , , OPR0) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000, , , OPR1) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000, , , OPR2) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000, , , OPR3) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000, , , OPR4) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000, , , OPR5) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000, , , OPR6) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000, , , OPR7) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000, , , ESG0) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000, , , ESG1) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000, , , ESG2) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000, , , ESG3) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000, , , FSEG) + + /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, , , PMEM) + + /* High PCI Memory Region */ + QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, , , UMEM) + }) + + Method(_CRS, 0, Serialized) + { + /* Update PCI resource area */ + CreateDwordField(MCRS, ^PMEM._MIN, PMIN) + CreateDwordField(MCRS, ^PMEM._MAX, PMAX) + CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + + /* + * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value. + * + * TODO: for generic usage, read TOLM value from register, or + * from global NVS (not implemented by U-Boot yet). + */ + Store(0x80000000, PMIN) + Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Update High PCI resource area */ + CreateQwordField(MCRS, ^UMEM._MIN, UMIN) + CreateQwordField(MCRS, ^UMEM._MAX, UMAX) + CreateQwordField(MCRS, ^UMEM._LEN, ULEN) + + /* Set base address to 48GB and allocate 16GB for PCI space */ + Store(0xc00000000, UMIN) + Store(0x400000000, ULEN) + Add(UMIN, Subtract(ULEN, 1), UMAX) + + Return (MCRS) + } + + /* Device Resource Consumption */ + Device (PDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 1) + + Name(PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + }) + + /* Current Resource Settings */ + Method(_CRS, 0, Serialized) + { + Return (PDRS) + } + } + + Method(_OSC, 4) + { + /* Check for proper GUID */ + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField(Arg3, 0, CDW1) + Or(CDW1, 4, CDW1) + Return (Arg3) + } + } + + /* LPC Bridge 0:1f.0 */ + #include "lpc.asl" + + /* USB EHCI 0:1d.0 */ + #include "usb.asl" + + /* USB XHCI 0:14.0 */ + #include "xhci.asl" + + /* IRQ routing for each PCI device */ + #include <asm/acpi/irqroute.asl> +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl new file mode 100644 index 0000000..311f471 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* EHCI Controller 0:1d.0 */ + +Device (EHC1) +{ + Name(_ADR, 0x001d0000) + + /* Power Resources for Wake */ + Name(_PRW, Package() { 13, 4 }) + + /* Highest D state in S3 state */ + Name(_S3D, 2) + + /* Highest D state in S4 state */ + Name(_S4D, 2) + + Device (HUB7) + { + Name(_ADR, 0x00000000) + + Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ + Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ + Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ + Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl new file mode 100644 index 0000000..a5a4404 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name(_ADR, 0x00140000) + + /* Power Resources for Wake */ + Name(_PRW, Package() { 13, 3 }) + + /* Highest D state in S3 state */ + Name(_S3D, 3) + + Device (RHUB) + { + Name(_ADR, 0x00000000) + + Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */ + Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */ + Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */ + Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */ + } +} diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h new file mode 100644 index 0000000..798d35b --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/device.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DEVICE_H_ +#define _DEVICE_H_ + +/* + * Internal PCI device numbers within the SoC. + * + * Note it must start with 0x_ prefix, as the device number macro will be + * included in the ACPI ASL files (see irq_helper.h and irq_route.h). + */ + +/* SoC transaction router */ +#define SOC_DEV 0x00 + +/* Graphics and Display */ +#define GFX_DEV 0x02 + +/* MIPI */ +#define MIPI_DEV 0x03 + +/* EMMC Port */ +#define EMMC_DEV 0x10 + +/* SDIO Port */ +#define SDIO_DEV 0x11 + +/* SD Port */ +#define SD_DEV 0x12 + +/* SATA */ +#define SATA_DEV 0x13 + +/* xHCI */ +#define XHCI_DEV 0x14 + +/* LPE Audio */ +#define LPE_DEV 0x15 + +/* OTG */ +#define OTG_DEV 0x16 + +/* MMC45 Port */ +#define MMC45_DEV 0x17 + +/* Serial IO 1 */ +#define SIO1_DEV 0x18 + +/* Trusted Execution Engine */ +#define TXE_DEV 0x1a + +/* HD Audio */ +#define HDA_DEV 0x1b + +/* PCIe Ports */ +#define PCIE_DEV 0x1c + +/* EHCI */ +#define EHCI_DEV 0x1d + +/* Serial IO 2 */ +#define SIO2_DEV 0x1e + +/* Platform Controller Unit */ +#define PCU_DEV 0x1f + +#endif /* _DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h new file mode 100644 index 0000000..62a9105 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/iomap.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BAYTRAIL_IOMAP_H_ +#define _BAYTRAIL_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE +#define MCFG_BASE_SIZE 0x10000000 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* IO Port bases */ +#define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h new file mode 100644 index 0000000..cd66f83 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/irq.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +/* The below IRQs are for when devices are in ACPI mode */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +#define GPIO_NC_IRQ 48 +#define GPIO_SC_IRQ 49 +#define GPIO_SUS_IRQ 50 +/* GPIO direct / dedicated IRQs */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) + +#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h new file mode 100644 index 0000000..5ba31da --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/device.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D) + +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D) diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl new file mode 100644 index 0000000..c3b0b1d --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + OperationRegion(PRTX, PCI_Config, 0x60, 8) + Field(PRTX, AnyAcc, NoLock, Preserve) { + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } + + #include <asm/acpi/irqlinks.asl> + + /* Firmware Hub */ + Device (FWH) + { + Name(_HID, EISAID("INT0800")) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + /* 8259 Interrupt Controller */ + Device (PIC) + { + Name(_HID, EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x20, 0x20, 0x01, 0x02) + IO(Decode16, 0x24, 0x24, 0x01, 0x02) + IO(Decode16, 0x28, 0x28, 0x01, 0x02) + IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO(Decode16, 0x30, 0x30, 0x01, 0x02) + IO(Decode16, 0x34, 0x34, 0x01, 0x02) + IO(Decode16, 0x38, 0x38, 0x01, 0x02) + IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO(Decode16, 0xac, 0xac, 0x01, 0x02) + IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + /* 8254 timer */ + Device (TIMR) + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x40, 0x40, 0x01, 0x04) + IO(Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() { 0 } + }) + } + + /* HPET */ + Device (HPET) + { + Name(_HID, EISAID("PNP0103")) + Name(_CID, 0x010CD041) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) + }) + + Method(_STA) + { + Return (STA_VISIBLE) + } + } + + /* Real Time Clock */ + Device (RTC) + { + Name(_HID, EISAID("PNP0B00")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 1, 8) + IRQNoFlags() { 8 } + }) + } + + /* LPC device: Resource consumption */ + Device (LDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ + }) + + Method(_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } +} diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl new file mode 100644 index 0000000..bd72842 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/statdef.asl> +#include <asm/arch/iomap.h> +#include <asm/arch/irq.h> + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0. + */ +Method(_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ +Method(_WAK, 1) +{ + Return (Package() {0, 0}) +} + +/* TODO: add CPU ASL support */ + +Scope (\_SB) +{ + #include "southcluster.asl" +} + +/* Chipset specific sleep states */ +#include "sleepstates.asl" diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl new file mode 100644 index 0000000..63c82fa --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) +Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) +Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl new file mode 100644 index 0000000..a89cfaf --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Device (PCI0) +{ + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + + Name(_ADR, 0) + Name(_BBN, 0) + + Name(MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) + + /* IO Region 0 */ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) + + /* PCI Config Space */ + IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000, , , ASEG) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000, , , OPR0) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000, , , OPR1) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000, , , OPR2) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000, , , OPR3) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000, , , OPR4) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000, , , OPR5) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000, , , OPR6) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000, , , OPR7) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000, , , ESG0) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000, , , ESG1) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000, , , ESG2) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000, , , ESG3) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000, , , FSEG) + + /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, , , PMEM) + }) + + Method(_CRS, 0, Serialized) + { + /* Update PCI resource area */ + CreateDwordField(MCRS, ^PMEM._MIN, PMIN) + CreateDwordField(MCRS, ^PMEM._MAX, PMAX) + CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + + /* + * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h) + * + * TODO: for generic usage, read TOLM value from register, or + * from global NVS (not implemented by U-Boot yet). + */ + Store(0x80000000, PMIN) + Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) + } + + /* Device Resource Consumption */ + Device (PDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 1) + + Name(PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000) + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE) + IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE) + IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE) + }) + + /* Current Resource Settings */ + Method(_CRS, 0, Serialized) + { + Return (PDRS) + } + } + + Method(_OSC, 4) + { + /* Check for proper GUID */ + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField(Arg3, 0, CDW1) + Or(CDW1, 4, CDW1) + Return (Arg3) + } + } + + /* LPC Bridge 0:1f.0 */ + #include "lpc.asl" + + /* IRQ routing for each PCI device */ + #include <asm/acpi/irqroute.asl> +} diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h index 7882f33..4760aa2 100644 --- a/arch/x86/include/asm/arch-quark/device.h +++ b/arch/x86/include/asm/arch-quark/device.h @@ -7,12 +7,17 @@ #ifndef _QUARK_DEVICE_H_ #define _QUARK_DEVICE_H_ -#include <pci.h> +/* + * Internal PCI device numbers within the SoC. + * + * Note it must start with 0x_ prefix, as the device number macro will be + * included in the ACPI ASL files (see irq_helper.h and irq_route.h). + */ -#define QUARK_HOST_BRIDGE_DEV 0 +#define QUARK_HOST_BRIDGE_DEV 0x00 #define QUARK_HOST_BRIDGE_FUNC 0 -#define QUARK_DEV_20 20 +#define QUARK_DEV_20 0x14 #define QUARK_MMC_SDIO_FUNC 0 #define QUARK_UART0_FUNC 1 #define QUARK_USB_DEVICE_FUNC 2 @@ -22,18 +27,21 @@ #define QUARK_EMAC0_FUNC 6 #define QUARK_EMAC1_FUNC 7 -#define QUARK_DEV_21 21 +#define QUARK_DEV_21 0x15 #define QUARK_SPI0_FUNC 0 #define QUARK_SPI1_FUNC 1 #define QUARK_I2C_GPIO_FUNC 2 -#define QUARK_DEV_23 23 +#define QUARK_DEV_23 0x17 #define QUARK_PCIE0_FUNC 0 #define QUARK_PCIE1_FUNC 1 -#define QUARK_LGC_BRIDGE_DEV 31 +#define QUARK_LGC_BRIDGE_DEV 0x1f #define QUARK_LGC_BRIDGE_FUNC 0 +#ifndef __ASSEMBLY__ +#include <pci.h> + #define QUARK_HOST_BRIDGE \ PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC) #define QUARK_MMC_SDIO \ @@ -64,5 +72,6 @@ PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC) #define QUARK_LEGACY_BRIDGE \ PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC) +#endif /* __ASSEMBLY__ */ #endif /* _QUARK_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h new file mode 100644 index 0000000..fd1ef98 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/iomap.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* ESRAM */ +#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE +#define ESRAM_BASE_SIZE ESRAM_SIZE + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE +#define MCFG_BASE_SIZE 0x10000000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE +#define RCBA_BASE_SIZE 0x4000 + +/* IO Port bases */ +#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE +#define ACPI_PM1_BASE_SIZE 0x10 + +#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE +#define ACPI_PBLK_BASE_SIZE 0x10 + +#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE +#define SPI_DMA_BASE_SIZE 0x10 + +#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE +#define GPIO_BASE_SIZE 0x80 + +#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE +#define ACPI_GPE0_BASE_SIZE 0x40 + +#define WDT_BASE_ADDRESS CONFIG_WDT_BASE +#define WDT_BASE_SIZE 0x40 + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h new file mode 100644 index 0000000..21e6830 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/irq.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _QUARK_IRQ_H_ +#define _QUARK_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +#endif /* _QUARK_IRQ_H_ */ diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 15ccf9b..e036f74 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -295,6 +295,25 @@ struct cbmem_entry { #define CBMEM_ID_NONE 0x00000000 /** + * high_table_reserve() - reserve configuration table in high memory + * + * This reserves configuration table in high memory. + * + * @return: always 0 + */ +int high_table_reserve(void); + +/** + * high_table_malloc() - allocate configuration table in high memory + * + * This allocates configuration table in high memory. + * + * @bytes: size of configuration table to be allocated + * @return: pointer to configuration table in high memory + */ +void *high_table_malloc(size_t bytes); + +/** * write_coreboot_table() - write coreboot table * * This writes coreboot table at a given address. diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h deleted file mode 100644 index e9450c6..0000000 --- a/arch/x86/include/asm/fw_cfg.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FW_CFG__ -#define __FW_CFG__ - -#define FW_CONTROL_PORT 0x510 -#define FW_DATA_PORT 0x511 -#define FW_DMA_PORT_LOW 0x514 -#define FW_DMA_PORT_HIGH 0x518 - -#include <linux/list.h> - -enum qemu_fwcfg_items { - FW_CFG_SIGNATURE = 0x00, - FW_CFG_ID = 0x01, - FW_CFG_UUID = 0x02, - FW_CFG_RAM_SIZE = 0x03, - FW_CFG_NOGRAPHIC = 0x04, - FW_CFG_NB_CPUS = 0x05, - FW_CFG_MACHINE_ID = 0x06, - FW_CFG_KERNEL_ADDR = 0x07, - FW_CFG_KERNEL_SIZE = 0x08, - FW_CFG_KERNEL_CMDLINE = 0x09, - FW_CFG_INITRD_ADDR = 0x0a, - FW_CFG_INITRD_SIZE = 0x0b, - FW_CFG_BOOT_DEVICE = 0x0c, - FW_CFG_NUMA = 0x0d, - FW_CFG_BOOT_MENU = 0x0e, - FW_CFG_MAX_CPUS = 0x0f, - FW_CFG_KERNEL_ENTRY = 0x10, - FW_CFG_KERNEL_DATA = 0x11, - FW_CFG_INITRD_DATA = 0x12, - FW_CFG_CMDLINE_ADDR = 0x13, - FW_CFG_CMDLINE_SIZE = 0x14, - FW_CFG_CMDLINE_DATA = 0x15, - FW_CFG_SETUP_ADDR = 0x16, - FW_CFG_SETUP_SIZE = 0x17, - FW_CFG_SETUP_DATA = 0x18, - FW_CFG_FILE_DIR = 0x19, - FW_CFG_FILE_FIRST = 0x20, - FW_CFG_WRITE_CHANNEL = 0x4000, - FW_CFG_ARCH_LOCAL = 0x8000, - FW_CFG_INVALID = 0xffff, -}; - -enum { - BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, - BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, - BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, -}; - -enum { - BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, - BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, -}; - -#define FW_CFG_FILE_SLOTS 0x10 -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) -#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) - -#define FW_CFG_MAX_FILE_PATH 56 -#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH - -#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') - -#define FW_CFG_DMA_ERROR (1 << 0) -#define FW_CFG_DMA_READ (1 << 1) -#define FW_CFG_DMA_SKIP (1 << 2) -#define FW_CFG_DMA_SELECT (1 << 3) - -#define FW_CFG_DMA_ENABLED (1 << 1) - -struct fw_cfg_file { - __be32 size; - __be16 select; - __be16 reserved; - char name[FW_CFG_MAX_FILE_PATH]; -}; - -struct fw_file { - struct fw_cfg_file cfg; /* firmware file information */ - unsigned long addr; /* firmware file in-memory address */ - struct list_head list; /* list node to link to fw_list */ -}; - -struct fw_cfg_dma_access { - __be32 control; - __be32 length; - __be64 address; -}; - -struct bios_linker_entry { - __le32 command; - union { - /* - * COMMAND_ALLOCATE - allocate a table from @alloc.file - * subject to @alloc.align alignment (must be power of 2) - * and @alloc.zone (can be HIGH or FSEG) requirements. - * - * Must appear exactly once for each file, and before - * this file is referenced by any other command. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 align; - uint8_t zone; - } alloc; - - /* - * COMMAND_ADD_POINTER - patch the table (originating from - * @dest_file) at @pointer.offset, by adding a pointer to the - * table originating from @src_file. 1,2,4 or 8 byte unsigned - * addition is used depending on @pointer.size. - */ - struct { - char dest_file[BIOS_LINKER_LOADER_FILESZ]; - char src_file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - uint8_t size; - } pointer; - - /* - * COMMAND_ADD_CHECKSUM - calculate checksum of the range - * specified by @cksum_start and @cksum_length fields, - * and then add the value at @cksum.offset. - * Checksum simply sums -X for each byte X in the range - * using 8-bit math. - */ - struct { - char file[BIOS_LINKER_LOADER_FILESZ]; - __le32 offset; - __le32 start; - __le32 length; - } cksum; - - /* padding */ - char pad[124]; - }; -} __packed; - -/** - * Initialize QEMU fw_cfg interface - */ -void qemu_fwcfg_init(void); - -/** - * Get system cpu number - * - * @return: cpu number in system - */ -int qemu_fwcfg_online_cpus(void); - -#endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3bc2ac2..7434f77 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,10 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ +#ifdef CONFIG_SEABIOS + u32 high_table_ptr; + u32 high_table_limit; +#endif }; #endif diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 5b9e673..ddb529e 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -34,6 +34,8 @@ enum pirq_config { * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address + * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) + * @actl_addr: ACTL register offset */ struct irq_router { int config; @@ -41,6 +43,8 @@ struct irq_router { u16 irq_mask; u32 bdf; u32 ibase; + bool actl_8bit; + int actl_addr; }; struct pirq_routing { diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index dc90df2..e17f0bb 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,7 +10,7 @@ obj-y += bios_asm.o obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o -obj-y += coreboot_table.o +obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-$(CONFIG_EFI) += efi/ obj-y += e820.o obj-y += gcc.o @@ -31,7 +31,7 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += sfi.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o -ifndef CONFIG_QEMU_ACPI_TABLE +ifndef CONFIG_QEMU obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 790f6fb..ffb4678 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -2,6 +2,7 @@ * Based on acpi.c from coreboot * * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com> + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,25 +11,92 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> -#include <dm/lists.h> #include <asm/acpi_table.h> -#include <asm/cpu.h> -#include <asm/ioapic.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/tables.h> -#include <asm/pci.h> /* - * IASL compiles the dsdt entries and - * writes the hex values to AmlCode array. - * CamelCase cannot be handled here. + * IASL compiles the dsdt entries and writes the hex values + * to a C array AmlCode[] (see dsdt.c). */ extern const unsigned char AmlCode[]; +static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, + struct acpi_xsdt *xsdt) +{ + memset(rsdp, 0, sizeof(struct acpi_rsdp)); + + memcpy(rsdp->signature, RSDP_SIG, 8); + memcpy(rsdp->oem_id, OEM_ID, 6); + + rsdp->length = sizeof(struct acpi_rsdp); + rsdp->rsdt_address = (u32)rsdt; + + /* + * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2 + * + * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2. + * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR + * revision 0) + */ + if (xsdt == NULL) { + rsdp->revision = ACPI_RSDP_REV_ACPI_1_0; + } else { + rsdp->xsdt_address = (u64)(u32)xsdt; + rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; + } + + /* Calculate checksums */ + rsdp->checksum = table_compute_checksum((void *)rsdp, 20); + rsdp->ext_checksum = table_compute_checksum((void *)rsdp, + sizeof(struct acpi_rsdp)); +} + +void acpi_fill_header(struct acpi_table_header *header, char *signature) +{ + memcpy(header->signature, signature, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->aslc_id, ASLC_ID, 4); +} + +static void acpi_write_rsdt(struct acpi_rsdt *rsdt) +{ + struct acpi_table_header *header = &(rsdt->header); + + /* Fill out header fields */ + acpi_fill_header(header, "RSDT"); + header->length = sizeof(struct acpi_rsdt); + header->revision = 1; + + /* Entries are filled in later, we come with an empty set */ + + /* Fix checksum */ + header->checksum = table_compute_checksum((void *)rsdt, + sizeof(struct acpi_rsdt)); +} + +static void acpi_write_xsdt(struct acpi_xsdt *xsdt) +{ + struct acpi_table_header *header = &(xsdt->header); + + /* Fill out header fields */ + acpi_fill_header(header, "XSDT"); + header->length = sizeof(struct acpi_xsdt); + header->revision = 1; + + /* Entries are filled in later, we come with an empty set */ + + /* Fix checksum */ + header->checksum = table_compute_checksum((void *)xsdt, + sizeof(struct acpi_xsdt)); +} + /** -* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length -* and checksum. -*/ + * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length + * and checksum. + */ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) { int i, entries_num; @@ -50,7 +118,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) } if (i >= entries_num) { - debug("ACPI: Error: too many tables.\n"); + debug("ACPI: Error: too many tables\n"); return; } @@ -58,12 +126,13 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) rsdt->entry[i] = (u32)table; /* Fix RSDT length or the kernel will assume invalid entries */ - rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1)); + rsdt->header.length = sizeof(struct acpi_table_header) + + (sizeof(u32) * (i + 1)); /* Re-calculate checksum */ rsdt->header.checksum = 0; rsdt->header.checksum = table_compute_checksum((u8 *)rsdt, - rsdt->header.length); + rsdt->header.length); /* * And now the same thing for the XSDT. We use the same index as for @@ -74,8 +143,8 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) xsdt->entry[i] = (u64)(u32)table; /* Fix XSDT length */ - xsdt->header.length = sizeof(acpi_header_t) + - (sizeof(u64) * (i + 1)); + xsdt->header.length = sizeof(struct acpi_table_header) + + (sizeof(u64) * (i + 1)); /* Re-calculate checksum */ xsdt->header.checksum = 0; @@ -84,38 +153,56 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) } } +static void acpi_create_facs(struct acpi_facs *facs) +{ + memset((void *)facs, 0, sizeof(struct acpi_facs)); + + memcpy(facs->signature, "FACS", 4); + facs->length = sizeof(struct acpi_facs); + facs->hardware_signature = 0; + facs->firmware_waking_vector = 0; + facs->global_lock = 0; + facs->flags = 0; + facs->x_firmware_waking_vector_l = 0; + facs->x_firmware_waking_vector_h = 0; + facs->version = 1; +} + static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic, - u8 cpu, u8 apic) + u8 cpu, u8 apic) { - lapic->type = LOCALAPIC; /* Local APIC structure */ + lapic->type = ACPI_APIC_LAPIC; lapic->length = sizeof(struct acpi_madt_lapic); - lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */ + lapic->flags = LOCAL_APIC_FLAG_ENABLED; lapic->processor_id = cpu; lapic->apic_id = apic; return lapic->length; } -unsigned long acpi_create_madt_lapics(unsigned long current) +int acpi_create_madt_lapics(u32 current) { struct udevice *dev; + int length = 0; for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { struct cpu_platdata *plat = dev_get_parent_platdata(dev); - current += acpi_create_madt_lapic( + length += acpi_create_madt_lapic( (struct acpi_madt_lapic *)current, plat->cpu_id, plat->cpu_id); - } - return current; + current += length; + } + + return length; } -int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, - u32 gsi_base) +int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, + u32 addr, u32 gsi_base) { - ioapic->type = IOAPIC; + ioapic->type = ACPI_APIC_IOAPIC; ioapic->length = sizeof(struct acpi_madt_ioapic); ioapic->reserved = 0x00; ioapic->gsi_base = gsi_base; @@ -126,9 +213,9 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, } int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags) + u8 bus, u8 source, u32 gsirq, u16 flags) { - irqoverride->type = IRQSOURCEOVERRIDE; + irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE; irqoverride->length = sizeof(struct acpi_madt_irqoverride); irqoverride->bus = bus; irqoverride->source = source; @@ -139,9 +226,9 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, } int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, - u8 cpu, u16 flags, u8 lint) + u8 cpu, u16 flags, u8 lint) { - lapic_nmi->type = LOCALNMITYPE; + lapic_nmi->type = ACPI_APIC_LAPIC_NMI; lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi); lapic_nmi->flags = flags; lapic_nmi->processor_id = cpu; @@ -150,45 +237,35 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, return lapic_nmi->length; } -static void fill_header(acpi_header_t *header, char *signature, int length) -{ - memcpy(header->signature, signature, length); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); -} - static void acpi_create_madt(struct acpi_madt *madt) { - acpi_header_t *header = &(madt->header); - unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt); + struct acpi_table_header *header = &(madt->header); + u32 current = (u32)madt + sizeof(struct acpi_madt); memset((void *)madt, 0, sizeof(struct acpi_madt)); /* Fill out header fields */ - fill_header(header, "APIC", 4); + acpi_fill_header(header, "APIC"); header->length = sizeof(struct acpi_madt); - - /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ - header->revision = ACPI_REV_ACPI_2_0; + header->revision = 4; madt->lapic_addr = LAPIC_DEFAULT_BASE; - madt->flags = PCAT_COMPAT; + madt->flags = ACPI_MADT_PCAT_COMPAT; current = acpi_fill_madt(current); /* (Re)calculate length and checksum */ - header->length = current - (unsigned long)madt; + header->length = current - (u32)madt; header->checksum = table_compute_checksum((void *)madt, header->length); } static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, - u32 base, u16 seg_nr, u8 start, u8 end) + u32 base, u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); - mmconfig->base_address = base; - mmconfig->base_reserved = 0; + mmconfig->base_address_l = base; + mmconfig->base_address_h = 0; mmconfig->pci_segment_group_number = seg_nr; mmconfig->start_bus_number = start; mmconfig->end_bus_number = end; @@ -196,11 +273,11 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, return sizeof(struct acpi_mcfg_mmconfig); } -static unsigned long acpi_fill_mcfg(unsigned long current) +static u32 acpi_fill_mcfg(u32 current) { current += acpi_create_mcfg_mmconfig ((struct acpi_mcfg_mmconfig *)current, - CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255); + CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255); return current; } @@ -208,132 +285,45 @@ static unsigned long acpi_fill_mcfg(unsigned long current) /* MCFG is defined in the PCI Firmware Specification 3.0 */ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) { - acpi_header_t *header = &(mcfg->header); - unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg); + struct acpi_table_header *header = &(mcfg->header); + u32 current = (u32)mcfg + sizeof(struct acpi_mcfg); memset((void *)mcfg, 0, sizeof(struct acpi_mcfg)); /* Fill out header fields */ - fill_header(header, "MCFG", 4); + acpi_fill_header(header, "MCFG"); header->length = sizeof(struct acpi_mcfg); - - /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ - header->revision = ACPI_REV_ACPI_2_0; + header->revision = 1; current = acpi_fill_mcfg(current); /* (Re)calculate length and checksum */ - header->length = current - (unsigned long)mcfg; + header->length = current - (u32)mcfg; header->checksum = table_compute_checksum((void *)mcfg, header->length); } -static void acpi_create_facs(struct acpi_facs *facs) -{ - memset((void *)facs, 0, sizeof(struct acpi_facs)); - - memcpy(facs->signature, "FACS", 4); - facs->length = sizeof(struct acpi_facs); - facs->hardware_signature = 0; - facs->firmware_waking_vector = 0; - facs->global_lock = 0; - facs->flags = 0; - facs->x_firmware_waking_vector_l = 0; - facs->x_firmware_waking_vector_h = 0; - facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ -} - -static void acpi_write_rsdt(struct acpi_rsdt *rsdt) -{ - acpi_header_t *header = &(rsdt->header); - - /* Fill out header fields */ - fill_header(header, "RSDT", 4); - header->length = sizeof(struct acpi_rsdt); - - /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ - header->revision = ACPI_REV_ACPI_2_0; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)rsdt, - sizeof(struct acpi_rsdt)); -} - -static void acpi_write_xsdt(struct acpi_xsdt *xsdt) +static void enter_acpi_mode(int pm1_cnt) { - acpi_header_t *header = &(xsdt->header); - - /* Fill out header fields */ - fill_header(header, "XSDT", 4); - header->length = sizeof(struct acpi_xsdt); - - /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ - header->revision = ACPI_REV_ACPI_2_0; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)xsdt, - sizeof(struct acpi_xsdt)); -} - -static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, - struct acpi_xsdt *xsdt) -{ - memset(rsdp, 0, sizeof(struct acpi_rsdp)); - - memcpy(rsdp->signature, RSDP_SIG, 8); - memcpy(rsdp->oem_id, OEM_ID, 6); - - rsdp->length = sizeof(struct acpi_rsdp); - rsdp->rsdt_address = (u32)rsdt; - /* - * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2 - * - * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2. - * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR - * revision 0) - */ - if (xsdt == NULL) { - rsdp->revision = ACPI_RSDP_REV_ACPI_1_0; - } else { - rsdp->xsdt_address = (u64)(u32)xsdt; - rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; - } - - /* Calculate checksums */ - rsdp->checksum = table_compute_checksum((void *)rsdp, 20); - rsdp->ext_checksum = table_compute_checksum((void *)rsdp, - sizeof(struct acpi_rsdp)); -} - -static void acpi_create_ssdt_generator(acpi_header_t *ssdt, - const char *oem_table_id) -{ - unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); - - memset((void *)ssdt, 0, sizeof(acpi_header_t)); - - memcpy(&ssdt->signature, "SSDT", 4); - /* Access size in ACPI 2.0c/3.0/4.0/5.0 */ - ssdt->revision = ACPI_REV_ACPI_3_0; - memcpy(&ssdt->oem_id, OEM_ID, 6); - memcpy(&ssdt->oem_table_id, oem_table_id, 8); - ssdt->oem_revision = OEM_REVISION; - memcpy(&ssdt->asl_compiler_id, ASLC, 4); - ssdt->asl_compiler_revision = ASL_COMPILER_REVISION; - ssdt->length = sizeof(acpi_header_t); - - /* (Re)calculate length and checksum */ - ssdt->length = current - (unsigned long)ssdt; - ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); + * PM1_CNT register bit0 selects the power management event to be + * either an SCI or SMI interrupt. When this bit is set, then power + * management events will generate an SCI interrupt. When this bit + * is reset power management events will generate an SMI interrupt. + * + * Per ACPI spec, it is the responsibility of the hardware to set + * or reset this bit. OSPM always preserves this bit position. + * + * U-Boot does not support SMI. And we don't have plan to support + * anything running in SMM within U-Boot. To create a legacy-free + * system, and expose ourselves to OSPM as working under ACPI mode + * already, turn this bit on. + */ + outw(PM1_CNT_SCI_EN, pm1_cnt); } /* * QEMU's version of write_acpi_tables is defined in - * arch/x86/cpu/qemu/fw_cfg.c + * arch/x86/cpu/qemu/acpi_table.c */ u32 write_acpi_tables(u32 start) { @@ -342,18 +332,17 @@ u32 write_acpi_tables(u32 start) struct acpi_rsdt *rsdt; struct acpi_xsdt *xsdt; struct acpi_facs *facs; - acpi_header_t *dsdt; + struct acpi_table_header *dsdt; struct acpi_fadt *fadt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; - acpi_header_t *ssdt; current = start; - /* Align ACPI tables to 16byte */ + /* Align ACPI tables to 16 byte */ current = ALIGN(current, 16); - debug("ACPI: Writing ACPI tables at %lx.\n", start); + debug("ACPI: Writing ACPI tables at %x\n", start); /* We need at least an RSDP and an RSDT Table */ rsdp = (struct acpi_rsdp *)current; @@ -364,7 +353,11 @@ u32 write_acpi_tables(u32 start) current = ALIGN(current, 16); xsdt = (struct acpi_xsdt *)current; current += sizeof(struct acpi_xsdt); - current = ALIGN(current, 16); + /* + * Per ACPI spec, the FACS table address must be aligned to a 64 byte + * boundary (Windows checks this, but Linux does not). + */ + current = ALIGN(current, 64); /* clear all table memory */ memset((void *)start, 0, current - start); @@ -381,21 +374,13 @@ u32 write_acpi_tables(u32 start) acpi_create_facs(facs); debug("ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - if (dsdt->length >= sizeof(acpi_header_t)) { - current += sizeof(acpi_header_t); - memcpy((char *)current, - (char *)&AmlCode + sizeof(acpi_header_t), - dsdt->length - sizeof(acpi_header_t)); - current += dsdt->length - sizeof(acpi_header_t); - - /* (Re)calculate length and checksum */ - dsdt->length = current - (unsigned long)dsdt; - dsdt->checksum = 0; - dsdt->checksum = table_compute_checksum((void *)dsdt, - dsdt->length); - } + dsdt = (struct acpi_table_header *)current; + memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); + current += sizeof(struct acpi_table_header); + memcpy((char *)current, + (char *)&AmlCode + sizeof(struct acpi_table_header), + dsdt->length - sizeof(struct acpi_table_header)); + current += dsdt->length - sizeof(struct acpi_table_header); current = ALIGN(current, 16); debug("ACPI: * FADT\n"); @@ -405,36 +390,29 @@ u32 write_acpi_tables(u32 start) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); - debug("ACPI: * MCFG\n"); - mcfg = (struct acpi_mcfg *)current; - acpi_create_mcfg(mcfg); - if (mcfg->header.length > sizeof(struct acpi_mcfg)) { - current += mcfg->header.length; - current = ALIGN(current, 16); - acpi_add_table(rsdp, mcfg); - } - debug("ACPI: * MADT\n"); madt = (struct acpi_madt *)current; acpi_create_madt(madt); - if (madt->header.length > sizeof(struct acpi_madt)) { - current += madt->header.length; - acpi_add_table(rsdp, madt); - } + current += madt->header.length; + acpi_add_table(rsdp, madt); current = ALIGN(current, 16); - debug("ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length > sizeof(acpi_header_t)) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - current = ALIGN(current, 16); - } + debug("ACPI: * MCFG\n"); + mcfg = (struct acpi_mcfg *)current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + current = ALIGN(current, 16); + + debug("current = %x\n", current); - debug("current = %lx\n", current); + debug("ACPI: done\n"); - debug("ACPI: done.\n"); + /* + * Other than waiting for OSPM to request us to switch to ACPI mode, + * do it by ourselves, since SMI will not be triggered. + */ + enter_acpi_mode(fadt->pm1a_cnt_blk); return current; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 783be69..7cf9de4 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -26,14 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; #define COMMAND_LINE_OFFSET 0x9000 -/* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. - */ -__weak void board_final_cleanup(void) -{ -} - void bootm_announce_and_cleanup(void) { printf("\nStarting kernel ...\n\n"); @@ -45,7 +37,6 @@ void bootm_announce_and_cleanup(void) #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif - board_final_cleanup(); } #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index cb45a79..ceab3cf 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -9,6 +9,37 @@ #include <asm/coreboot_tables.h> #include <asm/e820.h> +DECLARE_GLOBAL_DATA_PTR; + +int high_table_reserve(void) +{ + /* adjust stack pointer to reserve space for configuration tables */ + gd->arch.high_table_limit = gd->start_addr_sp; + gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE; + gd->arch.high_table_ptr = gd->start_addr_sp; + + /* clear the memory */ + memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE); + + gd->start_addr_sp &= ~0xf; + + return 0; +} + +void *high_table_malloc(size_t bytes) +{ + u32 new_ptr; + void *ptr; + + new_ptr = gd->arch.high_table_ptr + bytes; + if (new_ptr >= gd->arch.high_table_limit) + return NULL; + ptr = (void *)gd->arch.high_table_ptr; + gd->arch.high_table_ptr = new_ptr; + + return ptr; +} + /** * cb_table_init() - initialize a coreboot table header * diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 3cc6adb..a93d355 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -10,7 +10,6 @@ #include <pci.h> #include <asm/pci.h> #include <asm/pirq_routing.h> -#include <asm/tables.h> static bool irq_already_routed[16]; @@ -111,9 +110,6 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) { struct irq_routing_table *rom_rt; - /* Fix up the table checksum */ - rt->checksum = table_compute_checksum(rt, rt->size); - /* Align the table to be 16 byte aligned */ addr = ALIGN(addr, 16); diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c index 441fca9..9f30550 100644 --- a/arch/x86/lib/smbios.c +++ b/arch/x86/lib/smbios.c @@ -105,8 +105,8 @@ static int smbios_write_type1(u32 *current, int handle) memset(t, 0, sizeof(struct smbios_type1)); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); - t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); + t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME); len = t->length + smbios_string_table_len(t->eos); *current += len; @@ -121,8 +121,8 @@ static int smbios_write_type2(u32 *current, int handle) memset(t, 0, sizeof(struct smbios_type2)); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); - t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); + t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; @@ -139,7 +139,7 @@ static int smbios_write_type3(u32 *current, int handle) memset(t, 0, sizeof(struct smbios_type3)); fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); - t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER); t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index a156f2c..f92111e 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -80,9 +80,8 @@ void write_tables(void) #ifdef CONFIG_SEABIOS table_size = rom_table_end - rom_table_start; - high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size); + high_table = (u32)high_table_malloc(table_size); if (high_table) { - memset((void *)high_table, 0, table_size); table_write_funcs[i](high_table); cfg_tables[i].start = high_table; |